; -------------------------------------------------------------------------------- ; @Title: STM32H7x On-Chip Peripherals ; @Props: Released ; @Author: DAS, JMI, DLI, KMB, KWI, RSA, NEJ ; @Changelog: 2019-07-11 KMB ; 2020-07-23 KWI ; 2021-06-14 KWI ; 2021-12-06 RSA ; 2022-05-25 NEJ ; 2023-09-20 NEJ ; 2024-01-24 NEJ ; @Manufacturer: STM - ST Microelectronics N.V. ; @Doc: Generated (TRACE32, build: 166176.), based on: ; STM32H723.svd (Ver. 1.6), STM32H725.svd (Ver. 1.5), ; STM32H730.svd (Ver. 1.2), STM32H733.svd (Ver. 1.2), ; STM32H735.svd (Ver. 1.2), STM32H742.svd (Ver. 1.8), ; STM32H743.svd (Ver. 1.8), STM32H745_CM4.svd (Ver. 2.0), ; STM32H745_CM7.svd (Ver. 2.0), STM32H747_CM4.svd (Ver. 1.8), ; STM32H747_CM7.svd (Ver. 1.8), STM32H750.svd (Ver. 2.2), ; STM32H753.svd (Ver. 1.9), STM32H755_CM4.svd (Ver. 2.0), ; STM32H755_CM7.svd (Ver. 2.0), STM32H757_CM4.svd (Ver. 1.8), ; STM32H757_CM7.svd (Ver. 1.8), STM32H7A3.svd (Ver. 2.7), ; STM32H7B0.svd (Ver. 1.7), STM32H7B3.svd (Ver. 2.7) ; @Core: Cortex-M7F, Cortex-M4F ; @Chip: STM32H723VE, STM32H723VG, STM32H723ZE, STM32H723ZG, STM32H730AB, ; STM32H730IB, STM32H730VB, STM32H730ZB, STM32H733VG, STM32H733ZG, ; STM32H735AG, STM32H735IG, STM32H735RG, STM32H735VG, STM32H735ZG, ; STM32H742AG, STM32H742AI, STM32H742BG, STM32H742BI, STM32H742IG, ; STM32H742II, STM32H742VG, STM32H742VI, STM32H742XG, STM32H742XI, ; STM32H742ZG, STM32H742ZI, STM32H743AG, STM32H743AI, STM32H743BG, ; STM32H743BI, STM32H743IG, STM32H743II, STM32H743VG, STM32H743VI, ; STM32H743XG, STM32H743XI, STM32H743ZG, STM32H743ZI, STM32H745BG-CM4, ; STM32H745BG-CM7, STM32H745BI-CM4, STM32H745BI-CM7, STM32H745IG-CM4, STM32H745IG-CM7, ; STM32H745II-CM4, STM32H745II-CM7, STM32H745XG-CM4, STM32H745XG-CM7, STM32H745XI-CM4, ; STM32H745XI-CM7, STM32H745ZG-CM4, STM32H745ZG-CM7, STM32H745ZI-CM4, STM32H745ZI-CM7, ; STM32H747AG-CM4, STM32H747AG-CM7, STM32H747AI-CM4, STM32H747AI-CM7, STM32H747BG-CM4, ; STM32H747BG-CM7, STM32H747BI-CM4, STM32H747BI-CM7, STM32H747IG-CM4, STM32H747IG-CM7, ; STM32H747II-CM4, STM32H747II-CM7, STM32H747XG-CM4, STM32H747XG-CM7, STM32H747XI-CM4, ; STM32H747XI-CM7, STM32H747ZI-CM4, STM32H747ZI-CM7, STM32H750IB, STM32H750VB, ; STM32H750XB, STM32H753AI, STM32H753BI, STM32H753II, STM32H753VI, ; STM32H753XI, STM32H753ZI, STM32H755BI-CM4, STM32H755BI-CM7, STM32H755II-CM4, ; STM32H755II-CM7, STM32H755XI-CM4, STM32H755XI-CM7, STM32H755ZI-CM4, STM32H755ZI-CM7, ; STM32H757AI-CM4, STM32H757AI-CM7, STM32H757BI-CM4, STM32H757BI-CM7, STM32H757II-CM4, ; STM32H757II-CM7, STM32H757XI-CM4, STM32H757XI-CM7, STM32H757ZI-CM4, STM32H757ZI-CM7, ; STM32H7A3AG, STM32H7A3AI, STM32H7A3IG, STM32H7A3II, STM32H7A3LG, ; STM32H7A3LI, STM32H7A3NG, STM32H7A3NI, STM32H7A3RG, STM32H7A3RI, ; STM32H7A3VG, STM32H7A3VI, STM32H7A3ZG, STM32H7A3ZI, STM32H7B0AB, ; STM32H7B0IB, STM32H7B0RB, STM32H7B3AI, STM32H7B3II, STM32H7B3LI, ; STM32H7B3NI, STM32H7B3RI, STM32H7B0VB, STM32H7B3VI, STM32H7B0ZB, ; STM32H7B3ZI ; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perstm32h7x.per 17392 2024-01-25 14:23:21Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXM7F") tree.close "Core Registers (Cortex-M7F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes" bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes" bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes" textline " " bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..." bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes" textline " " bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes" bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes" bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes" textline " " bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes" bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes" textline "" group.long 0x10++0x03 line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" group.long 0x14++0x07 line.long 0x00 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x04 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPUID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..." group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control and State Register" bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active" setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending" textline " " rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled" rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt" textline " " rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent" hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key" rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian" bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration and Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored" bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled" bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x13 line.long 0x00 "HFSR,HardFault Status Register" eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred" eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred" eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred" eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred" eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred" line.long 0x08 "MMFAR,MemManage Fault Address Register" line.long 0x0C "BFAR,BusFault Address Register" line.long 0x10 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Triggered Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" tree "Memory System" width 10. rgroup.long 0xD78++0x0B line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..." bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..." bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..." bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..." textline " " bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..." bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..." bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..." line.long 0x04 "CTR,Cache Type Register" bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..." bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..." bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..." textline " " bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "CCSIDR,Cache Size ID Register" bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported" bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported" bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported" textline " " bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported" hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1" hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1" textline " " bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512" group.long 0xD84++0x03 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..." bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction" wgroup.long 0xF50++0x03 line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification" wgroup.long 0xF58++0x1F line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU" line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)" line.long 0x08 "DCISW,Data cache invalidate by set/way" line.long 0x0C "DCCMVAU,Data cache by address to PoU" line.long 0x10 "DCCMVAC,Data cache clean by address to PoC" line.long 0x14 "DCCSW,Data cache clean by set/way" line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC" line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way" group.long 0xF90++0x13 line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register" bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register" bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB" bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled" bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled" line.long 0x08 "AHBPCR,AHBP control register" bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..." bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled" line.long 0x0C "CACR,L1 Cache Control Register" bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled" bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes" bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled" line.long 0x10 "AHBSCR,AHB Slave Control Register" bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion" bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI" group.long 0xFA8++0x03 line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register" bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR" bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred" bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred" bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred" bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred" group.long 0xFB0++0x03 line.long 0x00 "IEBR0,Instruction Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB4++0x03 line.long 0x00 "IEBR1,Instruction Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFB8++0x03 line.long 0x00 "DEBR0,Data Error bank Register 0" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" group.long 0xFBC++0x03 line.long 0x00 "DEBR1,Data Error bank Register 1" bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3" bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable" bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data" textline " " hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM" bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked" bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid" tree.end tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end tree "CoreSight Identification Registers" width 6. rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM7F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" newline bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" newline bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" newline bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x0B line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." newline bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." newline bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." newline bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." line.long 0x08 "MVFR2,Media and FP Feature Register 2" bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..." width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x03 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" newline if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" newline rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" newline bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" newline bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" newline bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" newline bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count register" line.long 0x08 "DWT_CPICNT,CPI Count register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" newline group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" newline textfld " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXM4F") tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif tree "ADC (Analog-to-Digital Converter)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "ADC1" base ad:0x40022000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x0++0x27 line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,ADC LDO output voltage ready bit" "0: ADC LDO voltage regulator disabled,1: ADC LDO voltage regulator enabled" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" newline bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" newline bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" newline bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" newline bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" newline bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Writing ADCAL will launch a calibration in..,1: Writing ADCAL will launch a calibration in.." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in deep-power down,1: ADC in deep-power-down (default reset state)" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." newline bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word 6" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word 5" "0,1" newline bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word 4" "0,1" bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word 3" "0,1" newline bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word 2" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word 1" "0,1" newline bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0: Writing ADCAL will launch a calibration without..,1: Writing ADCAL will launch a calibration with he.." bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0: used when ADC clock <= 6.25 MHz,1: used when 6.25 MHz < ADC clock frequency <= 12.5..,2: used when 12.5 MHz < ADC clock frequency <= 25.0..,3: used when 25.0 MHz < ADC clock <= 50.0 MHz" newline bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." newline bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." newline bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0: Injected Queue enabled,1: Injected Queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR Mode 0: The Queue is never empty and..,1: JSQR Mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun Mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--4. "RES,Data resolution" "0: 16 bits,1: 14 bits in legacy mode (not optimized power..,2: 12 bits in legacy mode (not optimized power..,3: 10 bits,?,5: 14 bits,6: 12 bits,7: 8 bits" newline bitfld.long 0xC 0.--1. "DMNGT,Data Management configuration" "0: Regular conversion data stored in DR only,1: DMA One Shot Mode selected,2: DFSDM mode selected,3: DMA Circular Mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSVR,Oversampling ratio" newline bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4 correction" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3 correction" "0,1" newline bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2 correction" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1 correction" "0: Right-shifting disabled,1: Data is right-shifted 1-bit." newline bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling right shift" bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected Oversampling disabled,1: Injected Oversampling enabled" newline bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 18. "PCSEL18,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 17. "PCSEL17,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 16. "PCSEL16,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 15. "PCSEL15,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 14. "PCSEL14,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 13. "PCSEL13,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 12. "PCSEL12,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 11. "PCSEL11,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 10. "PCSEL10,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 9. "PCSEL9,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 8. "PCSEL8,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 7. "PCSEL7,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 6. "PCSEL6,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 5. "PCSEL5,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 4. "PCSEL4,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 3. "PCSEL3,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 2. "PCSEL2,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 1. "PCSEL1,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 0. "PCSEL0,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." line.long 0x20 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x20 0.--25. 1. "LTR1,Analog watchdog 1 lower threshold" line.long 0x24 "ADC_HTR1,ADC watchdog threshold register 1" hexmask.long 0x24 0.--25. 1. "HTR1,Analog watchdog 1 higher threshold" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular Data converted" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: If JQDIS=0 (queue enabled) Hardware and software..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" group.long 0x60++0xF line.long 0x0 "ADC_OFR1,ADC injected channel 1 offset register" bitfld.long 0x0 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,Channel selection for the Data offset y" newline hexmask.long 0x0 0.--25. 1. "OFFSET1,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" line.long 0x4 "ADC_OFR2,ADC injected channel 2 offset register" bitfld.long 0x4 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,Channel selection for the Data offset y" newline hexmask.long 0x4 0.--25. 1. "OFFSET2,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" line.long 0x8 "ADC_OFR3,ADC injected channel 3 offset register" bitfld.long 0x8 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,Channel selection for the Data offset y" newline hexmask.long 0x8 0.--25. 1. "OFFSET3,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" line.long 0xC "ADC_OFR4,ADC injected channel 4 offset register" bitfld.long 0xC 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,Channel selection for the Data offset y" newline hexmask.long 0xC 0.--25. 1. "OFFSET4,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" group.long 0xB0++0x1B line.long 0x0 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower threshold" line.long 0x4 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher threshold" line.long 0x8 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower threshold" line.long 0xC "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher threshold" line.long 0x10 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x10 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0" line.long 0x14 "ADC_CALFACT,ADC calibration factors register" hexmask.long.word 0x14 16.--26. 1. "CALFACT_D,Calibration Factors in differential mode" hexmask.long.word 0x14 0.--10. 1. "CALFACT_S,Calibration Factors In Single-Ended mode" line.long 0x18 "ADC_CALFACT2,ADC calibration factor register 2" hexmask.long 0x18 0.--29. 1. "LINCALFACT,Linearity Calibration Factor" endif sif (cpuis("STM32H742*")) group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" newline bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" newline bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" newline bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" newline bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" newline bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" newline bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" newline bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" newline bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" newline bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" newline bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" newline bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" newline bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" newline bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" newline bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" newline bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" newline bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" newline bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" newline bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" newline bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" newline bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" newline bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" newline hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" newline bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" newline bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" endif sif (cpuis("STM32H742*")) group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "ADC2" base ad:0x40022100 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x0++0x27 line.long 0x0 "ADC_ISR,ADC interrupt and status register" rbitfld.long 0x0 12. "LDORDY,ADC LDO output voltage ready bit" "0: ADC LDO voltage regulator disabled,1: ADC LDO voltage regulator enabled" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" newline bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" newline bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" newline bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" newline bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" newline bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Writing ADCAL will launch a calibration in..,1: Writing ADCAL will launch a calibration in.." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in deep-power down,1: ADC in deep-power-down (default reset state)" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." newline bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word 6" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word 5" "0,1" newline bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word 4" "0,1" bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word 3" "0,1" newline bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word 2" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word 1" "0,1" newline bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0: Writing ADCAL will launch a calibration without..,1: Writing ADCAL will launch a calibration with he.." bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0: used when ADC clock <= 6.25 MHz,1: used when 6.25 MHz < ADC clock frequency <= 12.5..,2: used when 12.5 MHz < ADC clock frequency <= 25.0..,3: used when 25.0 MHz < ADC clock <= 50.0 MHz" newline bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." newline bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." newline bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0: Injected Queue enabled,1: Injected Queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR Mode 0: The Queue is never empty and..,1: JSQR Mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" bitfld.long 0xC 13. "CONT,Single / continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" newline bitfld.long 0xC 12. "OVRMOD,Overrun Mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,External trigger selection for regular group" bitfld.long 0xC 2.--4. "RES,Data resolution" "0: 16 bits,1: 14 bits in legacy mode (not optimized power..,2: 12 bits in legacy mode (not optimized power..,3: 10 bits,?,5: 14 bits,6: 12 bits,7: 8 bits" newline bitfld.long 0xC 0.--1. "DMNGT,Data Management configuration" "0: Regular conversion data stored in DR only,1: DMA One Shot Mode selected,2: DFSDM mode selected,3: DMA Circular Mode selected" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSVR,Oversampling ratio" newline bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4 correction" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3 correction" "0,1" newline bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2 correction" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1 correction" "0: Right-shifting disabled,1: Data is right-shifted 1-bit." newline bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling right shift" bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected Oversampling disabled,1: Injected Oversampling enabled" newline bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection (x = 0 to 9)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 27.--29. "SMP19,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" newline bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection (x = 10 to 19)" "0: 1.5 ADC clock cycles,1: 2.5 ADC clock cycles,2: 8.5 ADC clock cycles,3: 16.5 ADC clock cycles,4: 32.5 ADC clock cycles,5: 64.5 ADC clock cycles,6: 387.5 ADC clock cycles,7: 810.5 ADC clock cycles" line.long 0x1C "ADC_PCSEL,ADC channel preselection register" bitfld.long 0x1C 19. "PCSEL19,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 18. "PCSEL18,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 17. "PCSEL17,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 16. "PCSEL16,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 15. "PCSEL15,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 14. "PCSEL14,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 13. "PCSEL13,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 12. "PCSEL12,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 11. "PCSEL11,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 10. "PCSEL10,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 9. "PCSEL9,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 8. "PCSEL8,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 7. "PCSEL7,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 6. "PCSEL6,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 5. "PCSEL5,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 4. "PCSEL4,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 3. "PCSEL3,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 2. "PCSEL2,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." newline bitfld.long 0x1C 1. "PCSEL1,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." bitfld.long 0x1C 0. "PCSEL0,:Channel x (VINP[i]) pre selection (x = 0 to 19)" "0: Input Channel x (Vinp x) is not pre selected for..,1: Input Channel x (Vinp x) is pre selected for.." line.long 0x20 "ADC_LTR1,ADC watchdog threshold register 1" hexmask.long 0x20 0.--25. 1. "LTR1,Analog watchdog 1 lower threshold" line.long 0x24 "ADC_HTR1,ADC watchdog threshold register 1" hexmask.long 0x24 0.--25. 1. "HTR1,Analog watchdog 1 higher threshold" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular Data Register" hexmask.long 0x0 0.--31. 1. "RDATA,Regular Data converted" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: If JQDIS=0 (queue enabled) Hardware and software..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External trigger selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" group.long 0x60++0xF line.long 0x0 "ADC_OFR1,ADC injected channel 1 offset register" bitfld.long 0x0 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,Channel selection for the Data offset y" newline hexmask.long 0x0 0.--25. 1. "OFFSET1,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" line.long 0x4 "ADC_OFR2,ADC injected channel 2 offset register" bitfld.long 0x4 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0x4 26.--30. 1. "OFFSET2_CH,Channel selection for the Data offset y" newline hexmask.long 0x4 0.--25. 1. "OFFSET2,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" line.long 0x8 "ADC_OFR3,ADC injected channel 3 offset register" bitfld.long 0x8 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0x8 26.--30. 1. "OFFSET3_CH,Channel selection for the Data offset y" newline hexmask.long 0x8 0.--25. 1. "OFFSET3,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" line.long 0xC "ADC_OFR4,ADC injected channel 4 offset register" bitfld.long 0xC 31. "SSATE,Signed saturation Enable" "0: Offset is subtracted maintaining data integrity..,1: Offset is subtracted and result is saturated to.." hexmask.long.byte 0xC 26.--30. 1. "OFFSET4_CH,Channel selection for the Data offset y" newline hexmask.long 0xC 0.--25. 1. "OFFSET4,Data offset y for the channel programmed into bits OFFSETy_CH[4:0]" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long 0x0 0.--31. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long 0x4 0.--31. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long 0x8 0.--31. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long 0xC 0.--31. 1. "JDATA,Injected data" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC analog watchdog 3 configuration register" hexmask.long.tbyte 0x4 0.--19. 1. "AWD3CH,Analog watchdog 3 channel selection" group.long 0xB0++0x1B line.long 0x0 "ADC_LTR2,ADC watchdog lower threshold register 2" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower threshold" line.long 0x4 "ADC_HTR2,ADC watchdog higher threshold register 2" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher threshold" line.long 0x8 "ADC_LTR3,ADC watchdog lower threshold register 3" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower threshold" line.long 0xC "ADC_HTR3,ADC watchdog higher threshold register 3" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher threshold" line.long 0x10 "ADC_DIFSEL,ADC differential mode selection register" hexmask.long.tbyte 0x10 0.--19. 1. "DIFSEL,Differential mode for channels 19 to 0" line.long 0x14 "ADC_CALFACT,ADC calibration factors register" hexmask.long.word 0x14 16.--26. 1. "CALFACT_D,Calibration Factors in differential mode" hexmask.long.word 0x14 0.--10. 1. "CALFACT_S,Calibration Factors In Single-Ended mode" line.long 0x18 "ADC_CALFACT2,ADC calibration factor register 2" hexmask.long 0x18 0.--29. 1. "LINCALFACT,Linearity Calibration Factor" endif sif (cpuis("STM32H742*")) group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" newline bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" newline bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" newline bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" newline bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" newline bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" newline bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" newline bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" newline bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" newline bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" newline bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" newline bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" newline bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" newline bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" newline bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" newline bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" newline bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" newline bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" newline bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" newline bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" newline bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" newline bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" newline hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" newline bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" newline bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" endif sif (cpuis("STM32H742*")) group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" endif tree.end endif sif (cpuis("STM32H743*")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H750*")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x3 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "CDR2,ADC x common regular data register for" hexmask.long 0x0 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "ADC3" base ad:0x58026000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x0++0x1B line.long 0x0 "ADC_ISR,ADC interrupt and status register" bitfld.long 0x0 10. "JQOVF,Injected context queue overflow" "0: No injected context queue overflow occurred (or..,1: Injected context queue overflow has occurred" bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog 3 event occurred (or the flag..,1: Analog watchdog 3 event occurred" newline bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog 2 event occurred (or the flag..,1: Analog watchdog 2 event occurred" bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog 1 event occurred (or the flag..,1: Analog watchdog 1 event occurred" newline bitfld.long 0x0 6. "JEOS,Injected channel end of sequence flag" "0: Injected conversion sequence not complete (or..,1: Injected conversions complete" bitfld.long 0x0 5. "JEOC,Injected channel end of conversion flag" "0: Injected channel conversion not complete (or the..,1: Injected channel conversion complete" newline bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred" bitfld.long 0x0 3. "EOS,End of regular sequence flag" "0: Regular Conversions sequence not complete (or..,1: Regular Conversions sequence complete" newline bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Regular channel conversion not complete (or the..,1: Regular channel conversion complete" bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: not at the end of the sampling phase (or the..,1: End of sampling phase reached" newline bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion" line.long 0x4 "ADC_IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,Injected context queue overflow interrupt enable" "0: Injected Context Queue Overflow interrupt disabled,1: Injected Context Queue Overflow interrupt.." bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog 3 interrupt disabled,1: Analog watchdog 3 interrupt enabled" newline bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog 2 interrupt disabled,1: Analog watchdog 2 interrupt enabled" bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog 1 interrupt disabled,1: Analog watchdog 1 interrupt enabled" newline bitfld.long 0x4 6. "JEOSIE,End of injected sequence of conversions interrupt enable" "0: JEOS interrupt disabled,1: JEOS interrupt enabled. An interrupt is.." bitfld.long 0x4 5. "JEOCIE,End of injected conversion interrupt enable" "0: JEOC interrupt disabled.,1: JEOC interrupt enabled. An interrupt is.." newline bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.." bitfld.long 0x4 3. "EOSIE,End of regular sequence of conversions interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.." newline bitfld.long 0x4 2. "EOCIE,End of regular conversion interrupt enable" "0: EOC interrupt disabled.,1: EOC interrupt enabled. An interrupt is generated.." bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable for regular conversions" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.." newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled,1: ADRDY interrupt enabled. An interrupt is.." line.long 0x8 "ADC_CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.." bitfld.long 0x8 30. "ADCALDIF,Differential mode for calibration" "0: Writing ADCAL launches a calibration in..,1: Writing ADCAL launches a calibration in.." newline bitfld.long 0x8 29. "DEEPPWD,Deep-power-down enable" "0: ADC not in Deep-power down,1: ADC in Deep-power-down (default reset state)" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator enable" "0: ADC Voltage regulator disabled,1: ADC Voltage regulator enabled." newline bitfld.long 0x8 5. "JADSTP,ADC stop of injected conversion command" "0: No ADC stop injected conversion command ongoing,1: Write 1 to stop injected conversions ongoing." bitfld.long 0x8 4. "ADSTP,ADC stop of regular conversion command" "0: No ADC stop regular conversion command ongoing,1: Write 1 to stop regular conversions ongoing." newline bitfld.long 0x8 3. "JADSTART,ADC start of injected conversion" "0: No ADC injected conversion is ongoing.,1: Write 1 to start injected conversions. Read 1.." bitfld.long 0x8 2. "ADSTART,ADC start of regular conversion" "0: No ADC regular conversion is ongoing.,1: Write 1 to start regular conversions. Read 1.." newline bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: no ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.." bitfld.long 0x8 0. "ADEN,ADC enable control" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC." line.long 0xC "ADC_CFGR,ADC configuration register" bitfld.long 0xC 31. "JQDIS,Injected Queue disable" "0: Injected Queue enabled,1: Injected Queue disabled" hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog 1 channel selection" newline bitfld.long 0xC 25. "JAUTO,Automatic injected group conversion" "0: Automatic injected group conversion disabled,1: Automatic injected group conversion enabled" bitfld.long 0xC 24. "JAWD1EN,Analog watchdog 1 enable on injected channels" "0: Analog watchdog 1 disabled on injected channels,1: Analog watchdog 1 enabled on injected channels" newline bitfld.long 0xC 23. "AWD1EN,Analog watchdog 1 enable on regular channels" "0: Analog watchdog 1 disabled on regular channels,1: Analog watchdog 1 enabled on regular channels" bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog 1 on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel" newline bitfld.long 0xC 21. "JQM,JSQR queue mode" "0: JSQR mode 0: The Queue is never empty and..,1: JSQR mode 1: The Queue can be empty and when.." bitfld.long 0xC 20. "JDISCEN,Discontinuous mode on injected channels" "0: Discontinuous mode on injected channels disabled,1: Discontinuous mode on injected channels enabled" newline bitfld.long 0xC 17.--19. "DISCNUM,Discontinuous mode channel count" "0: 1 channel,1: 2 channels,?,?,?,?,?,7: 8 channels" bitfld.long 0xC 16. "DISCEN,Discontinuous mode for regular channels" "0: Discontinuous mode for regular channels disabled,1: Discontinuous mode for regular channels enabled" newline bitfld.long 0xC 15. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment" bitfld.long 0xC 14. "AUTDLY,Delayed conversion mode" "0: Auto-delayed conversion mode off,1: Auto-delayed conversion mode on" newline bitfld.long 0xC 13. "CONT,Single / Continuous conversion mode for regular conversions" "0: Single conversion mode,1: Continuous conversion mode" bitfld.long 0xC 12. "OVRMOD,Overrun mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.." newline bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection for regular channels" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." bitfld.long 0xC 9. "EXTSEL4,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1" newline bitfld.long 0xC 8. "EXTSEL3,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1" bitfld.long 0xC 7. "EXTSEL2,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1" newline bitfld.long 0xC 6. "EXTSEL1,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1" bitfld.long 0xC 5. "EXTSEL0,External trigger selection for regular group" "0: adc_ext_trg0,1: adc_ext_trg1" newline bitfld.long 0xC 3.--4. "RES,Data resolution" "0: 12-bit,1: 10-bit,2: 8-bit,3: 6-bit" bitfld.long 0xC 2. "DFSDMCFG,DFSDM mode configuration" "0: DFSDM mode disabled,1: DFSDM mode enabled" newline bitfld.long 0xC 1. "DMACFG,Direct memory access configuration" "0: DMA One Shot mode selected,1: DMA Circular mode selected" bitfld.long 0xC 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled" line.long 0x10 "ADC_CFGR2,ADC configuration register 2" bitfld.long 0x10 27. "SMPTRIG,Sampling time control trigger mode" "0: Sampling time control trigger mode disabled,1: Sampling time control trigger mode enabled" bitfld.long 0x10 26. "BULB,Bulb sampling mode" "0: Bulb sampling mode disabled,1: Bulb sampling mode enabled. The sampling period.." newline bitfld.long 0x10 25. "SWTRIG,Software trigger bit for sampling time control trigger mode" "0: Software trigger starts the conversion for..,1: Software trigger starts the sampling for.." bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0: Continued mode: When injected conversions are..,1: Resumed mode: When injected conversions are.." newline bitfld.long 0x10 9. "TROVS,Triggered Regular Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.." hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift" newline bitfld.long 0x10 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x" bitfld.long 0x10 1. "JOVSE,Injected Oversampling Enable" "0: Injected Oversampling disabled,1: Injected Oversampling enabled" newline bitfld.long 0x10 0. "ROVSE,Regular Oversampling Enable" "0: Regular Oversampling disabled,1: Regular Oversampling enabled" line.long 0x14 "ADC_SMPR1,ADC sample time register 1" bitfld.long 0x14 31. "SMPPLUS,Addition of one clock cycle to the sampling time." "0: The sampling time remains set to 2.5 ADC clock..,1: 2.5 ADC clock cycle sampling time becomes 3.5.." bitfld.long 0x14 27.--29. "SMP9,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 24.--26. "SMP8,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 21.--23. "SMP7,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 18.--20. "SMP6,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 15.--17. "SMP5,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 12.--14. "SMP4,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 9.--11. "SMP3,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 6.--8. "SMP2,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x14 3.--5. "SMP1,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x14 0.--2. "SMP0,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" line.long 0x18 "ADC_SMPR2,ADC sample time register 2" bitfld.long 0x18 24.--26. "SMP18,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 21.--23. "SMP17,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 18.--20. "SMP16,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 15.--17. "SMP15,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 12.--14. "SMP14,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 9.--11. "SMP13,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 6.--8. "SMP12,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" bitfld.long 0x18 3.--5. "SMP11,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" newline bitfld.long 0x18 0.--2. "SMP10,Channel x sampling time selection" "0: 2.5 ADC clock cycles,1: 6.5 ADC clock cycles,2: 12.5 ADC clock cycles,3: 24.5 ADC clock cycles,4: 47.5 ADC clock cycles,5: 92.5 ADC clock cycles,6: 247.5 ADC clock cycles,7: 640.5 ADC clock cycles" group.long 0x20++0xB line.long 0x0 "ADC_TR1,ADC watchdog threshold register 1" hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold" bitfld.long 0x0 12.--14. "AWDFILT,Analog watchdog filtering parameter" "0: No filtering,1: two consecutive detection generates an AWDx flag..,?,?,?,?,?,7: Eight consecutive detection generates an AWDx.." newline hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold" line.long 0x4 "ADC_TR2,ADC watchdog threshold register 2" hexmask.long.byte 0x4 16.--23. 1. "HT2,Analog watchdog 2 higher threshold" hexmask.long.byte 0x4 0.--7. 1. "LT2,Analog watchdog 2 lower threshold" line.long 0x8 "ADC_TR3,ADC watchdog threshold register 3" hexmask.long.byte 0x8 16.--23. 1. "HT3,Analog watchdog 3 higher threshold" hexmask.long.byte 0x8 0.--7. 1. "LT3,Analog watchdog 3 lower threshold" group.long 0x30++0xF line.long 0x0 "ADC_SQR1,ADC regular sequence register 1" hexmask.long.byte 0x0 24.--28. 1. "SQ4,4th conversion in regular sequence" hexmask.long.byte 0x0 18.--22. 1. "SQ3,3rd conversion in regular sequence" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,2nd conversion in regular sequence" hexmask.long.byte 0x0 6.--10. 1. "SQ1,1st conversion in regular sequence" newline hexmask.long.byte 0x0 0.--3. 1. "L,Regular channel sequence length" line.long 0x4 "ADC_SQR2,ADC regular sequence register 2" hexmask.long.byte 0x4 24.--28. 1. "SQ9,9th conversion in regular sequence" hexmask.long.byte 0x4 18.--22. 1. "SQ8,8th conversion in regular sequence" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,7th conversion in regular sequence" hexmask.long.byte 0x4 6.--10. 1. "SQ6,6th conversion in regular sequence" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,5th conversion in regular sequence" line.long 0x8 "ADC_SQR3,ADC regular sequence register 3" hexmask.long.byte 0x8 24.--28. 1. "SQ14,14th conversion in regular sequence" hexmask.long.byte 0x8 18.--22. 1. "SQ13,13th conversion in regular sequence" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,12th conversion in regular sequence" hexmask.long.byte 0x8 6.--10. 1. "SQ11,11th conversion in regular sequence" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,10th conversion in regular sequence" line.long 0xC "ADC_SQR4,ADC regular sequence register 4" hexmask.long.byte 0xC 6.--10. 1. "SQ16,16th conversion in regular sequence" hexmask.long.byte 0xC 0.--4. 1. "SQ15,15th conversion in regular sequence" rgroup.long 0x40++0x3 line.long 0x0 "ADC_DR,ADC regular data register" hexmask.long.word 0x0 0.--15. 1. "RDATA,Regular data converted" group.long 0x4C++0x3 line.long 0x0 "ADC_JSQR,ADC injected sequence register" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,4th conversion in the injected sequence" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,3rd conversion in the injected sequence" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,2nd conversion in the injected sequence" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,1st conversion in the injected sequence" newline bitfld.long 0x0 7.--8. "JEXTEN,External trigger enable and polarity selection for injected channels" "0: If JQDIS = 0 (queue enabled) hardware and..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.." hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,External Trigger Selection for injected group" newline bitfld.long 0x0 0.--1. "JL,Injected channel sequence length" "0: 1 conversion,1: 2 conversions,2: 3 conversions,3: 4 conversions" group.long 0x60++0xF line.long 0x0 "ADC_OFR1,ADC offset 1 register" bitfld.long 0x0 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x0 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x0 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x0 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0x4 "ADC_OFR2,ADC offset 2 register" bitfld.long 0x4 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x4 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x4 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x4 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0x8 "ADC_OFR3,ADC offset 3 register" bitfld.long 0x8 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0x8 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0x8 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0x8 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" line.long 0xC "ADC_OFR4,ADC offset 4 register" bitfld.long 0xC 31. "OFFSET_EN,Offset y enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET_CH,Channel selection for the data offset y" newline bitfld.long 0xC 25. "SATEN,Saturation enable" "0: No saturation control offset result can be signed,1: Saturation enabled offset result unsigned and.." bitfld.long 0xC 24. "OFFSETPOS,Positive offset" "0: Negative offset,1: Positive offset" newline hexmask.long.word 0xC 0.--11. 1. "OFFSET,Data offset y for the channel programmed into bits OFFSET_CH[4:0]" rgroup.long 0x80++0xF line.long 0x0 "ADC_JDR1,ADC injected channel 1 data register" hexmask.long.word 0x0 0.--15. 1. "JDATA,Injected data" line.long 0x4 "ADC_JDR2,ADC injected channel 2 data register" hexmask.long.word 0x4 0.--15. 1. "JDATA,Injected data" line.long 0x8 "ADC_JDR3,ADC injected channel 3 data register" hexmask.long.word 0x8 0.--15. 1. "JDATA,Injected data" line.long 0xC "ADC_JDR4,ADC injected channel 4 data register" hexmask.long.word 0xC 0.--15. 1. "JDATA,Injected data" group.long 0xA0++0x7 line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration Register" hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,Analog watchdog 2 channel selection" line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration Register" hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,Analog watchdog 3 channel selection" group.long 0xB0++0x7 line.long 0x0 "ADC_DIFSEL,ADC Differential mode Selection Register" hexmask.long.tbyte 0x0 0.--18. 1. "DIFSEL,Differential mode for channels 18 to 0." line.long 0x4 "ADC_CALFACT,ADC Calibration Factors" hexmask.long.byte 0x4 16.--22. 1. "CALFACT_D,Calibration Factors in differential mode" hexmask.long.byte 0x4 0.--6. 1. "CALFACT_S,Calibration Factors In Single-ended mode" endif sif (cpuis("STM32H742*")) group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" newline bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" newline bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" newline bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" newline bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" newline bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" newline bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" newline bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" newline bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" newline bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" newline bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" newline bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" newline bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" newline bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" newline bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" newline bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" newline bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" newline bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" newline bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" newline bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" newline bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" newline bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" newline bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" newline bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" newline hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" newline bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" newline hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" newline hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" newline hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" newline hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" newline hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" newline hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" newline hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" newline bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" newline bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" newline hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" endif sif (cpuis("STM32H742*")) group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "ADC3_Common" base ad:0x58026300 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) rgroup.long 0x0++0x3 line.long 0x0 "ADC_CSR,ADC common status register" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of the master ADC" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master ADC" "0,1" newline bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master ADC" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master ADC" "0,1" newline bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the master ADC" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the master ADC" "0,1" newline bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master ADC" "0,1" bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the master ADC" "0,1" newline bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master ADC" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master ADC" "0,1" newline bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "ADC_CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled" bitfld.long 0x0 23. "TSEN,VSENSE enable" "0: Temperature sensor channel disabled,1: Temperature sensor channel enabled" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT channel disabled,1: VREFINT channel enabled" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0: adc_ker_ck (x = 3) (Asynchronous clock mode)..,1: adc_hclk/1 (Synchronous clock mode). This..,2: adc_hclk/2 (Synchronous clock mode),3: adc_hclk/4 (Synchronous clock mode)" rgroup.long 0xC++0x7 line.long 0x0 "ADC_CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "ADC_CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" endif sif (cpuis("STM32H742*")) rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" newline bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" newline bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" newline bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" newline bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" newline bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" newline bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" newline bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" newline bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" newline bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" newline bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" newline bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" endif tree.end endif sif (cpuis("STM32H743*")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H750*")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x3 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" tree.end endif sif (cpuis("STM32H753*")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H753*")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H753*")) tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "ADC3" base ad:0x58026000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8.--9. "BOOST,Boost mode control" "0,1,2,3" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--4. "RES,ADC data resolution" "0,1,2,3,4,5,6,7" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC3_Common" base ad:0x58026300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x7 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" line.long 0x4 "CDR2,ADC x common regular data register for" hexmask.long 0x4 0.--31. 1. "RDATA_ALT,Regular data of the master/slave" tree.end endif sif (cpuis("STM32H7A3*")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" bitfld.long 0xC 17.--19. "DISCNUM,ADC group regular sequencer" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" bitfld.long 0x14 27.--29. "SMP9,ADC channel 9 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 24.--26. "SMP8,ADC channel 8 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 21.--23. "SMP7,ADC channel 7 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 18.--20. "SMP6,ADC channel 6 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 15.--17. "SMP5,ADC channel 5 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 12.--14. "SMP4,ADC channel 4 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 9.--11. "SMP3,ADC channel 3 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6.--8. "SMP2,ADC channel 2 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x14 3.--5. "SMP1,ADC channel 1 sampling time" "0,1,2,3,4,5,6,7" line.long 0x18 "SMPR2,ADC sampling time register 2" bitfld.long 0x18 27.--29. "SMP19,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 24.--26. "SMP18,ADC channel 18 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 21.--23. "SMP17,ADC channel 17 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 18.--20. "SMP16,ADC channel 16 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 15.--17. "SMP15,ADC channel 15 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 12.--14. "SMP14,ADC channel 14 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 9.--11. "SMP13,ADC channel 13 sampling time" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 6.--8. "SMP12,ADC channel 12 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 3.--5. "SMP11,ADC channel 11 sampling time" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--2. "SMP10,ADC channel 10 sampling time" "0,1,2,3,4,5,6,7" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x3 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" tree.end endif sif (cpuis("STM32H7B0*")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" hexmask.long.byte 0xC 17.--20. 1. "DISCNUM,ADC group regular sequencer" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" hexmask.long.byte 0x14 27.--30. 1. "SMP9,ADC channel 9 sampling time" hexmask.long.byte 0x14 24.--27. 1. "SMP8,ADC channel 8 sampling time" hexmask.long.byte 0x14 21.--24. 1. "SMP7,ADC channel 7 sampling time" hexmask.long.byte 0x14 18.--21. 1. "SMP6,ADC channel 6 sampling time" hexmask.long.byte 0x14 15.--18. 1. "SMP5,ADC channel 5 sampling time" hexmask.long.byte 0x14 12.--15. 1. "SMP4,ADC channel 4 sampling time" hexmask.long.byte 0x14 9.--12. 1. "SMP3,ADC channel 3 sampling time" newline hexmask.long.byte 0x14 6.--9. 1. "SMP2,ADC channel 2 sampling time" hexmask.long.byte 0x14 3.--6. 1. "SMP1,ADC channel 1 sampling time" line.long 0x18 "SMPR2,ADC sampling time register 2" hexmask.long.byte 0x18 27.--30. 1. "SMP19,ADC channel 18 sampling time" hexmask.long.byte 0x18 24.--27. 1. "SMP18,ADC channel 18 sampling time" hexmask.long.byte 0x18 21.--24. 1. "SMP17,ADC channel 17 sampling time" hexmask.long.byte 0x18 18.--21. 1. "SMP16,ADC channel 16 sampling time" hexmask.long.byte 0x18 15.--18. 1. "SMP15,ADC channel 15 sampling time" hexmask.long.byte 0x18 12.--15. 1. "SMP14,ADC channel 14 sampling time" hexmask.long.byte 0x18 9.--12. 1. "SMP13,ADC channel 13 sampling time" newline hexmask.long.byte 0x18 6.--9. 1. "SMP12,ADC channel 12 sampling time" hexmask.long.byte 0x18 3.--6. 1. "SMP11,ADC channel 11 sampling time" hexmask.long.byte 0x18 0.--3. 1. "SMP10,ADC channel 10 sampling time" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" hexmask.long.byte 0xC 17.--20. 1. "DISCNUM,ADC group regular sequencer" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" hexmask.long.byte 0x14 27.--30. 1. "SMP9,ADC channel 9 sampling time" hexmask.long.byte 0x14 24.--27. 1. "SMP8,ADC channel 8 sampling time" hexmask.long.byte 0x14 21.--24. 1. "SMP7,ADC channel 7 sampling time" hexmask.long.byte 0x14 18.--21. 1. "SMP6,ADC channel 6 sampling time" hexmask.long.byte 0x14 15.--18. 1. "SMP5,ADC channel 5 sampling time" hexmask.long.byte 0x14 12.--15. 1. "SMP4,ADC channel 4 sampling time" hexmask.long.byte 0x14 9.--12. 1. "SMP3,ADC channel 3 sampling time" newline hexmask.long.byte 0x14 6.--9. 1. "SMP2,ADC channel 2 sampling time" hexmask.long.byte 0x14 3.--6. 1. "SMP1,ADC channel 1 sampling time" line.long 0x18 "SMPR2,ADC sampling time register 2" hexmask.long.byte 0x18 27.--30. 1. "SMP19,ADC channel 18 sampling time" hexmask.long.byte 0x18 24.--27. 1. "SMP18,ADC channel 18 sampling time" hexmask.long.byte 0x18 21.--24. 1. "SMP17,ADC channel 17 sampling time" hexmask.long.byte 0x18 18.--21. 1. "SMP16,ADC channel 16 sampling time" hexmask.long.byte 0x18 15.--18. 1. "SMP15,ADC channel 15 sampling time" hexmask.long.byte 0x18 12.--15. 1. "SMP14,ADC channel 14 sampling time" hexmask.long.byte 0x18 9.--12. 1. "SMP13,ADC channel 13 sampling time" newline hexmask.long.byte 0x18 6.--9. 1. "SMP12,ADC channel 12 sampling time" hexmask.long.byte 0x18 3.--6. 1. "SMP11,ADC channel 11 sampling time" hexmask.long.byte 0x18 0.--3. 1. "SMP10,ADC channel 10 sampling time" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x3 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" tree.end endif sif (cpuis("STM32H7B3*")) tree "ADC1" base ad:0x40022000 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" hexmask.long.byte 0xC 17.--20. 1. "DISCNUM,ADC group regular sequencer" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" hexmask.long.byte 0x14 27.--30. 1. "SMP9,ADC channel 9 sampling time" hexmask.long.byte 0x14 24.--27. 1. "SMP8,ADC channel 8 sampling time" hexmask.long.byte 0x14 21.--24. 1. "SMP7,ADC channel 7 sampling time" hexmask.long.byte 0x14 18.--21. 1. "SMP6,ADC channel 6 sampling time" hexmask.long.byte 0x14 15.--18. 1. "SMP5,ADC channel 5 sampling time" hexmask.long.byte 0x14 12.--15. 1. "SMP4,ADC channel 4 sampling time" hexmask.long.byte 0x14 9.--12. 1. "SMP3,ADC channel 3 sampling time" newline hexmask.long.byte 0x14 6.--9. 1. "SMP2,ADC channel 2 sampling time" hexmask.long.byte 0x14 3.--6. 1. "SMP1,ADC channel 1 sampling time" line.long 0x18 "SMPR2,ADC sampling time register 2" hexmask.long.byte 0x18 27.--30. 1. "SMP19,ADC channel 18 sampling time" hexmask.long.byte 0x18 24.--27. 1. "SMP18,ADC channel 18 sampling time" hexmask.long.byte 0x18 21.--24. 1. "SMP17,ADC channel 17 sampling time" hexmask.long.byte 0x18 18.--21. 1. "SMP16,ADC channel 16 sampling time" hexmask.long.byte 0x18 15.--18. 1. "SMP15,ADC channel 15 sampling time" hexmask.long.byte 0x18 12.--15. 1. "SMP14,ADC channel 14 sampling time" hexmask.long.byte 0x18 9.--12. 1. "SMP13,ADC channel 13 sampling time" newline hexmask.long.byte 0x18 6.--9. 1. "SMP12,ADC channel 12 sampling time" hexmask.long.byte 0x18 3.--6. 1. "SMP11,ADC channel 11 sampling time" hexmask.long.byte 0x18 0.--3. 1. "SMP10,ADC channel 10 sampling time" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC2" base ad:0x40022100 group.long 0x0++0x1B line.long 0x0 "ISR,ADC interrupt and status" bitfld.long 0x0 10. "JQOVF,ADC group injected contexts queue" "0,1" bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1" bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1" bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1" bitfld.long 0x0 6. "JEOS,ADC group injected end of sequence" "0,1" bitfld.long 0x0 5. "JEOC,ADC group injected end of unitary" "0,1" bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1" newline bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1" bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1" bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1" bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1" line.long 0x4 "IER,ADC interrupt enable register" bitfld.long 0x4 10. "JQOVFIE,ADC group injected contexts queue" "0,1" bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1" bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1" bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1" bitfld.long 0x4 6. "JEOSIE,ADC group injected end of sequence" "0,1" bitfld.long 0x4 5. "JEOCIE,ADC group injected end of unitary" "0,1" bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1" newline bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1" bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1" bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1" bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1" line.long 0x8 "CR,ADC control register" bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1" bitfld.long 0x8 30. "ADCALDIF,ADC differential mode for" "0,1" bitfld.long 0x8 29. "DEEPPWD,ADC deep power down enable" "0,1" bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1" bitfld.long 0x8 27. "LINCALRDYW6,Linearity calibration ready Word" "0,1" bitfld.long 0x8 26. "LINCALRDYW5,Linearity calibration ready Word" "0,1" bitfld.long 0x8 25. "LINCALRDYW4,Linearity calibration ready Word" "0,1" newline bitfld.long 0x8 24. "LINCALRDYW3,Linearity calibration ready Word" "0,1" bitfld.long 0x8 23. "LINCALRDYW2,Linearity calibration ready Word" "0,1" bitfld.long 0x8 22. "LINCALRDYW1,Linearity calibration ready Word" "0,1" bitfld.long 0x8 16. "ADCALLIN,Linearity calibration" "0,1" bitfld.long 0x8 8. "BOOST,Boost mode control" "0,1" bitfld.long 0x8 5. "JADSTP,ADC group injected conversion" "0,1" bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1" newline bitfld.long 0x8 3. "JADSTART,ADC group injected conversion" "0,1" bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1" bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1" bitfld.long 0x8 0. "ADEN,ADC enable" "0,1" line.long 0xC "CFGR,ADC configuration register 1" bitfld.long 0xC 31. "JQDIS,ADC group injected contexts queue" "0,1" hexmask.long.byte 0xC 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel" bitfld.long 0xC 25. "JAUTO,ADC group injected automatic trigger" "0,1" bitfld.long 0xC 24. "JAWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1" bitfld.long 0xC 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1" bitfld.long 0xC 21. "JQM,ADC group injected contexts queue" "0,1" newline bitfld.long 0xC 20. "JDISCEN,ADC group injected sequencer" "0,1" hexmask.long.byte 0xC 17.--20. 1. "DISCNUM,ADC group regular sequencer" bitfld.long 0xC 16. "DISCEN,ADC group regular sequencer" "0,1" bitfld.long 0xC 14. "AUTDLY,ADC low power auto wait" "0,1" bitfld.long 0xC 13. "CONT,ADC group regular continuous conversion" "0,1" bitfld.long 0xC 12. "OVRMOD,ADC group regular overrun" "0,1" bitfld.long 0xC 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3" newline hexmask.long.byte 0xC 5.--9. 1. "EXTSEL,ADC group regular external trigger" bitfld.long 0xC 2.--3. "RES,ADC data resolution" "0,1,2,3" bitfld.long 0xC 0.--1. "DMNGT,ADC DMA transfer enable" "0,1,2,3" line.long 0x10 "CFGR2,ADC configuration register 2" hexmask.long.byte 0x10 28.--31. 1. "LSHIFT,Left shift factor" hexmask.long.word 0x10 16.--25. 1. "OSR,Oversampling ratio" bitfld.long 0x10 14. "RSHIFT4,Right-shift data after Offset 4" "0,1" bitfld.long 0x10 13. "RSHIFT3,Right-shift data after Offset 3" "0,1" bitfld.long 0x10 12. "RSHIFT2,Right-shift data after Offset 2" "0,1" bitfld.long 0x10 11. "RSHIFT1,Right-shift data after Offset 1" "0,1" bitfld.long 0x10 10. "ROVSM,Regular Oversampling mode" "0,1" newline bitfld.long 0x10 9. "TROVS,ADC oversampling discontinuous mode" "0,1" hexmask.long.byte 0x10 5.--8. 1. "OVSS,ADC oversampling shift" bitfld.long 0x10 1. "JOVSE,ADC oversampler enable on scope ADC" "0,1" bitfld.long 0x10 0. "ROVSE,ADC oversampler enable on scope ADC" "0,1" line.long 0x14 "SMPR1,ADC sampling time register 1" hexmask.long.byte 0x14 27.--30. 1. "SMP9,ADC channel 9 sampling time" hexmask.long.byte 0x14 24.--27. 1. "SMP8,ADC channel 8 sampling time" hexmask.long.byte 0x14 21.--24. 1. "SMP7,ADC channel 7 sampling time" hexmask.long.byte 0x14 18.--21. 1. "SMP6,ADC channel 6 sampling time" hexmask.long.byte 0x14 15.--18. 1. "SMP5,ADC channel 5 sampling time" hexmask.long.byte 0x14 12.--15. 1. "SMP4,ADC channel 4 sampling time" hexmask.long.byte 0x14 9.--12. 1. "SMP3,ADC channel 3 sampling time" newline hexmask.long.byte 0x14 6.--9. 1. "SMP2,ADC channel 2 sampling time" hexmask.long.byte 0x14 3.--6. 1. "SMP1,ADC channel 1 sampling time" line.long 0x18 "SMPR2,ADC sampling time register 2" hexmask.long.byte 0x18 27.--30. 1. "SMP19,ADC channel 18 sampling time" hexmask.long.byte 0x18 24.--27. 1. "SMP18,ADC channel 18 sampling time" hexmask.long.byte 0x18 21.--24. 1. "SMP17,ADC channel 17 sampling time" hexmask.long.byte 0x18 18.--21. 1. "SMP16,ADC channel 16 sampling time" hexmask.long.byte 0x18 15.--18. 1. "SMP15,ADC channel 15 sampling time" hexmask.long.byte 0x18 12.--15. 1. "SMP14,ADC channel 14 sampling time" hexmask.long.byte 0x18 9.--12. 1. "SMP13,ADC channel 13 sampling time" newline hexmask.long.byte 0x18 6.--9. 1. "SMP12,ADC channel 12 sampling time" hexmask.long.byte 0x18 3.--6. 1. "SMP11,ADC channel 11 sampling time" hexmask.long.byte 0x18 0.--3. 1. "SMP10,ADC channel 10 sampling time" group.long 0x20++0x7 line.long 0x0 "LTR1,ADC analog watchdog 1 threshold" hexmask.long 0x0 0.--25. 1. "LTR1,ADC analog watchdog 1 threshold" line.long 0x4 "LHTR1,ADC analog watchdog 2 threshold" hexmask.long 0x4 0.--25. 1. "LHTR1,ADC analog watchdog 2 threshold" group.long 0x30++0xF line.long 0x0 "SQR1,ADC group regular sequencer ranks register" hexmask.long.byte 0x0 24.--28. 1. "SQ4,ADC group regular sequencer rank" hexmask.long.byte 0x0 18.--22. 1. "SQ3,ADC group regular sequencer rank" hexmask.long.byte 0x0 12.--16. 1. "SQ2,ADC group regular sequencer rank" hexmask.long.byte 0x0 6.--10. 1. "SQ1,ADC group regular sequencer rank" hexmask.long.byte 0x0 0.--3. 1. "L3,L3" line.long 0x4 "SQR2,ADC group regular sequencer ranks register" hexmask.long.byte 0x4 24.--28. 1. "SQ9,ADC group regular sequencer rank" hexmask.long.byte 0x4 18.--22. 1. "SQ8,ADC group regular sequencer rank" hexmask.long.byte 0x4 12.--16. 1. "SQ7,ADC group regular sequencer rank" hexmask.long.byte 0x4 6.--10. 1. "SQ6,ADC group regular sequencer rank" hexmask.long.byte 0x4 0.--4. 1. "SQ5,ADC group regular sequencer rank" line.long 0x8 "SQR3,ADC group regular sequencer ranks register" hexmask.long.byte 0x8 24.--28. 1. "SQ14,ADC group regular sequencer rank" hexmask.long.byte 0x8 18.--22. 1. "SQ13,ADC group regular sequencer rank" hexmask.long.byte 0x8 12.--16. 1. "SQ12,ADC group regular sequencer rank" hexmask.long.byte 0x8 6.--10. 1. "SQ11,ADC group regular sequencer rank" hexmask.long.byte 0x8 0.--4. 1. "SQ10,ADC group regular sequencer rank" line.long 0xC "SQR4,ADC group regular sequencer ranks register" hexmask.long.byte 0xC 6.--10. 1. "SQ16,ADC group regular sequencer rank" hexmask.long.byte 0xC 0.--4. 1. "SQ15,ADC group regular sequencer rank" rgroup.long 0x40++0x3 line.long 0x0 "DR,ADC group regular conversion data" hexmask.long.word 0x0 0.--15. 1. "RDATA,ADC group regular conversion" group.long 0x4C++0x3 line.long 0x0 "JSQR,ADC group injected sequencer" hexmask.long.byte 0x0 27.--31. 1. "JSQ4,ADC group injected sequencer rank" hexmask.long.byte 0x0 21.--25. 1. "JSQ3,ADC group injected sequencer rank" hexmask.long.byte 0x0 15.--19. 1. "JSQ2,ADC group injected sequencer rank" hexmask.long.byte 0x0 9.--13. 1. "JSQ1,ADC group injected sequencer rank" bitfld.long 0x0 7.--8. "JEXTEN,ADC group injected external trigger" "0,1,2,3" hexmask.long.byte 0x0 2.--6. 1. "JEXTSEL,ADC group injected external trigger" bitfld.long 0x0 0.--1. "JL,ADC group injected sequencer scan" "0,1,2,3" group.long 0x60++0xF line.long 0x0 "OFR1,ADC offset number 1 register" bitfld.long 0x0 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x0 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x0 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x4 "OFR2,ADC offset number 2 register" bitfld.long 0x4 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x4 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x4 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0x8 "OFR3,ADC offset number 3 register" bitfld.long 0x8 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0x8 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0x8 0.--25. 1. "OFFSET1,ADC offset number 1 offset" line.long 0xC "OFR4,ADC offset number 4 register" bitfld.long 0xC 31. "SSATE,ADC offset number 1 enable" "0,1" hexmask.long.byte 0xC 26.--30. 1. "OFFSET1_CH,ADC offset number 1 channel" hexmask.long 0xC 0.--25. 1. "OFFSET1,ADC offset number 1 offset" rgroup.long 0x80++0xF line.long 0x0 "JDR1,ADC group injected sequencer rank 1" hexmask.long 0x0 0.--31. 1. "JDATA1,ADC group injected sequencer rank 1" line.long 0x4 "JDR2,ADC group injected sequencer rank 2" hexmask.long 0x4 0.--31. 1. "JDATA2,ADC group injected sequencer rank 2" line.long 0x8 "JDR3,ADC group injected sequencer rank 3" hexmask.long 0x8 0.--31. 1. "JDATA3,ADC group injected sequencer rank 3" line.long 0xC "JDR4,ADC group injected sequencer rank 4" hexmask.long 0xC 0.--31. 1. "JDATA4,ADC group injected sequencer rank 4" group.long 0xA0++0x7 line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration" hexmask.long.tbyte 0x0 0.--19. 1. "AWD2CH,ADC analog watchdog 2 monitored channel" line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration" hexmask.long.tbyte 0x4 1.--20. 1. "AWD3CH,ADC analog watchdog 3 monitored channel" group.long 0xC0++0x7 line.long 0x0 "DIFSEL,ADC channel differential or single-ended" hexmask.long.tbyte 0x0 0.--19. 1. "DIFSEL,ADC channel differential or single-ended" line.long 0x4 "CALFACT,ADC calibration factors" hexmask.long.word 0x4 16.--26. 1. "CALFACT_D,ADC calibration factor in differential" hexmask.long.word 0x4 0.--10. 1. "CALFACT_S,ADC calibration factor in single-ended" group.long 0x1C++0x3 line.long 0x0 "PCSEL,ADC pre channel selection" hexmask.long.tbyte 0x0 0.--19. 1. "PCSEL,Channel x (VINP[i]) pre" group.long 0xB0++0xF line.long 0x0 "LTR2,ADC watchdog lower threshold register" hexmask.long 0x0 0.--25. 1. "LTR2,Analog watchdog 2 lower" line.long 0x4 "HTR2,ADC watchdog higher threshold register" hexmask.long 0x4 0.--25. 1. "HTR2,Analog watchdog 2 higher" line.long 0x8 "LTR3,ADC watchdog lower threshold register" hexmask.long 0x8 0.--25. 1. "LTR3,Analog watchdog 3 lower" line.long 0xC "HTR3,ADC watchdog higher threshold register" hexmask.long 0xC 0.--25. 1. "HTR3,Analog watchdog 3 higher" group.long 0xC8++0x3 line.long 0x0 "CALFACT2,ADC Calibration Factor register" hexmask.long 0x0 0.--29. 1. "LINCALFACT,Linearity Calibration" tree.end tree "ADC12_Common" base ad:0x40022300 rgroup.long 0x0++0x3 line.long 0x0 "CSR,ADC Common status register" bitfld.long 0x0 26. "JQOVF_SLV,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 25. "AWD3_SLV,Analog watchdog 3 flag of the slave" "0,1" bitfld.long 0x0 24. "AWD2_SLV,Analog watchdog 2 flag of the slave" "0,1" bitfld.long 0x0 23. "AWD1_SLV,Analog watchdog 1 flag of the slave" "0,1" bitfld.long 0x0 22. "JEOS_SLV,End of injected sequence flag of the" "0,1" bitfld.long 0x0 21. "JEOC_SLV,End of injected conversion flag of the" "0,1" bitfld.long 0x0 20. "OVR_SLV,Overrun flag of the slave" "0,1" bitfld.long 0x0 19. "EOS_SLV,End of regular sequence flag of the" "0,1" bitfld.long 0x0 18. "EOC_SLV,End of regular conversion of the slave" "0,1" newline bitfld.long 0x0 17. "EOSMP_SLV,End of Sampling phase flag of the slave" "0,1" bitfld.long 0x0 16. "ADRDY_SLV,Slave ADC ready" "0,1" bitfld.long 0x0 10. "JQOVF_MST,Injected Context Queue Overflow flag of" "0,1" bitfld.long 0x0 9. "AWD3_MST,Analog watchdog 3 flag of the master" "0,1" bitfld.long 0x0 8. "AWD2_MST,Analog watchdog 2 flag of the master" "0,1" bitfld.long 0x0 7. "AWD1_MST,Analog watchdog 1 flag of the master" "0,1" bitfld.long 0x0 6. "JEOS_MST,End of injected sequence flag of the" "0,1" bitfld.long 0x0 5. "JEOC_MST,End of injected conversion flag of the" "0,1" bitfld.long 0x0 4. "OVR_MST,Overrun flag of the master" "0,1" newline bitfld.long 0x0 3. "EOS_MST,End of regular sequence flag of the" "0,1" bitfld.long 0x0 2. "EOC_MST,End of regular conversion of the master" "0,1" bitfld.long 0x0 1. "EOSMP_MST,End of Sampling phase flag of the master" "0,1" bitfld.long 0x0 0. "ADRDY_MST,Master ADC ready" "0,1" group.long 0x8++0x3 line.long 0x0 "CCR,ADC common control register" bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1" bitfld.long 0x0 23. "VSENSEEN,Temperature sensor enable" "0,1" bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1" hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler" bitfld.long 0x0 16.--17. "CKMODE,ADC clock mode" "0,1,2,3" bitfld.long 0x0 14.--15. "DAMDF,Dual ADC Mode Data Format" "0,1,2,3" hexmask.long.byte 0x0 8.--11. 1. "DELAY,Delay between 2 sampling" hexmask.long.byte 0x0 0.--4. 1. "DUAL,Dual ADC mode selection" rgroup.long 0xC++0x3 line.long 0x0 "CDR,ADC common regular data register for dual" hexmask.long.word 0x0 16.--31. 1. "RDATA_SLV,Regular data of the slave" hexmask.long.word 0x0 0.--15. 1. "RDATA_MST,Regular data of the master" tree.end endif tree.end sif (cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "ART (ART Accelerator)" base ad:0x40024400 group.long 0x0++0x3 line.long 0x0 "CTR,control register" hexmask.long.word 0x0 8.--19. 1. "PCACHEADDR,Cacheable page index" bitfld.long 0x0 0. "EN,Cache enable" "0,1" tree.end endif tree "AXI (AXI Interconnect Registers)" base ad:0x51000000 rgroup.long 0x1FD0++0x3 line.long 0x0 "AXI_PERIPH_ID_4,AXI interconnect - peripheral ID4" hexmask.long.byte 0x0 4.--7. 1. "KCOUNT4,Register file size" hexmask.long.byte 0x0 0.--3. 1. "JEP106CON,JEP106 continuation code" rgroup.long 0x1FE0++0x1F line.long 0x0 "AXI_PERIPH_ID_0,AXI interconnect - peripheral ID0" hexmask.long.byte 0x0 0.--7. 1. "PARTNUM,Peripheral part number bits 0 to" line.long 0x4 "AXI_PERIPH_ID_1,AXI interconnect - peripheral ID1" hexmask.long.byte 0x4 4.--7. 1. "JEP106I,JEP106 identity bits 0 to" hexmask.long.byte 0x4 0.--3. 1. "PARTNUM,Peripheral part number bits 8 to" line.long 0x8 "AXI_PERIPH_ID_2,AXI interconnect - peripheral ID2" hexmask.long.byte 0x8 4.--7. 1. "REVISION,Peripheral revision number" bitfld.long 0x8 3. "JEDEC,JEP106 code flag" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 0.--2. "JEP106ID,JEP106 Identity bits 4 to" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x8 0.--3. 1. "JEP106ID,JEP106 Identity bits 4 to" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 0.--3. 1. "JEP106ID,JEP106 Identity bits 4 to" endif line.long 0xC "AXI_PERIPH_ID_3,AXI interconnect - peripheral ID3" hexmask.long.byte 0xC 4.--7. 1. "REV_AND,Customer version" hexmask.long.byte 0xC 0.--3. 1. "CUST_MOD_NUM,Customer modification" line.long 0x10 "AXI_COMP_ID_0,AXI interconnect - component ID0" hexmask.long.byte 0x10 0.--7. 1. "PREAMBLE,Preamble bits 0 to 7" line.long 0x14 "AXI_COMP_ID_1,AXI interconnect - component ID1" hexmask.long.byte 0x14 4.--7. 1. "CLASS,Component class" hexmask.long.byte 0x14 0.--3. 1. "PREAMBLE,Preamble bits 8 to 11" line.long 0x18 "AXI_COMP_ID_2,AXI interconnect - component ID2" hexmask.long.byte 0x18 0.--7. 1. "PREAMBLE,Preamble bits 12 to 19" line.long 0x1C "AXI_COMP_ID_3,AXI interconnect - component ID3" hexmask.long.byte 0x1C 0.--7. 1. "PREAMBLE,Preamble bits 20 to 27" group.long 0x2008++0x3 line.long 0x0 "AXI_TARG1_FN_MOD_ISS_BM,AXI interconnect - TARG x bus matrix issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Switch matrix write issuing override for" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x3008++0x3 line.long 0x0 "AXI_TARG2_FN_MOD_ISS_BM,AXI interconnect - TARG x bus matrix issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Switch matrix write issuing override for" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x4008++0x3 line.long 0x0 "AXI_TARG3_FN_MOD_ISS_BM,AXI interconnect - TARG x bus matrix issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Switch matrix write issuing override for" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x5008++0x3 line.long 0x0 "AXI_TARG4_FN_MOD_ISS_BM,AXI interconnect - TARG x bus matrix issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Switch matrix write issuing override for" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x6008++0x3 line.long 0x0 "AXI_TARG5_FN_MOD_ISS_BM,AXI interconnect - TARG x bus matrix issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Switch matrix write issuing override for" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x7008++0x3 line.long 0x0 "AXI_TARG6_FN_MOD_ISS_BM,AXI interconnect - TARG x bus matrix issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Switch matrix write issuing override for" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x800C++0x3 line.long 0x0 "AXI_TARG7_FN_MOD_ISS_BM,AXI interconnect - TARG x bus matrix issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Switch matrix write issuing override for" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,READ_ISS_OVERRIDE" "0,1" group.long 0x2024++0x3 line.long 0x0 "AXI_TARG1_FN_MOD2,AXI interconnect - TARG x bus matrix" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the" "0,1" group.long 0x3024++0x3 line.long 0x0 "AXI_TARG2_FN_MOD2,AXI interconnect - TARG x bus matrix" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the" "0,1" group.long 0x8024++0x3 line.long 0x0 "AXI_TARG7_FN_MOD2,AXI interconnect - TARG x bus matrix" bitfld.long 0x0 0. "BYPASS_MERGE,Disable packing of beats to match the" "0,1" group.long 0x202C++0x3 line.long 0x0 "AXI_TARG1_FN_MOD_LB,AXI interconnect - TARG x long burst" bitfld.long 0x0 0. "FN_MOD_LB,Controls burst breaking of long" "0,1" group.long 0x302C++0x3 line.long 0x0 "AXI_TARG2_FN_MOD_LB,AXI interconnect - TARG x long burst" bitfld.long 0x0 0. "FN_MOD_LB,Controls burst breaking of long" "0,1" group.long 0x2108++0x3 line.long 0x0 "AXI_TARG1_FN_MOD,AXI interconnect - TARG x long burst" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override AMIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override AMIB read issuing" "0,1" group.long 0x3108++0x3 line.long 0x0 "AXI_TARG2_FN_MOD,AXI interconnect - TARG x long burst" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override AMIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override AMIB read issuing" "0,1" group.long 0x8108++0x3 line.long 0x0 "AXI_TARG7_FN_MOD,AXI interconnect - TARG x long burst" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override AMIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override AMIB read issuing" "0,1" group.long 0x42024++0x3 line.long 0x0 "AXI_INI1_FN_MOD2,AXI interconnect - INI x functionality" bitfld.long 0x0 0. "BYPASS_MERGE,Disables alteration of transactions by" "0,1" group.long 0x44024++0x3 line.long 0x0 "AXI_INI3_FN_MOD2,AXI interconnect - INI x functionality" bitfld.long 0x0 0. "BYPASS_MERGE,Disables alteration of transactions by" "0,1" group.long 0x42028++0x3 line.long 0x0 "AXI_INI1_FN_MOD_AHB,AXI interconnect - INI x AHB functionality" bitfld.long 0x0 1. "WR_INC_OVERRIDE,Converts all AHB-Lite read transactions" "0,1" bitfld.long 0x0 0. "RD_INC_OVERRIDE,Converts all AHB-Lite write transactions" "0,1" group.long 0x44028++0x3 line.long 0x0 "AXI_INI3_FN_MOD_AHB,AXI interconnect - INI x AHB functionality" bitfld.long 0x0 1. "WR_INC_OVERRIDE,Converts all AHB-Lite read transactions" "0,1" bitfld.long 0x0 0. "RD_INC_OVERRIDE,Converts all AHB-Lite write transactions" "0,1" group.long 0x42100++0x3 line.long 0x0 "AXI_INI1_READ_QOS,AXI interconnect - INI x read QoS" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,Read channel QoS setting" group.long 0x43100++0x3 line.long 0x0 "AXI_INI2_READ_QOS,AXI interconnect - INI x read QoS" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,Read channel QoS setting" group.long 0x44100++0x3 line.long 0x0 "AXI_INI3_READ_QOS,AXI interconnect - INI x read QoS" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,Read channel QoS setting" group.long 0x45100++0x3 line.long 0x0 "AXI_INI4_READ_QOS,AXI interconnect - INI x read QoS" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,Read channel QoS setting" group.long 0x46100++0x3 line.long 0x0 "AXI_INI5_READ_QOS,AXI interconnect - INI x read QoS" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,Read channel QoS setting" group.long 0x47100++0x3 line.long 0x0 "AXI_INI6_READ_QOS,AXI interconnect - INI x read QoS" hexmask.long.byte 0x0 0.--3. 1. "AR_QOS,Read channel QoS setting" group.long 0x42104++0x3 line.long 0x0 "AXI_INI1_WRITE_QOS,AXI interconnect - INI x write QoS" hexmask.long.byte 0x0 0.--3. 1. "AW_QOS,Write channel QoS setting" group.long 0x43104++0x3 line.long 0x0 "AXI_INI2_WRITE_QOS,AXI interconnect - INI x write QoS" hexmask.long.byte 0x0 0.--3. 1. "AW_QOS,Write channel QoS setting" group.long 0x44104++0x3 line.long 0x0 "AXI_INI3_WRITE_QOS,AXI interconnect - INI x write QoS" hexmask.long.byte 0x0 0.--3. 1. "AW_QOS,Write channel QoS setting" group.long 0x45104++0x3 line.long 0x0 "AXI_INI4_WRITE_QOS,AXI interconnect - INI x write QoS" hexmask.long.byte 0x0 0.--3. 1. "AW_QOS,Write channel QoS setting" group.long 0x46104++0x3 line.long 0x0 "AXI_INI5_WRITE_QOS,AXI interconnect - INI x write QoS" hexmask.long.byte 0x0 0.--3. 1. "AW_QOS,Write channel QoS setting" group.long 0x47104++0x3 line.long 0x0 "AXI_INI6_WRITE_QOS,AXI interconnect - INI x write QoS" hexmask.long.byte 0x0 0.--3. 1. "AW_QOS,Write channel QoS setting" group.long 0x42108++0x3 line.long 0x0 "AXI_INI1_FN_MOD,AXI interconnect - INI x issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override ASIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override ASIB read issuing" "0,1" group.long 0x43108++0x3 line.long 0x0 "AXI_INI2_FN_MOD,AXI interconnect - INI x issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override ASIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override ASIB read issuing" "0,1" group.long 0x44108++0x3 line.long 0x0 "AXI_INI3_FN_MOD,AXI interconnect - INI x issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override ASIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override ASIB read issuing" "0,1" group.long 0x45108++0x3 line.long 0x0 "AXI_INI4_FN_MOD,AXI interconnect - INI x issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override ASIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override ASIB read issuing" "0,1" group.long 0x46108++0x3 line.long 0x0 "AXI_INI5_FN_MOD,AXI interconnect - INI x issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override ASIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override ASIB read issuing" "0,1" group.long 0x47108++0x3 line.long 0x0 "AXI_INI6_FN_MOD,AXI interconnect - INI x issuing" bitfld.long 0x0 1. "WRITE_ISS_OVERRIDE,Override ASIB write issuing" "0,1" bitfld.long 0x0 0. "READ_ISS_OVERRIDE,Override ASIB read issuing" "0,1" tree.end tree "BDMA (Basic Direct Memory Access Controller)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")) tree "BDMA" base ad:0x58025400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) rgroup.long 0x0++0x3 line.long 0x0 "BDMA_ISR,BDMA interrupt status register" bitfld.long 0x0 31. "TEIF7,transfer error (TE) flag for channel 7" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 30. "HTIF7,half transfer (HT) flag for channel 7" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 29. "TCIF7,transfer complete (TC) flag for channel 7" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 28. "GIF7,global interrupt flag for channel 7" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 27. "TEIF6,transfer error (TE) flag for channel 6" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 26. "HTIF6,half transfer (HT) flag for channel 6" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 25. "TCIF6,transfer complete (TC) flag for channel 6" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 24. "GIF6,global interrupt flag for channel 6" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 23. "TEIF5,transfer error (TE) flag for channel 5" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 22. "HTIF5,half transfer (HT) flag for channel 5" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 21. "TCIF5,transfer complete (TC) flag for channel 5" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 20. "GIF5,global interrupt flag for channel 5" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 19. "TEIF4,transfer error (TE) flag for channel 4" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 18. "HTIF4,half transfer (HT) flag for channel 4" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 17. "TCIF4,transfer complete (TC) flag for channel 4" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 16. "GIF4,global interrupt flag for channel 4" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 15. "TEIF3,transfer error (TE) flag for channel 3" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 14. "HTIF3,half transfer (HT) flag for channel 3" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 13. "TCIF3,transfer complete (TC) flag for channel 3" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 12. "GIF3,global interrupt flag for channel 3" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 11. "TEIF2,transfer error (TE) flag for channel 2" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 10. "HTIF2,half transfer (HT) flag for channel 2" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 9. "TCIF2,transfer complete (TC) flag for channel 2" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 8. "GIF2,global interrupt flag for channel 2" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 7. "TEIF1,transfer error (TE) flag for channel 1" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 6. "HTIF1,half transfer (HT) flag for channel 1" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 5. "TCIF1,transfer complete (TC) flag for channel 1" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 4. "GIF1,global interrupt flag for channel 1" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 3. "TEIF0,transfer error (TE) flag for channel 0" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 2. "HTIF0,half transfer (HT) flag for channel 0" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 1. "TCIF0,transfer complete (TC) flag for channel 0" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 0. "GIF0,global interrupt flag for channel 0" "0: no TE HT or TC event,1: a TE HT or TC event occurred" wgroup.long 0x4++0x3 line.long 0x0 "BDMA_IFCR,BDMA interrupt flag clear register" bitfld.long 0x0 31. "CTEIF7,transfer error flag clear for channel 7" "0,1" bitfld.long 0x0 30. "CHTIF7,half transfer flag clear for channel 7" "0,1" newline bitfld.long 0x0 29. "CTCIF7,transfer complete flag clear for channel 7" "0,1" bitfld.long 0x0 28. "CGIF7,global interrupt flag clear for channel 7" "0,1" newline bitfld.long 0x0 27. "CTEIF6,transfer error flag clear for channel 6" "0,1" bitfld.long 0x0 26. "CHTIF6,half transfer flag clear for channel 6" "0,1" newline bitfld.long 0x0 25. "CTCIF6,transfer complete flag clear for channel 6" "0,1" bitfld.long 0x0 24. "CGIF6,global interrupt flag clear for channel 6" "0,1" newline bitfld.long 0x0 23. "CTEIF5,transfer error flag clear for channel 5" "0,1" bitfld.long 0x0 22. "CHTIF5,half transfer flag clear for channel 5" "0,1" newline bitfld.long 0x0 21. "CTCIF5,transfer complete flag clear for channel 5" "0,1" bitfld.long 0x0 20. "CGIF5,global interrupt flag clear for channel 5" "0,1" newline bitfld.long 0x0 19. "CTEIF4,transfer error flag clear for channel 4" "0,1" bitfld.long 0x0 18. "CHTIF4,half transfer flag clear for channel 4" "0,1" newline bitfld.long 0x0 17. "CTCIF4,transfer complete flag clear for channel 4" "0,1" bitfld.long 0x0 16. "CGIF4,global interrupt flag clear for channel 4" "0,1" newline bitfld.long 0x0 15. "CTEIF3,transfer error flag clear for channel 3" "0,1" bitfld.long 0x0 14. "CHTIF3,half transfer flag clear for channel 3" "0,1" newline bitfld.long 0x0 13. "CTCIF3,transfer complete flag clear for channel 3" "0,1" bitfld.long 0x0 12. "CGIF3,global interrupt flag clear for channel 3" "0,1" newline bitfld.long 0x0 11. "CTEIF2,transfer error flag clear for channel 2" "0,1" bitfld.long 0x0 10. "CHTIF2,half transfer flag clear for channe2" "0,1" newline bitfld.long 0x0 9. "CTCIF2,transfer complete flag clear for channel 2" "0,1" bitfld.long 0x0 8. "CGIF2,global interrupt flag clear for channel 2" "0,1" newline bitfld.long 0x0 7. "CTEIF1,transfer error flag clear for channel 1" "0,1" bitfld.long 0x0 6. "CHTIF1,half transfer flag clear for channel 1" "0,1" newline bitfld.long 0x0 5. "CTCIF1,transfer complete flag clear for channel 1" "0,1" bitfld.long 0x0 4. "CGIF1,global interrupt flag clear for channel 0" "0,1" newline bitfld.long 0x0 3. "CTEIF0,transfer error flag clear for channel 0" "0,1" bitfld.long 0x0 2. "CHTIF0,half transfer flag clear for channel 0" "0,1" newline bitfld.long 0x0 1. "CTCIF0,transfer complete flag clear for channel 0" "0,1" bitfld.long 0x0 0. "CGIF0,global interrupt flag clear for channel 0" "0,1" group.long 0x8++0x9F line.long 0x0 "BDMA_CCR0,BDMA channel 0 configuration register" bitfld.long 0x0 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x0 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x4 "BDMA_CNDTR0," hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x8 "BDMA_CPAR0," hexmask.long 0x8 0.--31. 1. "PA,peripheral address" line.long 0xC "BDMA_CM0AR0," hexmask.long 0xC 0.--31. 1. "MA,peripheral address" line.long 0x10 "BDMA_CM1AR0," hexmask.long 0x10 0.--31. 1. "MA,peripheral address" line.long 0x14 "BDMA_CCR1,BDMA channel 1 configuration register" bitfld.long 0x14 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x14 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x14 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x14 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x14 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x14 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x14 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x14 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x14 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x14 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x14 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x14 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x14 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x14 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x18 "BDMA_CNDTR1," hexmask.long.word 0x18 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x1C "BDMA_CPAR1," hexmask.long 0x1C 0.--31. 1. "PA,peripheral address" line.long 0x20 "BDMA_CM0AR1," hexmask.long 0x20 0.--31. 1. "MA,peripheral address" line.long 0x24 "BDMA_CM1AR1," hexmask.long 0x24 0.--31. 1. "MA,peripheral address" line.long 0x28 "BDMA_CCR2,BDMA channel 2 configuration register" bitfld.long 0x28 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x28 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x28 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x28 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x28 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x28 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x28 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x28 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x28 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x28 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x28 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x28 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x28 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x28 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x2C "BDMA_CNDTR2," hexmask.long.word 0x2C 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x30 "BDMA_CPAR2," hexmask.long 0x30 0.--31. 1. "PA,peripheral address" line.long 0x34 "BDMA_CM0AR2," hexmask.long 0x34 0.--31. 1. "MA,peripheral address" line.long 0x38 "BDMA_CM1AR2," hexmask.long 0x38 0.--31. 1. "MA,peripheral address" line.long 0x3C "BDMA_CCR3,BDMA channel 3 configuration register" bitfld.long 0x3C 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x3C 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x3C 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x3C 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x3C 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x3C 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x3C 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x3C 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x3C 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x3C 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x3C 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x3C 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x3C 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x3C 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x40 "BDMA_CNDTR3," hexmask.long.word 0x40 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x44 "BDMA_CPAR3," hexmask.long 0x44 0.--31. 1. "PA,peripheral address" line.long 0x48 "BDMA_CM0AR3," hexmask.long 0x48 0.--31. 1. "MA,peripheral address" line.long 0x4C "BDMA_CM1AR3," hexmask.long 0x4C 0.--31. 1. "MA,peripheral address" line.long 0x50 "BDMA_CCR4,BDMA channel 4 configuration register" bitfld.long 0x50 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x50 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x50 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x50 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x50 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x50 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x50 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x50 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x50 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x50 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x50 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x50 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x50 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x50 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x54 "BDMA_CNDTR4," hexmask.long.word 0x54 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x58 "BDMA_CPAR4," hexmask.long 0x58 0.--31. 1. "PA,peripheral address" line.long 0x5C "BDMA_CM0AR4," hexmask.long 0x5C 0.--31. 1. "MA,peripheral address" line.long 0x60 "BDMA_CM1AR4," hexmask.long 0x60 0.--31. 1. "MA,peripheral address" line.long 0x64 "BDMA_CCR5,BDMA channel 5 configuration register" bitfld.long 0x64 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x64 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x64 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x64 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x64 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x64 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x64 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x64 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x64 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x64 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x64 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x64 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x64 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x64 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x68 "BDMA_CNDTR5," hexmask.long.word 0x68 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x6C "BDMA_CPAR5," hexmask.long 0x6C 0.--31. 1. "PA,peripheral address" line.long 0x70 "BDMA_CM0AR5," hexmask.long 0x70 0.--31. 1. "MA,peripheral address" line.long 0x74 "BDMA_CM1AR5," hexmask.long 0x74 0.--31. 1. "MA,peripheral address" line.long 0x78 "BDMA_CCR6,BDMA channel 6 configuration register" bitfld.long 0x78 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x78 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x78 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x78 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x78 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x78 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x78 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x78 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x78 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x78 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x78 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x78 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x78 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x78 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x7C "BDMA_CNDTR6," hexmask.long.word 0x7C 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x80 "BDMA_CPAR6," hexmask.long 0x80 0.--31. 1. "PA,peripheral address" line.long 0x84 "BDMA_CM0AR6," hexmask.long 0x84 0.--31. 1. "MA,peripheral address" line.long 0x88 "BDMA_CM1AR6," hexmask.long 0x88 0.--31. 1. "MA,peripheral address" line.long 0x8C "BDMA_CCR7,BDMA channel 7 configuration register" bitfld.long 0x8C 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x8C 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x8C 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x8C 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x8C 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x8C 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x8C 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x8C 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x8C 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x8C 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x8C 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x8C 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x8C 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x8C 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x90 "BDMA_CNDTR7," hexmask.long.word 0x90 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x94 "BDMA_CPAR7," hexmask.long 0x94 0.--31. 1. "PA,peripheral address" line.long 0x98 "BDMA_CM0AR7," hexmask.long 0x98 0.--31. 1. "MA,peripheral address" line.long 0x9C "BDMA_CM1AR7," hexmask.long 0x9C 0.--31. 1. "MA,peripheral address" endif sif (cpuis("STM32H745??-CM4")) rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" newline bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" newline bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" newline bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" endif tree.end endif sif (cpuis("STM32H745??-CM7")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" tree.end endif sif (cpuis("STM32H750*")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "BDMA_ISR,BDMA interrupt status register" bitfld.long 0x0 31. "TEIF7,transfer error (TE) flag for channel 7" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 30. "HTIF7,half transfer (HT) flag for channel 7" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 29. "TCIF7,transfer complete (TC) flag for channel 7" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 28. "GIF7,global interrupt flag for channel 7" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 27. "TEIF6,transfer error (TE) flag for channel 6" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 26. "HTIF6,half transfer (HT) flag for channel 6" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 25. "TCIF6,transfer complete (TC) flag for channel 6" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 24. "GIF6,global interrupt flag for channel 6" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 23. "TEIF5,transfer error (TE) flag for channel 5" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 22. "HTIF5,half transfer (HT) flag for channel 5" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 21. "TCIF5,transfer complete (TC) flag for channel 5" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 20. "GIF5,global interrupt flag for channel 5" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 19. "TEIF4,transfer error (TE) flag for channel 4" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 18. "HTIF4,half transfer (HT) flag for channel 4" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 17. "TCIF4,transfer complete (TC) flag for channel 4" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 16. "GIF4,global interrupt flag for channel 4" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 15. "TEIF3,transfer error (TE) flag for channel 3" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 14. "HTIF3,half transfer (HT) flag for channel 3" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 13. "TCIF3,transfer complete (TC) flag for channel 3" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 12. "GIF3,global interrupt flag for channel 3" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 11. "TEIF2,transfer error (TE) flag for channel 2" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 10. "HTIF2,half transfer (HT) flag for channel 2" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 9. "TCIF2,transfer complete (TC) flag for channel 2" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 8. "GIF2,global interrupt flag for channel 2" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 7. "TEIF1,transfer error (TE) flag for channel 1" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 6. "HTIF1,half transfer (HT) flag for channel 1" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 5. "TCIF1,transfer complete (TC) flag for channel 1" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 4. "GIF1,global interrupt flag for channel 1" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 3. "TEIF0,transfer error (TE) flag for channel 0" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 2. "HTIF0,half transfer (HT) flag for channel 0" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 1. "TCIF0,transfer complete (TC) flag for channel 0" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 0. "GIF0,global interrupt flag for channel 0" "0: no TE HT or TC event,1: a TE HT or TC event occurred" wgroup.long 0x4++0x3 line.long 0x0 "BDMA_IFCR,BDMA interrupt flag clear register" bitfld.long 0x0 31. "CTEIF7,transfer error flag clear for channel 7" "0,1" bitfld.long 0x0 30. "CHTIF7,half transfer flag clear for channel 7" "0,1" newline bitfld.long 0x0 29. "CTCIF7,transfer complete flag clear for channel 7" "0,1" bitfld.long 0x0 28. "CGIF7,global interrupt flag clear for channel 7" "0,1" newline bitfld.long 0x0 27. "CTEIF6,transfer error flag clear for channel 6" "0,1" bitfld.long 0x0 26. "CHTIF6,half transfer flag clear for channel 6" "0,1" newline bitfld.long 0x0 25. "CTCIF6,transfer complete flag clear for channel 6" "0,1" bitfld.long 0x0 24. "CGIF6,global interrupt flag clear for channel 6" "0,1" newline bitfld.long 0x0 23. "CTEIF5,transfer error flag clear for channel 5" "0,1" bitfld.long 0x0 22. "CHTIF5,half transfer flag clear for channel 5" "0,1" newline bitfld.long 0x0 21. "CTCIF5,transfer complete flag clear for channel 5" "0,1" bitfld.long 0x0 20. "CGIF5,global interrupt flag clear for channel 5" "0,1" newline bitfld.long 0x0 19. "CTEIF4,transfer error flag clear for channel 4" "0,1" bitfld.long 0x0 18. "CHTIF4,half transfer flag clear for channel 4" "0,1" newline bitfld.long 0x0 17. "CTCIF4,transfer complete flag clear for channel 4" "0,1" bitfld.long 0x0 16. "CGIF4,global interrupt flag clear for channel 4" "0,1" newline bitfld.long 0x0 15. "CTEIF3,transfer error flag clear for channel 3" "0,1" bitfld.long 0x0 14. "CHTIF3,half transfer flag clear for channel 3" "0,1" newline bitfld.long 0x0 13. "CTCIF3,transfer complete flag clear for channel 3" "0,1" bitfld.long 0x0 12. "CGIF3,global interrupt flag clear for channel 3" "0,1" newline bitfld.long 0x0 11. "CTEIF2,transfer error flag clear for channel 2" "0,1" bitfld.long 0x0 10. "CHTIF2,half transfer flag clear for channe2" "0,1" newline bitfld.long 0x0 9. "CTCIF2,transfer complete flag clear for channel 2" "0,1" bitfld.long 0x0 8. "CGIF2,global interrupt flag clear for channel 2" "0,1" newline bitfld.long 0x0 7. "CTEIF1,transfer error flag clear for channel 1" "0,1" bitfld.long 0x0 6. "CHTIF1,half transfer flag clear for channel 1" "0,1" newline bitfld.long 0x0 5. "CTCIF1,transfer complete flag clear for channel 1" "0,1" bitfld.long 0x0 4. "CGIF1,global interrupt flag clear for channel 0" "0,1" newline bitfld.long 0x0 3. "CTEIF0,transfer error flag clear for channel 0" "0,1" bitfld.long 0x0 2. "CHTIF0,half transfer flag clear for channel 0" "0,1" newline bitfld.long 0x0 1. "CTCIF0,transfer complete flag clear for channel 0" "0,1" bitfld.long 0x0 0. "CGIF0,global interrupt flag clear for channel 0" "0,1" group.long 0x8++0x9F line.long 0x0 "BDMA_CCR0,BDMA channel 0 configuration register" bitfld.long 0x0 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x0 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x4 "BDMA_CNDTR0," hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x8 "BDMA_CPAR0," hexmask.long 0x8 0.--31. 1. "PA,peripheral address" line.long 0xC "BDMA_CM0AR0," hexmask.long 0xC 0.--31. 1. "MA,peripheral address" line.long 0x10 "BDMA_CM1AR0," hexmask.long 0x10 0.--31. 1. "MA,peripheral address" line.long 0x14 "BDMA_CCR1,BDMA channel 1 configuration register" bitfld.long 0x14 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x14 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x14 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x14 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x14 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x14 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x14 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x14 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x14 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x14 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x14 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x14 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x14 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x14 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x18 "BDMA_CNDTR1," hexmask.long.word 0x18 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x1C "BDMA_CPAR1," hexmask.long 0x1C 0.--31. 1. "PA,peripheral address" line.long 0x20 "BDMA_CM0AR1," hexmask.long 0x20 0.--31. 1. "MA,peripheral address" line.long 0x24 "BDMA_CM1AR1," hexmask.long 0x24 0.--31. 1. "MA,peripheral address" line.long 0x28 "BDMA_CCR2,BDMA channel 2 configuration register" bitfld.long 0x28 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x28 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x28 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x28 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x28 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x28 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x28 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x28 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x28 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x28 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x28 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x28 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x28 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x28 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x2C "BDMA_CNDTR2," hexmask.long.word 0x2C 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x30 "BDMA_CPAR2," hexmask.long 0x30 0.--31. 1. "PA,peripheral address" line.long 0x34 "BDMA_CM0AR2," hexmask.long 0x34 0.--31. 1. "MA,peripheral address" line.long 0x38 "BDMA_CM1AR2," hexmask.long 0x38 0.--31. 1. "MA,peripheral address" line.long 0x3C "BDMA_CCR3,BDMA channel 3 configuration register" bitfld.long 0x3C 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x3C 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x3C 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x3C 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x3C 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x3C 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x3C 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x3C 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x3C 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x3C 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x3C 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x3C 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x3C 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x3C 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x40 "BDMA_CNDTR3," hexmask.long.word 0x40 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x44 "BDMA_CPAR3," hexmask.long 0x44 0.--31. 1. "PA,peripheral address" line.long 0x48 "BDMA_CM0AR3," hexmask.long 0x48 0.--31. 1. "MA,peripheral address" line.long 0x4C "BDMA_CM1AR3," hexmask.long 0x4C 0.--31. 1. "MA,peripheral address" line.long 0x50 "BDMA_CCR4,BDMA channel 4 configuration register" bitfld.long 0x50 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x50 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x50 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x50 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x50 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x50 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x50 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x50 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x50 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x50 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x50 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x50 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x50 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x50 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x54 "BDMA_CNDTR4," hexmask.long.word 0x54 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x58 "BDMA_CPAR4," hexmask.long 0x58 0.--31. 1. "PA,peripheral address" line.long 0x5C "BDMA_CM0AR4," hexmask.long 0x5C 0.--31. 1. "MA,peripheral address" line.long 0x60 "BDMA_CM1AR4," hexmask.long 0x60 0.--31. 1. "MA,peripheral address" line.long 0x64 "BDMA_CCR5,BDMA channel 5 configuration register" bitfld.long 0x64 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x64 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x64 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x64 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x64 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x64 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x64 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x64 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x64 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x64 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x64 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x64 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x64 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x64 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x68 "BDMA_CNDTR5," hexmask.long.word 0x68 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x6C "BDMA_CPAR5," hexmask.long 0x6C 0.--31. 1. "PA,peripheral address" line.long 0x70 "BDMA_CM0AR5," hexmask.long 0x70 0.--31. 1. "MA,peripheral address" line.long 0x74 "BDMA_CM1AR5," hexmask.long 0x74 0.--31. 1. "MA,peripheral address" line.long 0x78 "BDMA_CCR6,BDMA channel 6 configuration register" bitfld.long 0x78 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x78 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x78 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x78 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x78 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x78 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x78 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x78 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x78 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x78 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x78 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x78 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x78 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x78 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x7C "BDMA_CNDTR6," hexmask.long.word 0x7C 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x80 "BDMA_CPAR6," hexmask.long 0x80 0.--31. 1. "PA,peripheral address" line.long 0x84 "BDMA_CM0AR6," hexmask.long 0x84 0.--31. 1. "MA,peripheral address" line.long 0x88 "BDMA_CM1AR6," hexmask.long 0x88 0.--31. 1. "MA,peripheral address" line.long 0x8C "BDMA_CCR7,BDMA channel 7 configuration register" bitfld.long 0x8C 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x8C 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x8C 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x8C 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x8C 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x8C 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x8C 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x8C 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x8C 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x8C 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x8C 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x8C 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x8C 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x8C 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x90 "BDMA_CNDTR7," hexmask.long.word 0x90 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x94 "BDMA_CPAR7," hexmask.long 0x94 0.--31. 1. "PA,peripheral address" line.long 0x98 "BDMA_CM0AR7," hexmask.long 0x98 0.--31. 1. "MA,peripheral address" line.long 0x9C "BDMA_CM1AR7," hexmask.long 0x9C 0.--31. 1. "MA,peripheral address" tree.end endif sif (cpuis("STM32H753*")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "BDMA_ISR,BDMA interrupt status register" bitfld.long 0x0 31. "TEIF7,transfer error (TE) flag for channel 7" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 30. "HTIF7,half transfer (HT) flag for channel 7" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 29. "TCIF7,transfer complete (TC) flag for channel 7" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 28. "GIF7,global interrupt flag for channel 7" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 27. "TEIF6,transfer error (TE) flag for channel 6" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 26. "HTIF6,half transfer (HT) flag for channel 6" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 25. "TCIF6,transfer complete (TC) flag for channel 6" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 24. "GIF6,global interrupt flag for channel 6" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 23. "TEIF5,transfer error (TE) flag for channel 5" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 22. "HTIF5,half transfer (HT) flag for channel 5" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 21. "TCIF5,transfer complete (TC) flag for channel 5" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 20. "GIF5,global interrupt flag for channel 5" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 19. "TEIF4,transfer error (TE) flag for channel 4" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 18. "HTIF4,half transfer (HT) flag for channel 4" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 17. "TCIF4,transfer complete (TC) flag for channel 4" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 16. "GIF4,global interrupt flag for channel 4" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 15. "TEIF3,transfer error (TE) flag for channel 3" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 14. "HTIF3,half transfer (HT) flag for channel 3" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 13. "TCIF3,transfer complete (TC) flag for channel 3" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 12. "GIF3,global interrupt flag for channel 3" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 11. "TEIF2,transfer error (TE) flag for channel 2" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 10. "HTIF2,half transfer (HT) flag for channel 2" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 9. "TCIF2,transfer complete (TC) flag for channel 2" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 8. "GIF2,global interrupt flag for channel 2" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 7. "TEIF1,transfer error (TE) flag for channel 1" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 6. "HTIF1,half transfer (HT) flag for channel 1" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 5. "TCIF1,transfer complete (TC) flag for channel 1" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 4. "GIF1,global interrupt flag for channel 1" "0: no TE HT or TC event,1: a TE HT or TC event occurred" newline bitfld.long 0x0 3. "TEIF0,transfer error (TE) flag for channel 0" "0: no TE event,1: a TE event occurred" bitfld.long 0x0 2. "HTIF0,half transfer (HT) flag for channel 0" "0: no HT event,1: a HT event occurred" newline bitfld.long 0x0 1. "TCIF0,transfer complete (TC) flag for channel 0" "0: no TC event,1: a TC event occurred" bitfld.long 0x0 0. "GIF0,global interrupt flag for channel 0" "0: no TE HT or TC event,1: a TE HT or TC event occurred" wgroup.long 0x4++0x3 line.long 0x0 "BDMA_IFCR,BDMA interrupt flag clear register" bitfld.long 0x0 31. "CTEIF7,transfer error flag clear for channel 7" "0,1" bitfld.long 0x0 30. "CHTIF7,half transfer flag clear for channel 7" "0,1" newline bitfld.long 0x0 29. "CTCIF7,transfer complete flag clear for channel 7" "0,1" bitfld.long 0x0 28. "CGIF7,global interrupt flag clear for channel 7" "0,1" newline bitfld.long 0x0 27. "CTEIF6,transfer error flag clear for channel 6" "0,1" bitfld.long 0x0 26. "CHTIF6,half transfer flag clear for channel 6" "0,1" newline bitfld.long 0x0 25. "CTCIF6,transfer complete flag clear for channel 6" "0,1" bitfld.long 0x0 24. "CGIF6,global interrupt flag clear for channel 6" "0,1" newline bitfld.long 0x0 23. "CTEIF5,transfer error flag clear for channel 5" "0,1" bitfld.long 0x0 22. "CHTIF5,half transfer flag clear for channel 5" "0,1" newline bitfld.long 0x0 21. "CTCIF5,transfer complete flag clear for channel 5" "0,1" bitfld.long 0x0 20. "CGIF5,global interrupt flag clear for channel 5" "0,1" newline bitfld.long 0x0 19. "CTEIF4,transfer error flag clear for channel 4" "0,1" bitfld.long 0x0 18. "CHTIF4,half transfer flag clear for channel 4" "0,1" newline bitfld.long 0x0 17. "CTCIF4,transfer complete flag clear for channel 4" "0,1" bitfld.long 0x0 16. "CGIF4,global interrupt flag clear for channel 4" "0,1" newline bitfld.long 0x0 15. "CTEIF3,transfer error flag clear for channel 3" "0,1" bitfld.long 0x0 14. "CHTIF3,half transfer flag clear for channel 3" "0,1" newline bitfld.long 0x0 13. "CTCIF3,transfer complete flag clear for channel 3" "0,1" bitfld.long 0x0 12. "CGIF3,global interrupt flag clear for channel 3" "0,1" newline bitfld.long 0x0 11. "CTEIF2,transfer error flag clear for channel 2" "0,1" bitfld.long 0x0 10. "CHTIF2,half transfer flag clear for channe2" "0,1" newline bitfld.long 0x0 9. "CTCIF2,transfer complete flag clear for channel 2" "0,1" bitfld.long 0x0 8. "CGIF2,global interrupt flag clear for channel 2" "0,1" newline bitfld.long 0x0 7. "CTEIF1,transfer error flag clear for channel 1" "0,1" bitfld.long 0x0 6. "CHTIF1,half transfer flag clear for channel 1" "0,1" newline bitfld.long 0x0 5. "CTCIF1,transfer complete flag clear for channel 1" "0,1" bitfld.long 0x0 4. "CGIF1,global interrupt flag clear for channel 0" "0,1" newline bitfld.long 0x0 3. "CTEIF0,transfer error flag clear for channel 0" "0,1" bitfld.long 0x0 2. "CHTIF0,half transfer flag clear for channel 0" "0,1" newline bitfld.long 0x0 1. "CTCIF0,transfer complete flag clear for channel 0" "0,1" bitfld.long 0x0 0. "CGIF0,global interrupt flag clear for channel 0" "0,1" group.long 0x8++0x9F line.long 0x0 "BDMA_CCR0,BDMA channel 0 configuration register" bitfld.long 0x0 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x0 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x4 "BDMA_CNDTR0," hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x8 "BDMA_CPAR0," hexmask.long 0x8 0.--31. 1. "PA,peripheral address" line.long 0xC "BDMA_CM0AR0," hexmask.long 0xC 0.--31. 1. "MA,peripheral address" line.long 0x10 "BDMA_CM1AR0," hexmask.long 0x10 0.--31. 1. "MA,peripheral address" line.long 0x14 "BDMA_CCR1,BDMA channel 1 configuration register" bitfld.long 0x14 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x14 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x14 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x14 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x14 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x14 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x14 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x14 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x14 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x14 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x14 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x14 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x14 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x14 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x18 "BDMA_CNDTR1," hexmask.long.word 0x18 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x1C "BDMA_CPAR1," hexmask.long 0x1C 0.--31. 1. "PA,peripheral address" line.long 0x20 "BDMA_CM0AR1," hexmask.long 0x20 0.--31. 1. "MA,peripheral address" line.long 0x24 "BDMA_CM1AR1," hexmask.long 0x24 0.--31. 1. "MA,peripheral address" line.long 0x28 "BDMA_CCR2,BDMA channel 2 configuration register" bitfld.long 0x28 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x28 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x28 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x28 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x28 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x28 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x28 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x28 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x28 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x28 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x28 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x28 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x28 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x28 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x2C "BDMA_CNDTR2," hexmask.long.word 0x2C 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x30 "BDMA_CPAR2," hexmask.long 0x30 0.--31. 1. "PA,peripheral address" line.long 0x34 "BDMA_CM0AR2," hexmask.long 0x34 0.--31. 1. "MA,peripheral address" line.long 0x38 "BDMA_CM1AR2," hexmask.long 0x38 0.--31. 1. "MA,peripheral address" line.long 0x3C "BDMA_CCR3,BDMA channel 3 configuration register" bitfld.long 0x3C 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x3C 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x3C 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x3C 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x3C 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x3C 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x3C 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x3C 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x3C 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x3C 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x3C 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x3C 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x3C 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x3C 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x40 "BDMA_CNDTR3," hexmask.long.word 0x40 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x44 "BDMA_CPAR3," hexmask.long 0x44 0.--31. 1. "PA,peripheral address" line.long 0x48 "BDMA_CM0AR3," hexmask.long 0x48 0.--31. 1. "MA,peripheral address" line.long 0x4C "BDMA_CM1AR3," hexmask.long 0x4C 0.--31. 1. "MA,peripheral address" line.long 0x50 "BDMA_CCR4,BDMA channel 4 configuration register" bitfld.long 0x50 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x50 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x50 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x50 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x50 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x50 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x50 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x50 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x50 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x50 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x50 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x50 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x50 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x50 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x54 "BDMA_CNDTR4," hexmask.long.word 0x54 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x58 "BDMA_CPAR4," hexmask.long 0x58 0.--31. 1. "PA,peripheral address" line.long 0x5C "BDMA_CM0AR4," hexmask.long 0x5C 0.--31. 1. "MA,peripheral address" line.long 0x60 "BDMA_CM1AR4," hexmask.long 0x60 0.--31. 1. "MA,peripheral address" line.long 0x64 "BDMA_CCR5,BDMA channel 5 configuration register" bitfld.long 0x64 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x64 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x64 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x64 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x64 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x64 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x64 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x64 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x64 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x64 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x64 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x64 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x64 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x64 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x68 "BDMA_CNDTR5," hexmask.long.word 0x68 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x6C "BDMA_CPAR5," hexmask.long 0x6C 0.--31. 1. "PA,peripheral address" line.long 0x70 "BDMA_CM0AR5," hexmask.long 0x70 0.--31. 1. "MA,peripheral address" line.long 0x74 "BDMA_CM1AR5," hexmask.long 0x74 0.--31. 1. "MA,peripheral address" line.long 0x78 "BDMA_CCR6,BDMA channel 6 configuration register" bitfld.long 0x78 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x78 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x78 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x78 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x78 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x78 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x78 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x78 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x78 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x78 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x78 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x78 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x78 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x78 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x7C "BDMA_CNDTR6," hexmask.long.word 0x7C 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x80 "BDMA_CPAR6," hexmask.long 0x80 0.--31. 1. "PA,peripheral address" line.long 0x84 "BDMA_CM0AR6," hexmask.long 0x84 0.--31. 1. "MA,peripheral address" line.long 0x88 "BDMA_CM1AR6," hexmask.long 0x88 0.--31. 1. "MA,peripheral address" line.long 0x8C "BDMA_CCR7,BDMA channel 7 configuration register" bitfld.long 0x8C 16. "CT,current target memory of DMA transfer in double-buffer mode" "0: memory 0 (addressed by the BDMA_CM0AR pointer),1: memory 1 (addressed by the BDMA_CM1AR pointer)" bitfld.long 0x8C 15. "DBM,double-buffer mode" "0: disabled (no memory address switch at the end of..,1: enabled (memory address switched at the end of.." newline bitfld.long 0x8C 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled" bitfld.long 0x8C 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high" newline bitfld.long 0x8C 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?" bitfld.long 0x8C 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?" newline bitfld.long 0x8C 7. "MINC,memory increment mode" "0: disabled,1: enabled" bitfld.long 0x8C 6. "PINC,peripheral increment mode" "0: disabled,1: enabled" newline bitfld.long 0x8C 5. "CIRC,circular mode" "0: disabled,1: enabled" bitfld.long 0x8C 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory" newline bitfld.long 0x8C 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled" bitfld.long 0x8C 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled" newline bitfld.long 0x8C 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled" bitfld.long 0x8C 0. "EN,channel enable" "0: disabled,1: enabled" line.long 0x90 "BDMA_CNDTR7," hexmask.long.word 0x90 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)" line.long 0x94 "BDMA_CPAR7," hexmask.long 0x94 0.--31. 1. "PA,peripheral address" line.long 0x98 "BDMA_CM0AR7," hexmask.long 0x98 0.--31. 1. "MA,peripheral address" line.long 0x9C "BDMA_CM1AR7," hexmask.long 0x9C 0.--31. 1. "MA,peripheral address" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "BDMA" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR8,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR8,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR8,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CMAR8,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" tree.end endif sif (cpuis("STM32H7A3*")) tree "BDMA1" base ad:0x48022C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR0,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR0,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR0,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR0,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x18++0x3 line.long 0x0 "CM1AR0,This register must not be written when the" group.long 0x2C++0x3 line.long 0x0 "CM1AR1,BDMA_CMAR1" group.long 0x40++0x3 line.long 0x0 "CM1AR2,BDMA_CM1AR2" group.long 0x54++0x3 line.long 0x0 "CM1AR3,BDMA_CMAR3" group.long 0x68++0x3 line.long 0x0 "CM1AR4,BDMA_CM1AR4" group.long 0x7C++0x3 line.long 0x0 "CM1AR5,This register must not be written when the" group.long 0x90++0x3 line.long 0x0 "CM1AR6,This register must not be written when the" group.long 0xA4++0x3 line.long 0x0 "CM1AR7,This register must not be written when the" tree.end tree "BDMA2" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" newline bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" newline bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "CCR0,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR0,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR0,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR0,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "CM0AR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x18++0x3 line.long 0x0 "CM1AR0,This register must not be written when the" group.long 0x2C++0x3 line.long 0x0 "CM1AR1,BDMA_CMAR1" group.long 0x40++0x3 line.long 0x0 "CM1AR2,BDMA_CM1AR2" group.long 0x54++0x3 line.long 0x0 "CM1AR3,BDMA_CMAR3" group.long 0x68++0x3 line.long 0x0 "CM1AR4,BDMA_CM1AR4" group.long 0x7C++0x3 line.long 0x0 "CM1AR5,This register must not be written when the" group.long 0x90++0x3 line.long 0x0 "CM1AR6,This register must not be written when the" group.long 0xA4++0x3 line.long 0x0 "CM1AR7,This register must not be written when the" tree.end endif sif (cpuis("STM32H7B0*")) tree "BDMA2" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "BDMA_ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "BDMA_IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "BDMA_CCR0,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR0,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR0,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR0,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "BDMA_CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "BDMA_CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "BDMA_CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "BDMA_CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "BDMA_CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "BDMA_CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "BDMA_CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x18++0x3 line.long 0x0 "BDMA_CM1AR0,This register must not be written when the" group.long 0x2C++0x3 line.long 0x0 "BDMA_CM1AR1,BDMA_CMAR1" group.long 0x40++0x3 line.long 0x0 "BDMA_CM1AR2,BDMA_CM1AR2" group.long 0x54++0x3 line.long 0x0 "BDMA_CM1AR3,BDMA_CMAR3" group.long 0x68++0x3 line.long 0x0 "BDMA_CM1AR4,BDMA_CM1AR4" group.long 0x7C++0x3 line.long 0x0 "BDMA_CM1AR5,This register must not be written when the" group.long 0x90++0x3 line.long 0x0 "BDMA_CM1AR6,This register must not be written when the" group.long 0xA4++0x3 line.long 0x0 "BDMA_CM1AR7,This register must not be written when the" tree.end endif sif (cpuis("STM32H7B0*")) tree "BDMA1" base ad:0x48022C00 rgroup.long 0x0++0x3 line.long 0x0 "BDMA_ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "BDMA_IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "BDMA_CCR0,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR0,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR0,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR0,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "BDMA_CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "BDMA_CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "BDMA_CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "BDMA_CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "BDMA_CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "BDMA_CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "BDMA_CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x18++0x3 line.long 0x0 "BDMA_CM1AR0,This register must not be written when the" group.long 0x2C++0x3 line.long 0x0 "BDMA_CM1AR1,BDMA_CMAR1" group.long 0x40++0x3 line.long 0x0 "BDMA_CM1AR2,BDMA_CM1AR2" group.long 0x54++0x3 line.long 0x0 "BDMA_CM1AR3,BDMA_CMAR3" group.long 0x68++0x3 line.long 0x0 "BDMA_CM1AR4,BDMA_CM1AR4" group.long 0x7C++0x3 line.long 0x0 "BDMA_CM1AR5,This register must not be written when the" group.long 0x90++0x3 line.long 0x0 "BDMA_CM1AR6,This register must not be written when the" group.long 0xA4++0x3 line.long 0x0 "BDMA_CM1AR7,This register must not be written when the" tree.end endif sif (cpuis("STM32H7B3*")) tree "BDMA1" base ad:0x48022C00 rgroup.long 0x0++0x3 line.long 0x0 "BDMA_ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "BDMA_IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "BDMA_CCR0,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR0,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR0,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR0,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "BDMA_CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "BDMA_CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "BDMA_CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "BDMA_CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "BDMA_CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "BDMA_CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "BDMA_CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x18++0x3 line.long 0x0 "BDMA_CM1AR0,This register must not be written when the" group.long 0x2C++0x3 line.long 0x0 "BDMA_CM1AR1,BDMA_CMAR1" group.long 0x40++0x3 line.long 0x0 "BDMA_CM1AR2,BDMA_CM1AR2" group.long 0x54++0x3 line.long 0x0 "BDMA_CM1AR3,BDMA_CMAR3" group.long 0x68++0x3 line.long 0x0 "BDMA_CM1AR4,BDMA_CM1AR4" group.long 0x7C++0x3 line.long 0x0 "BDMA_CM1AR5,This register must not be written when the" group.long 0x90++0x3 line.long 0x0 "BDMA_CM1AR6,This register must not be written when the" group.long 0xA4++0x3 line.long 0x0 "BDMA_CM1AR7,This register must not be written when the" tree.end tree "BDMA2" base ad:0x58025400 rgroup.long 0x0++0x3 line.long 0x0 "BDMA_ISR,DMA interrupt status register" bitfld.long 0x0 31. "TEIF8,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 30. "HTIF8,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 29. "TCIF8,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 28. "GIF8,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 27. "TEIF7,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 26. "HTIF7,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 25. "TCIF7,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 24. "GIF7,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 23. "TEIF6,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 22. "HTIF6,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 21. "TCIF6,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 20. "GIF6,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 19. "TEIF5,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 18. "HTIF5,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 17. "TCIF5,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 16. "GIF5,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 15. "TEIF4,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 14. "HTIF4,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 13. "TCIF4,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 12. "GIF4,Channel x global interrupt flag (x =" "0,1" newline bitfld.long 0x0 11. "TEIF3,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 10. "HTIF3,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 9. "TCIF3,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 8. "GIF3,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 7. "TEIF2,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 6. "HTIF2,Channel x half transfer flag (x = 1..8)" "0,1" bitfld.long 0x0 5. "TCIF2,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 4. "GIF2,Channel x global interrupt flag (x =" "0,1" bitfld.long 0x0 3. "TEIF1,Channel x transfer error flag (x = 1..8)" "0,1" bitfld.long 0x0 2. "HTIF1,Channel x half transfer flag (x = 1..8)" "0,1" newline bitfld.long 0x0 1. "TCIF1,Channel x transfer complete flag (x =" "0,1" bitfld.long 0x0 0. "GIF1,Channel x global interrupt flag (x =" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "BDMA_IFCR,DMA interrupt flag clear" bitfld.long 0x0 31. "CTEIF8,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 30. "CHTIF8,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 29. "CTCIF8,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 28. "CGIF8,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 27. "CTEIF7,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 26. "CHTIF7,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 25. "CTCIF7,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 24. "CGIF7,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 23. "CTEIF6,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 22. "CHTIF6,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 21. "CTCIF6,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 20. "CGIF6,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 19. "CTEIF5,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 18. "CHTIF5,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 17. "CTCIF5,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 16. "CGIF5,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 15. "CTEIF4,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 14. "CHTIF4,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 13. "CTCIF4,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 12. "CGIF4,Channel x global interrupt clear This" "0,1" newline bitfld.long 0x0 11. "CTEIF3,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 10. "CHTIF3,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 9. "CTCIF3,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 8. "CGIF3,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 7. "CTEIF2,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 6. "CHTIF2,Channel x half transfer clear This bit" "0,1" bitfld.long 0x0 5. "CTCIF2,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 4. "CGIF2,Channel x global interrupt clear This" "0,1" bitfld.long 0x0 3. "CTEIF1,Channel x transfer error clear This bit" "0,1" bitfld.long 0x0 2. "CHTIF1,Channel x half transfer clear This bit" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x transfer complete clear This" "0,1" bitfld.long 0x0 0. "CGIF1,Channel x global interrupt clear This" "0,1" group.long 0x8++0xF line.long 0x0 "BDMA_CCR0,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR0,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR0,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR0,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x1C++0xF line.long 0x0 "BDMA_CCR1,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR1,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR1,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR1,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x30++0xF line.long 0x0 "BDMA_CCR2,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR2,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR2,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR2,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x44++0xF line.long 0x0 "BDMA_CCR3,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR3,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR3,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR3,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x58++0xF line.long 0x0 "BDMA_CCR4,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR4,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR4,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR4,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x6C++0xF line.long 0x0 "BDMA_CCR5,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR5,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR5,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR5,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x80++0xF line.long 0x0 "BDMA_CCR6,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR6,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR6,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR6,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x94++0xF line.long 0x0 "BDMA_CCR7,DMA channel x configuration" bitfld.long 0x0 14. "MEM2MEM,Memory to memory mode This bit is set" "0,1" bitfld.long 0x0 12.--13. "PL,Channel priority level These bits are" "0,1,2,3" bitfld.long 0x0 10.--11. "MSIZE,Memory size These bits are set and" "0,1,2,3" bitfld.long 0x0 8.--9. "PSIZE,Peripheral size These bits are set and" "0,1,2,3" bitfld.long 0x0 7. "MINC,Memory increment mode This bit is set" "0,1" bitfld.long 0x0 6. "PINC,Peripheral increment mode This bit is" "0,1" bitfld.long 0x0 5. "CIRC,Circular mode This bit is set and" "0,1" bitfld.long 0x0 4. "DIR,Data transfer direction This bit is set" "0,1" bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable This bit" "0,1" newline bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 0. "EN,Channel enable This bit is set and" "0,1" line.long 0x4 "BDMA_CNDTR7,DMA channel x number of data" hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer Number of" line.long 0x8 "BDMA_CPAR7,This register must not be written when the" hexmask.long 0x8 0.--31. 1. "PA,Peripheral address Base address of the" line.long 0xC "BDMA_CM0AR7,This register must not be written when the" hexmask.long 0xC 0.--31. 1. "MA,Memory address Base address of the" group.long 0x18++0x3 line.long 0x0 "BDMA_CM1AR0,This register must not be written when the" group.long 0x2C++0x3 line.long 0x0 "BDMA_CM1AR1,BDMA_CMAR1" group.long 0x40++0x3 line.long 0x0 "BDMA_CM1AR2,BDMA_CM1AR2" group.long 0x54++0x3 line.long 0x0 "BDMA_CM1AR3,BDMA_CMAR3" group.long 0x68++0x3 line.long 0x0 "BDMA_CM1AR4,BDMA_CM1AR4" group.long 0x7C++0x3 line.long 0x0 "BDMA_CM1AR5,This register must not be written when the" group.long 0x90++0x3 line.long 0x0 "BDMA_CM1AR6,This register must not be written when the" group.long 0xA4++0x3 line.long 0x0 "BDMA_CM1AR7,This register must not be written when the" tree.end endif tree.end tree "CEC (HDMI-CEC Controller)" base ad:0x40006C00 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H750*")) group.long 0x0++0x7 line.long 0x0 "CEC_CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CEC_CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "CEC_TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "CEC_RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "CEC_ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "CEC_IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H753*")) group.long 0x0++0x7 line.long 0x0 "CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x7 line.long 0x0 "CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6" wgroup.long 0x8++0x3 line.long 0x0 "TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x7 line.long 0x0 "CEC_CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CEC_CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "SFT,Signal Free Time SFT bits are set by" wgroup.long 0x8++0x3 line.long 0x0 "CEC_TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "CEC_RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "CEC_ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "CEC_IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x7 line.long 0x0 "CEC_CR,CEC control register" bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1" bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1" newline bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1" line.long 0x4 "CEC_CFGR,This register is used to configure the" bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1" hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration The OAR bits" newline bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1" bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1" newline bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1" bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1" newline bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1" bitfld.long 0x4 3. "RXTOL,Rx-Tolerance The RXTOL bit is set and" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "SFT,Signal Free Time SFT bits are set by" wgroup.long 0x8++0x3 line.long 0x0 "CEC_TXDR,CEC Tx data register" hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only" rgroup.long 0xC++0x3 line.long 0x0 "CEC_RXDR,CEC Rx Data Register" hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and" group.long 0x10++0x7 line.long 0x0 "CEC_ISR,CEC Interrupt and Status" bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1" bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1" newline bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1" bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1" newline bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1" bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1" newline bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1" bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1" newline bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1" bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1" newline bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1" bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1" newline bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1" line.long 0x4 "CEC_IER,CEC interrupt enable register" bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1" newline bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1" bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1" newline bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1" bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1" newline bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1" bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1" bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1" newline bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1" bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1" newline bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1" endif tree.end tree "COMP (Comparator)" base ad:0x58003800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) rgroup.long 0x0++0x3 line.long 0x0 "SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H750*")) rgroup.long 0x0++0x3 line.long 0x0 "COMP1_SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "COMP1_ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "COMP1_OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "COMP1_CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "COMP1_CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H753*")) rgroup.long 0x0++0x3 line.long 0x0 "SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H755??-CM4")) rgroup.long 0x0++0x3 line.long 0x0 "SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H755??-CM7")) rgroup.long 0x0++0x3 line.long 0x0 "SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H757??-CM4")) rgroup.long 0x0++0x3 line.long 0x0 "SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H757??-CM7")) rgroup.long 0x0++0x3 line.long 0x0 "SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x0++0x3 line.long 0x0 "SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x4 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" bitfld.long 0x8 16.--18. "INMSEL,COMP channel 1 inverting input selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H7B0*")) rgroup.long 0x0++0x3 line.long 0x0 "COMP1_SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "COMP1_ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "COMP1_OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "COMP1_CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" hexmask.long.byte 0x4 16.--19. 1. "INMSEL,COMP channel 1 inverting input selection" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "COMP1_CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" hexmask.long.byte 0x8 16.--19. 1. "INMSEL,COMP channel 1 inverting input selection" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif sif (cpuis("STM32H7B3*")) rgroup.long 0x0++0x3 line.long 0x0 "COMP1_SR,Comparator status register" bitfld.long 0x0 17. "C2IF,COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "C1IF,COMP channel 1 Interrupt" "0,1" newline bitfld.long 0x0 1. "C2VAL,COMP channel 2 output status" "0,1" bitfld.long 0x0 0. "C1VAL,COMP channel 1 output status" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "COMP1_ICFR,Comparator interrupt clear flag" bitfld.long 0x0 17. "CC2IF,Clear COMP channel 2 Interrupt" "0,1" bitfld.long 0x0 16. "CC1IF,Clear COMP channel 1 Interrupt" "0,1" group.long 0x8++0xB line.long 0x0 "COMP1_OR,Comparator option register" hexmask.long.tbyte 0x0 11.--31. 1. "OR,Option Register" hexmask.long.word 0x0 0.--10. 1. "AFOP,Selection of source for alternate" line.long 0x4 "COMP1_CFGR1,Comparator configuration register" bitfld.long 0x4 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x4 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x4 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" hexmask.long.byte 0x4 16.--19. 1. "INMSEL,COMP channel 1 inverting input selection" newline bitfld.long 0x4 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x4 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x4 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x4 3. "POLARITY,COMP channel 1 polarity selection" "0,1" newline bitfld.long 0x4 2. "SCALEN,Voltage scaler enable bit" "0,1" bitfld.long 0x4 1. "BRGEN,Scaler bridge enable" "0,1" newline bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1" line.long 0x8 "COMP1_CFGR2,Comparator configuration register" bitfld.long 0x8 31. "LOCK,Lock bit" "0,1" hexmask.long.byte 0x8 24.--27. 1. "BLANKING,COMP channel 1 blanking source selection" newline bitfld.long 0x8 20. "INPSEL,COMP channel 1 non-inverting input" "0,1" hexmask.long.byte 0x8 16.--19. 1. "INMSEL,COMP channel 1 inverting input selection" newline bitfld.long 0x8 12.--13. "PWRMODE,Power Mode of the COMP channel" "0,1,2,3" bitfld.long 0x8 8.--9. "HYST,COMP channel 1 hysteresis selection" "0,1,2,3" newline bitfld.long 0x8 6. "ITEN,COMP channel 1 interrupt" "0,1" bitfld.long 0x8 4. "WINMODE,Window comparator mode selection" "0,1" newline bitfld.long 0x8 3. "POLARITY,COMP channel 1 polarity selection" "0,1" bitfld.long 0x8 2. "SCALEN,Voltage scaler enable bit" "0,1" newline bitfld.long 0x8 1. "BRGEN,Scaler bridge enable" "0,1" bitfld.long 0x8 0. "EN,COMP channel 1 enable bit" "0,1" endif tree.end sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "CORDIC (CORDIC co-processor)" base ad:0x48024400 group.long 0x0++0x3 line.long 0x0 "CORDIC_CSR,CORDIC control/status register" rbitfld.long 0x0 31. "RRDY,Result ready flag" "0: No new result in output register,1: CORDIC_RDATA register contains new data." bitfld.long 0x0 22. "ARGSIZE,Width of input data" "0: 32-bit,1: 16-bit" newline bitfld.long 0x0 21. "RESSIZE,Width of output data" "0: 32-bit,1: 16-bit" bitfld.long 0x0 20. "NARGS,Number of arguments expected by the CORDIC_WDATA register" "0: Only one 32-bit write (or two 16-bit values if..,1: Two 32-bit values must be written to the.." newline bitfld.long 0x0 19. "NRES,Number of results in the CORDIC_RDATA register" "0: Only one 32-bit value (or two 16-bit values if..,1: Two 32-bit values are transferred to the.." bitfld.long 0x0 18. "DMAWEN,Enable DMA write channel" "0: Disabled. No DMA write requests are generated.,1: Enabled. Requests are generated on the DMA write.." newline bitfld.long 0x0 17. "DMAREN,Enable DMA read channel" "0: Disabled. No DMA read requests are generated.,1: Enabled. Requests are generated on the DMA read.." bitfld.long 0x0 16. "IEN,Enable interrupt." "0: Disabled. No interrupt requests are generated.,1: Enabled. An interrupt request is generated.." newline bitfld.long 0x0 8.--10. "SCALE,Scaling factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 4.--7. 1. "PRECISION,Precision required (number of iterations)" newline hexmask.long.byte 0x0 0.--3. 1. "FUNC,Function" wgroup.long 0x4++0x3 line.long 0x0 "CORDIC_WDATA,CORDIC argument register" hexmask.long 0x0 0.--31. 1. "ARG,Function input arguments" rgroup.long 0x8++0x3 line.long 0x0 "CORDIC_RDATA,CORDIC result register" hexmask.long 0x0 0.--31. 1. "RES,Function result" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) base ad:0x58024C00 elif (cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) base ad:0x40023000 endif tree "CRC (Cyclic Redundancy Check Calculation Unit)" group.long 0x0++0xB line.long 0x0 "DR,Data register" hexmask.long 0x0 0.--31. 1. "DR,Data Register" line.long 0x4 "IDR,Independent Data register" hexmask.long 0x4 0.--31. 1. "IDR,Independent Data register" line.long 0x8 "CR,Control register" bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1" bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3" bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 0. "RESET,RESET bit" "0,1" endif group.long 0x10++0x7 line.long 0x0 "INIT,Initial CRC value" hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC" line.long 0x4 "POL,CRC polynomial" hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial" tree.end tree "CRS (Clock Recovery System)" base ad:0x40008400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H750*")) group.long 0x0++0x7 line.long 0x0 "CRS_CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CRS_CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "CRS_ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "CRS_ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H753*")) group.long 0x0++0x7 line.long 0x0 "CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x7 line.long 0x0 "CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider These bits are set and" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x7 line.long 0x0 "CRS_CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CRS_CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline hexmask.long.byte 0x4 24.--27. 1. "SYNCDIV,SYNC divider These bits are set and" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "CRS_ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "CRS_ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x7 line.long 0x0 "CRS_CR,CRS control register" hexmask.long.byte 0x0 8.--13. 1. "TRIM,HSI48 oscillator smooth trimming These" rbitfld.long 0x0 7. "SWSYNC,Generate software SYNC event This bit is" "0,1" newline bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable This bit" "?,?" bitfld.long 0x0 5. "CEN,Frequency error counter enable This bit" "0,1" newline bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt" "0,1" bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error" "0,1" newline bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt" "0,1" bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt" "0,1" line.long 0x4 "CRS_CFGR,This register can be written only when the" bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection This bit is set" "0,1" bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection These bits" "0,1,2,3" newline hexmask.long.byte 0x4 24.--27. 1. "SYNCDIV,SYNC divider These bits are set and" hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit FELIM contains the" newline hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value RELOAD is the value" rgroup.long 0x8++0x3 line.long 0x0 "CRS_ISR,CRS interrupt and status" hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture FECAP is the" bitfld.long 0x0 15. "FEDIR,Frequency error direction FEDIR is the" "0,1" newline bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow This flag" "0,1" bitfld.long 0x0 9. "SYNCMISS,SYNC missed This flag is set by hardware" "0,1" newline bitfld.long 0x0 8. "SYNCERR,SYNC error This flag is set by hardware" "0,1" bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag This flag is set by" "0,1" newline bitfld.long 0x0 2. "ERRF,Error flag This flag is set by hardware" "0,1" bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag This flag is set by" "0,1" newline bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag This flag is set by" "0,1" group.long 0xC++0x3 line.long 0x0 "CRS_ICR,CRS interrupt flag clear" bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag Writing 1 to" "0,1" bitfld.long 0x0 2. "ERRC,Error clear flag Writing 1 to this bit" "0,1" newline bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag Writing 1 to" "0,1" bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag Writing 1 to" "0,1" endif tree.end sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "CRYP (Cryptographic Processor)" base ad:0x48021000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 19. "ALGOMODE3,ALGOMODE" "0,1" bitfld.long 0x0 16.--17. "GCM_CCMPH,GCM_CCMPH" "0,1,2,3" bitfld.long 0x0 15. "CRYPEN,Cryptographic processor" "0,1" bitfld.long 0x0 14. "FFLUSH,FIFO flush" "0,1" newline bitfld.long 0x0 8.--9. "KEYSIZE,Key size selection (AES mode" "0,1,2,3" bitfld.long 0x0 6.--7. "DATATYPE,Data type selection" "0,1,2,3" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 3.--5. "ALGOMODE0,Algorithm mode" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 3.--6. 1. "ALGOMODE0,Algorithm mode" newline endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 3.--6. 1. "ALGOMODE0,Algorithm mode" endif bitfld.long 0x0 2. "ALGODIR,Algorithm direction" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "SR,status register" bitfld.long 0x0 4. "BUSY,Busy bit" "0,1" bitfld.long 0x0 3. "OFFU,Output FIFO full" "0,1" bitfld.long 0x0 2. "OFNE,Output FIFO not empty" "0,1" bitfld.long 0x0 1. "IFNF,Input FIFO not full" "0,1" newline bitfld.long 0x0 0. "IFEM,Input FIFO empty" "0,1" group.long 0x8++0x3 line.long 0x0 "DIN,data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data input" rgroup.long 0xC++0x3 line.long 0x0 "DOUT,data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data output" group.long 0x10++0x7 line.long 0x0 "DMACR,DMA control register" bitfld.long 0x0 1. "DOEN,DMA output enable" "0,1" bitfld.long 0x0 0. "DIEN,DMA input enable" "0,1" line.long 0x4 "IMSCR,interrupt mask set/clear" bitfld.long 0x4 1. "OUTIM,Output FIFO service interrupt" "0,1" bitfld.long 0x4 0. "INIM,Input FIFO service interrupt" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "RISR,raw interrupt status register" bitfld.long 0x0 1. "OUTRIS,Output FIFO service raw interrupt" "0,1" bitfld.long 0x0 0. "INRIS,Input FIFO service raw interrupt" "0,1" line.long 0x4 "MISR,masked interrupt status" bitfld.long 0x4 1. "OUTMIS,Output FIFO service masked interrupt" "0,1" bitfld.long 0x4 0. "INMIS,Input FIFO service masked interrupt" "0,1" wgroup.long 0x20++0x1F line.long 0x0 "K0LR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 31. "k255,k255" "0,1" bitfld.long 0x0 30. "k254,k254" "0,1" bitfld.long 0x0 29. "k253,k253" "0,1" bitfld.long 0x0 28. "k252,k252" "0,1" newline bitfld.long 0x0 27. "k251,k251" "0,1" bitfld.long 0x0 26. "k250,k250" "0,1" bitfld.long 0x0 25. "k249,k249" "0,1" bitfld.long 0x0 24. "k248,k248" "0,1" newline bitfld.long 0x0 23. "k247,k247" "0,1" bitfld.long 0x0 22. "k246,k246" "0,1" bitfld.long 0x0 21. "k245,k245" "0,1" bitfld.long 0x0 20. "k244,k244" "0,1" newline bitfld.long 0x0 19. "k243,k243" "0,1" bitfld.long 0x0 18. "k242,k242" "0,1" bitfld.long 0x0 17. "k241,k241" "0,1" bitfld.long 0x0 16. "k240,k240" "0,1" newline bitfld.long 0x0 15. "k239,k239" "0,1" bitfld.long 0x0 14. "k238,k238" "0,1" bitfld.long 0x0 13. "k237,k237" "0,1" bitfld.long 0x0 12. "k236,k236" "0,1" newline bitfld.long 0x0 11. "k235,k235" "0,1" bitfld.long 0x0 10. "k234,k234" "0,1" bitfld.long 0x0 9. "k233,k233" "0,1" bitfld.long 0x0 8. "k232,k232" "0,1" newline bitfld.long 0x0 7. "k231,k231" "0,1" bitfld.long 0x0 6. "k230,k230" "0,1" bitfld.long 0x0 5. "k229,k229" "0,1" bitfld.long 0x0 4. "k228,k228" "0,1" newline bitfld.long 0x0 3. "k227,k227" "0,1" bitfld.long 0x0 2. "k226,k226" "0,1" bitfld.long 0x0 1. "k225,k225" "0,1" bitfld.long 0x0 0. "k224,k224" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 31. "b255,b255" "0,1" bitfld.long 0x0 30. "b254,b254" "0,1" bitfld.long 0x0 29. "b253,b253" "0,1" bitfld.long 0x0 28. "b252,b252" "0,1" newline bitfld.long 0x0 27. "b251,b251" "0,1" bitfld.long 0x0 26. "b250,b250" "0,1" bitfld.long 0x0 25. "b249,b249" "0,1" bitfld.long 0x0 24. "b248,b248" "0,1" newline bitfld.long 0x0 23. "b247,b247" "0,1" bitfld.long 0x0 22. "b246,b246" "0,1" bitfld.long 0x0 21. "b245,b245" "0,1" bitfld.long 0x0 20. "b244,b244" "0,1" newline bitfld.long 0x0 19. "b243,b243" "0,1" bitfld.long 0x0 18. "b242,b242" "0,1" bitfld.long 0x0 17. "b241,b241" "0,1" bitfld.long 0x0 16. "b240,b240" "0,1" newline bitfld.long 0x0 15. "b239,b239" "0,1" bitfld.long 0x0 14. "b238,b238" "0,1" bitfld.long 0x0 13. "b237,b237" "0,1" bitfld.long 0x0 12. "b236,b236" "0,1" newline bitfld.long 0x0 11. "b235,b235" "0,1" bitfld.long 0x0 10. "b234,b234" "0,1" bitfld.long 0x0 9. "b233,b233" "0,1" bitfld.long 0x0 8. "b232,b232" "0,1" newline bitfld.long 0x0 7. "b231,b231" "0,1" bitfld.long 0x0 6. "b230,b230" "0,1" bitfld.long 0x0 5. "b229,b229" "0,1" bitfld.long 0x0 4. "b228,b228" "0,1" newline bitfld.long 0x0 3. "b227,b227" "0,1" bitfld.long 0x0 2. "b226,b226" "0,1" bitfld.long 0x0 1. "b225,b225" "0,1" bitfld.long 0x0 0. "b224,b224" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 31. "K255,K255" "0,1" bitfld.long 0x0 30. "K254,K254" "0,1" bitfld.long 0x0 29. "K253,K253" "0,1" bitfld.long 0x0 28. "K252,K252" "0,1" newline bitfld.long 0x0 27. "K251,K251" "0,1" bitfld.long 0x0 26. "K250,K250" "0,1" bitfld.long 0x0 25. "K249,K249" "0,1" bitfld.long 0x0 24. "K248,K248" "0,1" newline bitfld.long 0x0 23. "K247,K247" "0,1" bitfld.long 0x0 22. "K246,K246" "0,1" bitfld.long 0x0 21. "K245,K245" "0,1" bitfld.long 0x0 20. "K244,K244" "0,1" newline bitfld.long 0x0 19. "K243,K243" "0,1" bitfld.long 0x0 18. "K242,K242" "0,1" bitfld.long 0x0 17. "K241,K241" "0,1" bitfld.long 0x0 16. "K240,K240" "0,1" newline bitfld.long 0x0 15. "K239,K239" "0,1" bitfld.long 0x0 14. "K238,K238" "0,1" bitfld.long 0x0 13. "K237,K237" "0,1" bitfld.long 0x0 12. "K236,K236" "0,1" newline bitfld.long 0x0 11. "K235,K235" "0,1" bitfld.long 0x0 10. "K234,K234" "0,1" bitfld.long 0x0 9. "K233,K233" "0,1" bitfld.long 0x0 8. "K232,K232" "0,1" newline bitfld.long 0x0 7. "K231,K231" "0,1" bitfld.long 0x0 6. "K230,K230" "0,1" bitfld.long 0x0 5. "K229,K229" "0,1" bitfld.long 0x0 4. "K228,K228" "0,1" newline bitfld.long 0x0 3. "K227,K227" "0,1" bitfld.long 0x0 2. "K226,K226" "0,1" bitfld.long 0x0 1. "K225,K225" "0,1" bitfld.long 0x0 0. "K224,K224" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 31. "b255,b255" "0,1" bitfld.long 0x0 30. "b254,b254" "0,1" bitfld.long 0x0 29. "b253,b253" "0,1" bitfld.long 0x0 28. "b252,b252" "0,1" newline bitfld.long 0x0 27. "b251,b251" "0,1" bitfld.long 0x0 26. "b250,b250" "0,1" bitfld.long 0x0 25. "b249,b249" "0,1" bitfld.long 0x0 24. "b248,b248" "0,1" newline bitfld.long 0x0 23. "b247,b247" "0,1" bitfld.long 0x0 22. "b246,b246" "0,1" bitfld.long 0x0 21. "b245,b245" "0,1" bitfld.long 0x0 20. "b244,b244" "0,1" newline bitfld.long 0x0 19. "b243,b243" "0,1" bitfld.long 0x0 18. "b242,b242" "0,1" bitfld.long 0x0 17. "b241,b241" "0,1" bitfld.long 0x0 16. "b240,b240" "0,1" newline bitfld.long 0x0 15. "b239,b239" "0,1" bitfld.long 0x0 14. "b238,b238" "0,1" bitfld.long 0x0 13. "b237,b237" "0,1" bitfld.long 0x0 12. "b236,b236" "0,1" newline bitfld.long 0x0 11. "b235,b235" "0,1" bitfld.long 0x0 10. "b234,b234" "0,1" bitfld.long 0x0 9. "b233,b233" "0,1" bitfld.long 0x0 8. "b232,b232" "0,1" newline bitfld.long 0x0 7. "b231,b231" "0,1" bitfld.long 0x0 6. "b230,b230" "0,1" bitfld.long 0x0 5. "b229,b229" "0,1" bitfld.long 0x0 4. "b228,b228" "0,1" newline bitfld.long 0x0 3. "b227,b227" "0,1" bitfld.long 0x0 2. "b226,b226" "0,1" bitfld.long 0x0 1. "b225,b225" "0,1" bitfld.long 0x0 0. "b224,b224" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 31. "b255,b255" "0,1" bitfld.long 0x0 30. "b254,b254" "0,1" bitfld.long 0x0 29. "b253,b253" "0,1" bitfld.long 0x0 28. "b252,b252" "0,1" newline bitfld.long 0x0 27. "b251,b251" "0,1" bitfld.long 0x0 26. "b250,b250" "0,1" bitfld.long 0x0 25. "b249,b249" "0,1" bitfld.long 0x0 24. "b248,b248" "0,1" newline bitfld.long 0x0 23. "b247,b247" "0,1" bitfld.long 0x0 22. "b246,b246" "0,1" bitfld.long 0x0 21. "b245,b245" "0,1" bitfld.long 0x0 20. "b244,b244" "0,1" newline bitfld.long 0x0 19. "b243,b243" "0,1" bitfld.long 0x0 18. "b242,b242" "0,1" bitfld.long 0x0 17. "b241,b241" "0,1" bitfld.long 0x0 16. "b240,b240" "0,1" newline bitfld.long 0x0 15. "b239,b239" "0,1" bitfld.long 0x0 14. "b238,b238" "0,1" bitfld.long 0x0 13. "b237,b237" "0,1" bitfld.long 0x0 12. "b236,b236" "0,1" newline bitfld.long 0x0 11. "b235,b235" "0,1" bitfld.long 0x0 10. "b234,b234" "0,1" bitfld.long 0x0 9. "b233,b233" "0,1" bitfld.long 0x0 8. "b232,b232" "0,1" newline bitfld.long 0x0 7. "b231,b231" "0,1" bitfld.long 0x0 6. "b230,b230" "0,1" bitfld.long 0x0 5. "b229,b229" "0,1" bitfld.long 0x0 4. "b228,b228" "0,1" newline bitfld.long 0x0 3. "b227,b227" "0,1" bitfld.long 0x0 2. "b226,b226" "0,1" bitfld.long 0x0 1. "b225,b225" "0,1" bitfld.long 0x0 0. "b224,b224" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 31. "b255,b255" "0,1" bitfld.long 0x0 30. "b254,b254" "0,1" bitfld.long 0x0 29. "b253,b253" "0,1" bitfld.long 0x0 28. "b252,b252" "0,1" newline bitfld.long 0x0 27. "b251,b251" "0,1" bitfld.long 0x0 26. "b250,b250" "0,1" bitfld.long 0x0 25. "b249,b249" "0,1" bitfld.long 0x0 24. "b248,b248" "0,1" newline bitfld.long 0x0 23. "b247,b247" "0,1" bitfld.long 0x0 22. "b246,b246" "0,1" bitfld.long 0x0 21. "b245,b245" "0,1" bitfld.long 0x0 20. "b244,b244" "0,1" newline bitfld.long 0x0 19. "b243,b243" "0,1" bitfld.long 0x0 18. "b242,b242" "0,1" bitfld.long 0x0 17. "b241,b241" "0,1" bitfld.long 0x0 16. "b240,b240" "0,1" newline bitfld.long 0x0 15. "b239,b239" "0,1" bitfld.long 0x0 14. "b238,b238" "0,1" bitfld.long 0x0 13. "b237,b237" "0,1" bitfld.long 0x0 12. "b236,b236" "0,1" newline bitfld.long 0x0 11. "b235,b235" "0,1" bitfld.long 0x0 10. "b234,b234" "0,1" bitfld.long 0x0 9. "b233,b233" "0,1" bitfld.long 0x0 8. "b232,b232" "0,1" newline bitfld.long 0x0 7. "b231,b231" "0,1" bitfld.long 0x0 6. "b230,b230" "0,1" bitfld.long 0x0 5. "b229,b229" "0,1" bitfld.long 0x0 4. "b228,b228" "0,1" newline bitfld.long 0x0 3. "b227,b227" "0,1" bitfld.long 0x0 2. "b226,b226" "0,1" bitfld.long 0x0 1. "b225,b225" "0,1" bitfld.long 0x0 0. "b224,b224" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 31. "b255,b255" "0,1" bitfld.long 0x0 30. "b254,b254" "0,1" bitfld.long 0x0 29. "b253,b253" "0,1" bitfld.long 0x0 28. "b252,b252" "0,1" newline bitfld.long 0x0 27. "b251,b251" "0,1" bitfld.long 0x0 26. "b250,b250" "0,1" bitfld.long 0x0 25. "b249,b249" "0,1" bitfld.long 0x0 24. "b248,b248" "0,1" newline bitfld.long 0x0 23. "b247,b247" "0,1" bitfld.long 0x0 22. "b246,b246" "0,1" bitfld.long 0x0 21. "b245,b245" "0,1" bitfld.long 0x0 20. "b244,b244" "0,1" newline bitfld.long 0x0 19. "b243,b243" "0,1" bitfld.long 0x0 18. "b242,b242" "0,1" bitfld.long 0x0 17. "b241,b241" "0,1" bitfld.long 0x0 16. "b240,b240" "0,1" newline bitfld.long 0x0 15. "b239,b239" "0,1" bitfld.long 0x0 14. "b238,b238" "0,1" bitfld.long 0x0 13. "b237,b237" "0,1" bitfld.long 0x0 12. "b236,b236" "0,1" newline bitfld.long 0x0 11. "b235,b235" "0,1" bitfld.long 0x0 10. "b234,b234" "0,1" bitfld.long 0x0 9. "b233,b233" "0,1" bitfld.long 0x0 8. "b232,b232" "0,1" newline bitfld.long 0x0 7. "b231,b231" "0,1" bitfld.long 0x0 6. "b230,b230" "0,1" bitfld.long 0x0 5. "b229,b229" "0,1" bitfld.long 0x0 4. "b228,b228" "0,1" newline bitfld.long 0x0 3. "b227,b227" "0,1" bitfld.long 0x0 2. "b226,b226" "0,1" bitfld.long 0x0 1. "b225,b225" "0,1" bitfld.long 0x0 0. "b224,b224" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 31. "b255,b255" "0,1" bitfld.long 0x0 30. "b254,b254" "0,1" bitfld.long 0x0 29. "b253,b253" "0,1" bitfld.long 0x0 28. "b252,b252" "0,1" newline bitfld.long 0x0 27. "b251,b251" "0,1" bitfld.long 0x0 26. "b250,b250" "0,1" bitfld.long 0x0 25. "b249,b249" "0,1" bitfld.long 0x0 24. "b248,b248" "0,1" newline bitfld.long 0x0 23. "b247,b247" "0,1" bitfld.long 0x0 22. "b246,b246" "0,1" bitfld.long 0x0 21. "b245,b245" "0,1" bitfld.long 0x0 20. "b244,b244" "0,1" newline bitfld.long 0x0 19. "b243,b243" "0,1" bitfld.long 0x0 18. "b242,b242" "0,1" bitfld.long 0x0 17. "b241,b241" "0,1" bitfld.long 0x0 16. "b240,b240" "0,1" newline bitfld.long 0x0 15. "b239,b239" "0,1" bitfld.long 0x0 14. "b238,b238" "0,1" bitfld.long 0x0 13. "b237,b237" "0,1" bitfld.long 0x0 12. "b236,b236" "0,1" newline bitfld.long 0x0 11. "b235,b235" "0,1" bitfld.long 0x0 10. "b234,b234" "0,1" bitfld.long 0x0 9. "b233,b233" "0,1" bitfld.long 0x0 8. "b232,b232" "0,1" newline bitfld.long 0x0 7. "b231,b231" "0,1" bitfld.long 0x0 6. "b230,b230" "0,1" bitfld.long 0x0 5. "b229,b229" "0,1" bitfld.long 0x0 4. "b228,b228" "0,1" newline bitfld.long 0x0 3. "b227,b227" "0,1" bitfld.long 0x0 2. "b226,b226" "0,1" bitfld.long 0x0 1. "b225,b225" "0,1" bitfld.long 0x0 0. "b224,b224" "0,1" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 31. "b255,b255" "0,1" bitfld.long 0x0 30. "b254,b254" "0,1" bitfld.long 0x0 29. "b253,b253" "0,1" bitfld.long 0x0 28. "b252,b252" "0,1" newline bitfld.long 0x0 27. "b251,b251" "0,1" bitfld.long 0x0 26. "b250,b250" "0,1" bitfld.long 0x0 25. "b249,b249" "0,1" bitfld.long 0x0 24. "b248,b248" "0,1" newline bitfld.long 0x0 23. "b247,b247" "0,1" bitfld.long 0x0 22. "b246,b246" "0,1" bitfld.long 0x0 21. "b245,b245" "0,1" bitfld.long 0x0 20. "b244,b244" "0,1" newline bitfld.long 0x0 19. "b243,b243" "0,1" bitfld.long 0x0 18. "b242,b242" "0,1" bitfld.long 0x0 17. "b241,b241" "0,1" bitfld.long 0x0 16. "b240,b240" "0,1" newline bitfld.long 0x0 15. "b239,b239" "0,1" bitfld.long 0x0 14. "b238,b238" "0,1" bitfld.long 0x0 13. "b237,b237" "0,1" bitfld.long 0x0 12. "b236,b236" "0,1" newline bitfld.long 0x0 11. "b235,b235" "0,1" bitfld.long 0x0 10. "b234,b234" "0,1" bitfld.long 0x0 9. "b233,b233" "0,1" bitfld.long 0x0 8. "b232,b232" "0,1" newline bitfld.long 0x0 7. "b231,b231" "0,1" bitfld.long 0x0 6. "b230,b230" "0,1" bitfld.long 0x0 5. "b229,b229" "0,1" bitfld.long 0x0 4. "b228,b228" "0,1" newline bitfld.long 0x0 3. "b227,b227" "0,1" bitfld.long 0x0 2. "b226,b226" "0,1" bitfld.long 0x0 1. "b225,b225" "0,1" bitfld.long 0x0 0. "b224,b224" "0,1" endif line.long 0x4 "K0RR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x4 31. "k223,k223" "0,1" bitfld.long 0x4 30. "k222,k222" "0,1" bitfld.long 0x4 29. "k221,k221" "0,1" bitfld.long 0x4 28. "k220,k220" "0,1" newline bitfld.long 0x4 27. "k219,k219" "0,1" bitfld.long 0x4 26. "k218,k218" "0,1" bitfld.long 0x4 25. "k217,k217" "0,1" bitfld.long 0x4 24. "k216,k216" "0,1" newline bitfld.long 0x4 23. "k215,k215" "0,1" bitfld.long 0x4 22. "k214,k214" "0,1" bitfld.long 0x4 21. "k213,k213" "0,1" bitfld.long 0x4 20. "k212,k212" "0,1" newline bitfld.long 0x4 19. "k211,k211" "0,1" bitfld.long 0x4 18. "k210,k210" "0,1" bitfld.long 0x4 17. "k209,k209" "0,1" bitfld.long 0x4 16. "k208,k208" "0,1" newline bitfld.long 0x4 15. "k207,k207" "0,1" bitfld.long 0x4 14. "k206,k206" "0,1" bitfld.long 0x4 13. "k205,k205" "0,1" bitfld.long 0x4 12. "k204,k204" "0,1" newline bitfld.long 0x4 11. "k203,k203" "0,1" bitfld.long 0x4 10. "k202,k202" "0,1" bitfld.long 0x4 9. "k201,k201" "0,1" bitfld.long 0x4 8. "k200,k200" "0,1" newline bitfld.long 0x4 7. "k199,k199" "0,1" bitfld.long 0x4 6. "k198,k198" "0,1" bitfld.long 0x4 5. "k197,k197" "0,1" bitfld.long 0x4 4. "k196,k196" "0,1" newline bitfld.long 0x4 3. "k195,k195" "0,1" bitfld.long 0x4 2. "k194,k194" "0,1" bitfld.long 0x4 1. "k193,k193" "0,1" bitfld.long 0x4 0. "k192,k192" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 31. "b223,b223" "0,1" bitfld.long 0x4 30. "b222,b222" "0,1" bitfld.long 0x4 29. "b221,b221" "0,1" bitfld.long 0x4 28. "b220,b220" "0,1" newline bitfld.long 0x4 27. "b219,b219" "0,1" bitfld.long 0x4 26. "b218,b218" "0,1" bitfld.long 0x4 25. "b217,b217" "0,1" bitfld.long 0x4 24. "b216,b216" "0,1" newline bitfld.long 0x4 23. "b215,b215" "0,1" bitfld.long 0x4 22. "b214,b214" "0,1" bitfld.long 0x4 21. "b213,b213" "0,1" bitfld.long 0x4 20. "b212,b212" "0,1" newline bitfld.long 0x4 19. "b211,b211" "0,1" bitfld.long 0x4 18. "b210,b210" "0,1" bitfld.long 0x4 17. "b209,b209" "0,1" bitfld.long 0x4 16. "b208,b208" "0,1" newline bitfld.long 0x4 15. "b207,b207" "0,1" bitfld.long 0x4 14. "b206,b206" "0,1" bitfld.long 0x4 13. "b205,b205" "0,1" bitfld.long 0x4 12. "b204,b204" "0,1" newline bitfld.long 0x4 11. "b203,b203" "0,1" bitfld.long 0x4 10. "b202,b202" "0,1" bitfld.long 0x4 9. "b201,b201" "0,1" bitfld.long 0x4 8. "b200,b200" "0,1" newline bitfld.long 0x4 7. "b199,b199" "0,1" bitfld.long 0x4 6. "b198,b198" "0,1" bitfld.long 0x4 5. "b197,b197" "0,1" bitfld.long 0x4 4. "b196,b196" "0,1" newline bitfld.long 0x4 3. "b195,b195" "0,1" bitfld.long 0x4 2. "b194,b194" "0,1" bitfld.long 0x4 1. "b193,b193" "0,1" bitfld.long 0x4 0. "b192,b192" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 31. "K223,K223" "0,1" bitfld.long 0x4 30. "K222,K222" "0,1" bitfld.long 0x4 29. "K221,K221" "0,1" bitfld.long 0x4 28. "K220,K220" "0,1" newline bitfld.long 0x4 27. "K219,K219" "0,1" bitfld.long 0x4 26. "K218,K218" "0,1" bitfld.long 0x4 25. "K217,K217" "0,1" bitfld.long 0x4 24. "K216,K216" "0,1" newline bitfld.long 0x4 23. "K215,K215" "0,1" bitfld.long 0x4 22. "K214,K214" "0,1" bitfld.long 0x4 21. "K213,K213" "0,1" bitfld.long 0x4 20. "K212,K212" "0,1" newline bitfld.long 0x4 19. "K211,K211" "0,1" bitfld.long 0x4 18. "K210,K210" "0,1" bitfld.long 0x4 17. "K209,K209" "0,1" bitfld.long 0x4 16. "K208,K208" "0,1" newline bitfld.long 0x4 15. "K207,K207" "0,1" bitfld.long 0x4 14. "K206,K206" "0,1" bitfld.long 0x4 13. "K205,K205" "0,1" bitfld.long 0x4 12. "K204,K204" "0,1" newline bitfld.long 0x4 11. "K203,K203" "0,1" bitfld.long 0x4 10. "K202,K202" "0,1" bitfld.long 0x4 9. "K201,K201" "0,1" bitfld.long 0x4 8. "K200,K200" "0,1" newline bitfld.long 0x4 7. "K199,K199" "0,1" bitfld.long 0x4 6. "K198,K198" "0,1" bitfld.long 0x4 5. "K197,K197" "0,1" bitfld.long 0x4 4. "K196,K196" "0,1" newline bitfld.long 0x4 3. "K195,K195" "0,1" bitfld.long 0x4 2. "K194,K194" "0,1" bitfld.long 0x4 1. "K193,K193" "0,1" bitfld.long 0x4 0. "K192,K192" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 31. "b223,b223" "0,1" bitfld.long 0x4 30. "b222,b222" "0,1" bitfld.long 0x4 29. "b221,b221" "0,1" bitfld.long 0x4 28. "b220,b220" "0,1" newline bitfld.long 0x4 27. "b219,b219" "0,1" bitfld.long 0x4 26. "b218,b218" "0,1" bitfld.long 0x4 25. "b217,b217" "0,1" bitfld.long 0x4 24. "b216,b216" "0,1" newline bitfld.long 0x4 23. "b215,b215" "0,1" bitfld.long 0x4 22. "b214,b214" "0,1" bitfld.long 0x4 21. "b213,b213" "0,1" bitfld.long 0x4 20. "b212,b212" "0,1" newline bitfld.long 0x4 19. "b211,b211" "0,1" bitfld.long 0x4 18. "b210,b210" "0,1" bitfld.long 0x4 17. "b209,b209" "0,1" bitfld.long 0x4 16. "b208,b208" "0,1" newline bitfld.long 0x4 15. "b207,b207" "0,1" bitfld.long 0x4 14. "b206,b206" "0,1" bitfld.long 0x4 13. "b205,b205" "0,1" bitfld.long 0x4 12. "b204,b204" "0,1" newline bitfld.long 0x4 11. "b203,b203" "0,1" bitfld.long 0x4 10. "b202,b202" "0,1" bitfld.long 0x4 9. "b201,b201" "0,1" bitfld.long 0x4 8. "b200,b200" "0,1" newline bitfld.long 0x4 7. "b199,b199" "0,1" bitfld.long 0x4 6. "b198,b198" "0,1" bitfld.long 0x4 5. "b197,b197" "0,1" bitfld.long 0x4 4. "b196,b196" "0,1" newline bitfld.long 0x4 3. "b195,b195" "0,1" bitfld.long 0x4 2. "b194,b194" "0,1" bitfld.long 0x4 1. "b193,b193" "0,1" bitfld.long 0x4 0. "b192,b192" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 31. "b223,b223" "0,1" bitfld.long 0x4 30. "b222,b222" "0,1" bitfld.long 0x4 29. "b221,b221" "0,1" bitfld.long 0x4 28. "b220,b220" "0,1" newline bitfld.long 0x4 27. "b219,b219" "0,1" bitfld.long 0x4 26. "b218,b218" "0,1" bitfld.long 0x4 25. "b217,b217" "0,1" bitfld.long 0x4 24. "b216,b216" "0,1" newline bitfld.long 0x4 23. "b215,b215" "0,1" bitfld.long 0x4 22. "b214,b214" "0,1" bitfld.long 0x4 21. "b213,b213" "0,1" bitfld.long 0x4 20. "b212,b212" "0,1" newline bitfld.long 0x4 19. "b211,b211" "0,1" bitfld.long 0x4 18. "b210,b210" "0,1" bitfld.long 0x4 17. "b209,b209" "0,1" bitfld.long 0x4 16. "b208,b208" "0,1" newline bitfld.long 0x4 15. "b207,b207" "0,1" bitfld.long 0x4 14. "b206,b206" "0,1" bitfld.long 0x4 13. "b205,b205" "0,1" bitfld.long 0x4 12. "b204,b204" "0,1" newline bitfld.long 0x4 11. "b203,b203" "0,1" bitfld.long 0x4 10. "b202,b202" "0,1" bitfld.long 0x4 9. "b201,b201" "0,1" bitfld.long 0x4 8. "b200,b200" "0,1" newline bitfld.long 0x4 7. "b199,b199" "0,1" bitfld.long 0x4 6. "b198,b198" "0,1" bitfld.long 0x4 5. "b197,b197" "0,1" bitfld.long 0x4 4. "b196,b196" "0,1" newline bitfld.long 0x4 3. "b195,b195" "0,1" bitfld.long 0x4 2. "b194,b194" "0,1" bitfld.long 0x4 1. "b193,b193" "0,1" bitfld.long 0x4 0. "b192,b192" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 31. "b223,b223" "0,1" bitfld.long 0x4 30. "b222,b222" "0,1" bitfld.long 0x4 29. "b221,b221" "0,1" bitfld.long 0x4 28. "b220,b220" "0,1" newline bitfld.long 0x4 27. "b219,b219" "0,1" bitfld.long 0x4 26. "b218,b218" "0,1" bitfld.long 0x4 25. "b217,b217" "0,1" bitfld.long 0x4 24. "b216,b216" "0,1" newline bitfld.long 0x4 23. "b215,b215" "0,1" bitfld.long 0x4 22. "b214,b214" "0,1" bitfld.long 0x4 21. "b213,b213" "0,1" bitfld.long 0x4 20. "b212,b212" "0,1" newline bitfld.long 0x4 19. "b211,b211" "0,1" bitfld.long 0x4 18. "b210,b210" "0,1" bitfld.long 0x4 17. "b209,b209" "0,1" bitfld.long 0x4 16. "b208,b208" "0,1" newline bitfld.long 0x4 15. "b207,b207" "0,1" bitfld.long 0x4 14. "b206,b206" "0,1" bitfld.long 0x4 13. "b205,b205" "0,1" bitfld.long 0x4 12. "b204,b204" "0,1" newline bitfld.long 0x4 11. "b203,b203" "0,1" bitfld.long 0x4 10. "b202,b202" "0,1" bitfld.long 0x4 9. "b201,b201" "0,1" bitfld.long 0x4 8. "b200,b200" "0,1" newline bitfld.long 0x4 7. "b199,b199" "0,1" bitfld.long 0x4 6. "b198,b198" "0,1" bitfld.long 0x4 5. "b197,b197" "0,1" bitfld.long 0x4 4. "b196,b196" "0,1" newline bitfld.long 0x4 3. "b195,b195" "0,1" bitfld.long 0x4 2. "b194,b194" "0,1" bitfld.long 0x4 1. "b193,b193" "0,1" bitfld.long 0x4 0. "b192,b192" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 31. "b223,b223" "0,1" bitfld.long 0x4 30. "b222,b222" "0,1" bitfld.long 0x4 29. "b221,b221" "0,1" bitfld.long 0x4 28. "b220,b220" "0,1" newline bitfld.long 0x4 27. "b219,b219" "0,1" bitfld.long 0x4 26. "b218,b218" "0,1" bitfld.long 0x4 25. "b217,b217" "0,1" bitfld.long 0x4 24. "b216,b216" "0,1" newline bitfld.long 0x4 23. "b215,b215" "0,1" bitfld.long 0x4 22. "b214,b214" "0,1" bitfld.long 0x4 21. "b213,b213" "0,1" bitfld.long 0x4 20. "b212,b212" "0,1" newline bitfld.long 0x4 19. "b211,b211" "0,1" bitfld.long 0x4 18. "b210,b210" "0,1" bitfld.long 0x4 17. "b209,b209" "0,1" bitfld.long 0x4 16. "b208,b208" "0,1" newline bitfld.long 0x4 15. "b207,b207" "0,1" bitfld.long 0x4 14. "b206,b206" "0,1" bitfld.long 0x4 13. "b205,b205" "0,1" bitfld.long 0x4 12. "b204,b204" "0,1" newline bitfld.long 0x4 11. "b203,b203" "0,1" bitfld.long 0x4 10. "b202,b202" "0,1" bitfld.long 0x4 9. "b201,b201" "0,1" bitfld.long 0x4 8. "b200,b200" "0,1" newline bitfld.long 0x4 7. "b199,b199" "0,1" bitfld.long 0x4 6. "b198,b198" "0,1" bitfld.long 0x4 5. "b197,b197" "0,1" bitfld.long 0x4 4. "b196,b196" "0,1" newline bitfld.long 0x4 3. "b195,b195" "0,1" bitfld.long 0x4 2. "b194,b194" "0,1" bitfld.long 0x4 1. "b193,b193" "0,1" bitfld.long 0x4 0. "b192,b192" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x4 31. "b223,b223" "0,1" bitfld.long 0x4 30. "b222,b222" "0,1" bitfld.long 0x4 29. "b221,b221" "0,1" bitfld.long 0x4 28. "b220,b220" "0,1" newline bitfld.long 0x4 27. "b219,b219" "0,1" bitfld.long 0x4 26. "b218,b218" "0,1" bitfld.long 0x4 25. "b217,b217" "0,1" bitfld.long 0x4 24. "b216,b216" "0,1" newline bitfld.long 0x4 23. "b215,b215" "0,1" bitfld.long 0x4 22. "b214,b214" "0,1" bitfld.long 0x4 21. "b213,b213" "0,1" bitfld.long 0x4 20. "b212,b212" "0,1" newline bitfld.long 0x4 19. "b211,b211" "0,1" bitfld.long 0x4 18. "b210,b210" "0,1" bitfld.long 0x4 17. "b209,b209" "0,1" bitfld.long 0x4 16. "b208,b208" "0,1" newline bitfld.long 0x4 15. "b207,b207" "0,1" bitfld.long 0x4 14. "b206,b206" "0,1" bitfld.long 0x4 13. "b205,b205" "0,1" bitfld.long 0x4 12. "b204,b204" "0,1" newline bitfld.long 0x4 11. "b203,b203" "0,1" bitfld.long 0x4 10. "b202,b202" "0,1" bitfld.long 0x4 9. "b201,b201" "0,1" bitfld.long 0x4 8. "b200,b200" "0,1" newline bitfld.long 0x4 7. "b199,b199" "0,1" bitfld.long 0x4 6. "b198,b198" "0,1" bitfld.long 0x4 5. "b197,b197" "0,1" bitfld.long 0x4 4. "b196,b196" "0,1" newline bitfld.long 0x4 3. "b195,b195" "0,1" bitfld.long 0x4 2. "b194,b194" "0,1" bitfld.long 0x4 1. "b193,b193" "0,1" bitfld.long 0x4 0. "b192,b192" "0,1" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0x4 31. "b223,b223" "0,1" bitfld.long 0x4 30. "b222,b222" "0,1" bitfld.long 0x4 29. "b221,b221" "0,1" bitfld.long 0x4 28. "b220,b220" "0,1" newline bitfld.long 0x4 27. "b219,b219" "0,1" bitfld.long 0x4 26. "b218,b218" "0,1" bitfld.long 0x4 25. "b217,b217" "0,1" bitfld.long 0x4 24. "b216,b216" "0,1" newline bitfld.long 0x4 23. "b215,b215" "0,1" bitfld.long 0x4 22. "b214,b214" "0,1" bitfld.long 0x4 21. "b213,b213" "0,1" bitfld.long 0x4 20. "b212,b212" "0,1" newline bitfld.long 0x4 19. "b211,b211" "0,1" bitfld.long 0x4 18. "b210,b210" "0,1" bitfld.long 0x4 17. "b209,b209" "0,1" bitfld.long 0x4 16. "b208,b208" "0,1" newline bitfld.long 0x4 15. "b207,b207" "0,1" bitfld.long 0x4 14. "b206,b206" "0,1" bitfld.long 0x4 13. "b205,b205" "0,1" bitfld.long 0x4 12. "b204,b204" "0,1" newline bitfld.long 0x4 11. "b203,b203" "0,1" bitfld.long 0x4 10. "b202,b202" "0,1" bitfld.long 0x4 9. "b201,b201" "0,1" bitfld.long 0x4 8. "b200,b200" "0,1" newline bitfld.long 0x4 7. "b199,b199" "0,1" bitfld.long 0x4 6. "b198,b198" "0,1" bitfld.long 0x4 5. "b197,b197" "0,1" bitfld.long 0x4 4. "b196,b196" "0,1" newline bitfld.long 0x4 3. "b195,b195" "0,1" bitfld.long 0x4 2. "b194,b194" "0,1" bitfld.long 0x4 1. "b193,b193" "0,1" bitfld.long 0x4 0. "b192,b192" "0,1" endif line.long 0x8 "K1LR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 31. "k191,k191" "0,1" bitfld.long 0x8 30. "k190,k190" "0,1" bitfld.long 0x8 29. "k189,k189" "0,1" bitfld.long 0x8 28. "k188,k188" "0,1" newline bitfld.long 0x8 27. "k187,k187" "0,1" bitfld.long 0x8 26. "k186,k186" "0,1" bitfld.long 0x8 25. "k185,k185" "0,1" bitfld.long 0x8 24. "k184,k184" "0,1" newline bitfld.long 0x8 23. "k183,k183" "0,1" bitfld.long 0x8 22. "k182,k182" "0,1" bitfld.long 0x8 21. "k181,k181" "0,1" bitfld.long 0x8 20. "k180,k180" "0,1" newline bitfld.long 0x8 19. "k179,k179" "0,1" bitfld.long 0x8 18. "k178,k178" "0,1" bitfld.long 0x8 17. "k177,k177" "0,1" bitfld.long 0x8 16. "k176,k176" "0,1" newline bitfld.long 0x8 15. "k175,k175" "0,1" bitfld.long 0x8 14. "k174,k174" "0,1" bitfld.long 0x8 13. "k173,k173" "0,1" bitfld.long 0x8 12. "k172,k172" "0,1" newline bitfld.long 0x8 11. "k171,k171" "0,1" bitfld.long 0x8 10. "k170,k170" "0,1" bitfld.long 0x8 9. "k169,k169" "0,1" bitfld.long 0x8 8. "k168,k168" "0,1" newline bitfld.long 0x8 7. "k167,k167" "0,1" bitfld.long 0x8 6. "k166,k166" "0,1" bitfld.long 0x8 5. "k165,k165" "0,1" bitfld.long 0x8 4. "k164,k164" "0,1" newline bitfld.long 0x8 3. "k163,k163" "0,1" bitfld.long 0x8 2. "k162,k162" "0,1" bitfld.long 0x8 1. "k161,k161" "0,1" bitfld.long 0x8 0. "k160,k160" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x8 31. "b191,b191" "0,1" bitfld.long 0x8 30. "b190,b190" "0,1" bitfld.long 0x8 29. "b189,b189" "0,1" bitfld.long 0x8 28. "b188,b188" "0,1" newline bitfld.long 0x8 27. "b187,b187" "0,1" bitfld.long 0x8 26. "b186,b186" "0,1" bitfld.long 0x8 25. "b185,b185" "0,1" bitfld.long 0x8 24. "b184,b184" "0,1" newline bitfld.long 0x8 23. "b183,b183" "0,1" bitfld.long 0x8 22. "b182,b182" "0,1" bitfld.long 0x8 21. "b181,b181" "0,1" bitfld.long 0x8 20. "b180,b180" "0,1" newline bitfld.long 0x8 19. "b179,b179" "0,1" bitfld.long 0x8 18. "b178,b178" "0,1" bitfld.long 0x8 17. "b177,b177" "0,1" bitfld.long 0x8 16. "b176,b176" "0,1" newline bitfld.long 0x8 15. "b175,b175" "0,1" bitfld.long 0x8 14. "b174,b174" "0,1" bitfld.long 0x8 13. "b173,b173" "0,1" bitfld.long 0x8 12. "b172,b172" "0,1" newline bitfld.long 0x8 11. "b171,b171" "0,1" bitfld.long 0x8 10. "b170,b170" "0,1" bitfld.long 0x8 9. "b169,b169" "0,1" bitfld.long 0x8 8. "b168,b168" "0,1" newline bitfld.long 0x8 7. "b167,b167" "0,1" bitfld.long 0x8 6. "b166,b166" "0,1" bitfld.long 0x8 5. "b165,b165" "0,1" bitfld.long 0x8 4. "b164,b164" "0,1" newline bitfld.long 0x8 3. "b163,b163" "0,1" bitfld.long 0x8 2. "b162,b162" "0,1" bitfld.long 0x8 1. "b161,b161" "0,1" bitfld.long 0x8 0. "b160,b160" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 31. "K191,K191" "0,1" bitfld.long 0x8 30. "K190,K190" "0,1" bitfld.long 0x8 29. "K189,K189" "0,1" bitfld.long 0x8 28. "K188,K188" "0,1" newline bitfld.long 0x8 27. "K187,K187" "0,1" bitfld.long 0x8 26. "K186,K186" "0,1" bitfld.long 0x8 25. "K185,K185" "0,1" bitfld.long 0x8 24. "K184,K184" "0,1" newline bitfld.long 0x8 23. "K183,K183" "0,1" bitfld.long 0x8 22. "K182,K182" "0,1" bitfld.long 0x8 21. "K181,K181" "0,1" bitfld.long 0x8 20. "K180,K180" "0,1" newline bitfld.long 0x8 19. "K179,K179" "0,1" bitfld.long 0x8 18. "K178,K178" "0,1" bitfld.long 0x8 17. "K177,K177" "0,1" bitfld.long 0x8 16. "K176,K176" "0,1" newline bitfld.long 0x8 15. "K175,K175" "0,1" bitfld.long 0x8 14. "K174,K174" "0,1" bitfld.long 0x8 13. "K173,K173" "0,1" bitfld.long 0x8 12. "K172,K172" "0,1" newline bitfld.long 0x8 11. "K171,K171" "0,1" bitfld.long 0x8 10. "K170,K170" "0,1" bitfld.long 0x8 9. "K169,K169" "0,1" bitfld.long 0x8 8. "K168,K168" "0,1" newline bitfld.long 0x8 7. "K167,K167" "0,1" bitfld.long 0x8 6. "K166,K166" "0,1" bitfld.long 0x8 5. "K165,K165" "0,1" bitfld.long 0x8 4. "K164,K164" "0,1" newline bitfld.long 0x8 3. "K163,K163" "0,1" bitfld.long 0x8 2. "K162,K162" "0,1" bitfld.long 0x8 1. "K161,K161" "0,1" bitfld.long 0x8 0. "K160,K160" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 31. "b191,b191" "0,1" bitfld.long 0x8 30. "b190,b190" "0,1" bitfld.long 0x8 29. "b189,b189" "0,1" bitfld.long 0x8 28. "b188,b188" "0,1" newline bitfld.long 0x8 27. "b187,b187" "0,1" bitfld.long 0x8 26. "b186,b186" "0,1" bitfld.long 0x8 25. "b185,b185" "0,1" bitfld.long 0x8 24. "b184,b184" "0,1" newline bitfld.long 0x8 23. "b183,b183" "0,1" bitfld.long 0x8 22. "b182,b182" "0,1" bitfld.long 0x8 21. "b181,b181" "0,1" bitfld.long 0x8 20. "b180,b180" "0,1" newline bitfld.long 0x8 19. "b179,b179" "0,1" bitfld.long 0x8 18. "b178,b178" "0,1" bitfld.long 0x8 17. "b177,b177" "0,1" bitfld.long 0x8 16. "b176,b176" "0,1" newline bitfld.long 0x8 15. "b175,b175" "0,1" bitfld.long 0x8 14. "b174,b174" "0,1" bitfld.long 0x8 13. "b173,b173" "0,1" bitfld.long 0x8 12. "b172,b172" "0,1" newline bitfld.long 0x8 11. "b171,b171" "0,1" bitfld.long 0x8 10. "b170,b170" "0,1" bitfld.long 0x8 9. "b169,b169" "0,1" bitfld.long 0x8 8. "b168,b168" "0,1" newline bitfld.long 0x8 7. "b167,b167" "0,1" bitfld.long 0x8 6. "b166,b166" "0,1" bitfld.long 0x8 5. "b165,b165" "0,1" bitfld.long 0x8 4. "b164,b164" "0,1" newline bitfld.long 0x8 3. "b163,b163" "0,1" bitfld.long 0x8 2. "b162,b162" "0,1" bitfld.long 0x8 1. "b161,b161" "0,1" bitfld.long 0x8 0. "b160,b160" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 31. "b191,b191" "0,1" bitfld.long 0x8 30. "b190,b190" "0,1" bitfld.long 0x8 29. "b189,b189" "0,1" bitfld.long 0x8 28. "b188,b188" "0,1" newline bitfld.long 0x8 27. "b187,b187" "0,1" bitfld.long 0x8 26. "b186,b186" "0,1" bitfld.long 0x8 25. "b185,b185" "0,1" bitfld.long 0x8 24. "b184,b184" "0,1" newline bitfld.long 0x8 23. "b183,b183" "0,1" bitfld.long 0x8 22. "b182,b182" "0,1" bitfld.long 0x8 21. "b181,b181" "0,1" bitfld.long 0x8 20. "b180,b180" "0,1" newline bitfld.long 0x8 19. "b179,b179" "0,1" bitfld.long 0x8 18. "b178,b178" "0,1" bitfld.long 0x8 17. "b177,b177" "0,1" bitfld.long 0x8 16. "b176,b176" "0,1" newline bitfld.long 0x8 15. "b175,b175" "0,1" bitfld.long 0x8 14. "b174,b174" "0,1" bitfld.long 0x8 13. "b173,b173" "0,1" bitfld.long 0x8 12. "b172,b172" "0,1" newline bitfld.long 0x8 11. "b171,b171" "0,1" bitfld.long 0x8 10. "b170,b170" "0,1" bitfld.long 0x8 9. "b169,b169" "0,1" bitfld.long 0x8 8. "b168,b168" "0,1" newline bitfld.long 0x8 7. "b167,b167" "0,1" bitfld.long 0x8 6. "b166,b166" "0,1" bitfld.long 0x8 5. "b165,b165" "0,1" bitfld.long 0x8 4. "b164,b164" "0,1" newline bitfld.long 0x8 3. "b163,b163" "0,1" bitfld.long 0x8 2. "b162,b162" "0,1" bitfld.long 0x8 1. "b161,b161" "0,1" bitfld.long 0x8 0. "b160,b160" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 31. "b191,b191" "0,1" bitfld.long 0x8 30. "b190,b190" "0,1" bitfld.long 0x8 29. "b189,b189" "0,1" bitfld.long 0x8 28. "b188,b188" "0,1" newline bitfld.long 0x8 27. "b187,b187" "0,1" bitfld.long 0x8 26. "b186,b186" "0,1" bitfld.long 0x8 25. "b185,b185" "0,1" bitfld.long 0x8 24. "b184,b184" "0,1" newline bitfld.long 0x8 23. "b183,b183" "0,1" bitfld.long 0x8 22. "b182,b182" "0,1" bitfld.long 0x8 21. "b181,b181" "0,1" bitfld.long 0x8 20. "b180,b180" "0,1" newline bitfld.long 0x8 19. "b179,b179" "0,1" bitfld.long 0x8 18. "b178,b178" "0,1" bitfld.long 0x8 17. "b177,b177" "0,1" bitfld.long 0x8 16. "b176,b176" "0,1" newline bitfld.long 0x8 15. "b175,b175" "0,1" bitfld.long 0x8 14. "b174,b174" "0,1" bitfld.long 0x8 13. "b173,b173" "0,1" bitfld.long 0x8 12. "b172,b172" "0,1" newline bitfld.long 0x8 11. "b171,b171" "0,1" bitfld.long 0x8 10. "b170,b170" "0,1" bitfld.long 0x8 9. "b169,b169" "0,1" bitfld.long 0x8 8. "b168,b168" "0,1" newline bitfld.long 0x8 7. "b167,b167" "0,1" bitfld.long 0x8 6. "b166,b166" "0,1" bitfld.long 0x8 5. "b165,b165" "0,1" bitfld.long 0x8 4. "b164,b164" "0,1" newline bitfld.long 0x8 3. "b163,b163" "0,1" bitfld.long 0x8 2. "b162,b162" "0,1" bitfld.long 0x8 1. "b161,b161" "0,1" bitfld.long 0x8 0. "b160,b160" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 31. "b191,b191" "0,1" bitfld.long 0x8 30. "b190,b190" "0,1" bitfld.long 0x8 29. "b189,b189" "0,1" bitfld.long 0x8 28. "b188,b188" "0,1" newline bitfld.long 0x8 27. "b187,b187" "0,1" bitfld.long 0x8 26. "b186,b186" "0,1" bitfld.long 0x8 25. "b185,b185" "0,1" bitfld.long 0x8 24. "b184,b184" "0,1" newline bitfld.long 0x8 23. "b183,b183" "0,1" bitfld.long 0x8 22. "b182,b182" "0,1" bitfld.long 0x8 21. "b181,b181" "0,1" bitfld.long 0x8 20. "b180,b180" "0,1" newline bitfld.long 0x8 19. "b179,b179" "0,1" bitfld.long 0x8 18. "b178,b178" "0,1" bitfld.long 0x8 17. "b177,b177" "0,1" bitfld.long 0x8 16. "b176,b176" "0,1" newline bitfld.long 0x8 15. "b175,b175" "0,1" bitfld.long 0x8 14. "b174,b174" "0,1" bitfld.long 0x8 13. "b173,b173" "0,1" bitfld.long 0x8 12. "b172,b172" "0,1" newline bitfld.long 0x8 11. "b171,b171" "0,1" bitfld.long 0x8 10. "b170,b170" "0,1" bitfld.long 0x8 9. "b169,b169" "0,1" bitfld.long 0x8 8. "b168,b168" "0,1" newline bitfld.long 0x8 7. "b167,b167" "0,1" bitfld.long 0x8 6. "b166,b166" "0,1" bitfld.long 0x8 5. "b165,b165" "0,1" bitfld.long 0x8 4. "b164,b164" "0,1" newline bitfld.long 0x8 3. "b163,b163" "0,1" bitfld.long 0x8 2. "b162,b162" "0,1" bitfld.long 0x8 1. "b161,b161" "0,1" bitfld.long 0x8 0. "b160,b160" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x8 31. "b191,b191" "0,1" bitfld.long 0x8 30. "b190,b190" "0,1" bitfld.long 0x8 29. "b189,b189" "0,1" bitfld.long 0x8 28. "b188,b188" "0,1" newline bitfld.long 0x8 27. "b187,b187" "0,1" bitfld.long 0x8 26. "b186,b186" "0,1" bitfld.long 0x8 25. "b185,b185" "0,1" bitfld.long 0x8 24. "b184,b184" "0,1" newline bitfld.long 0x8 23. "b183,b183" "0,1" bitfld.long 0x8 22. "b182,b182" "0,1" bitfld.long 0x8 21. "b181,b181" "0,1" bitfld.long 0x8 20. "b180,b180" "0,1" newline bitfld.long 0x8 19. "b179,b179" "0,1" bitfld.long 0x8 18. "b178,b178" "0,1" bitfld.long 0x8 17. "b177,b177" "0,1" bitfld.long 0x8 16. "b176,b176" "0,1" newline bitfld.long 0x8 15. "b175,b175" "0,1" bitfld.long 0x8 14. "b174,b174" "0,1" bitfld.long 0x8 13. "b173,b173" "0,1" bitfld.long 0x8 12. "b172,b172" "0,1" newline bitfld.long 0x8 11. "b171,b171" "0,1" bitfld.long 0x8 10. "b170,b170" "0,1" bitfld.long 0x8 9. "b169,b169" "0,1" bitfld.long 0x8 8. "b168,b168" "0,1" newline bitfld.long 0x8 7. "b167,b167" "0,1" bitfld.long 0x8 6. "b166,b166" "0,1" bitfld.long 0x8 5. "b165,b165" "0,1" bitfld.long 0x8 4. "b164,b164" "0,1" newline bitfld.long 0x8 3. "b163,b163" "0,1" bitfld.long 0x8 2. "b162,b162" "0,1" bitfld.long 0x8 1. "b161,b161" "0,1" bitfld.long 0x8 0. "b160,b160" "0,1" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0x8 31. "b191,b191" "0,1" bitfld.long 0x8 30. "b190,b190" "0,1" bitfld.long 0x8 29. "b189,b189" "0,1" bitfld.long 0x8 28. "b188,b188" "0,1" newline bitfld.long 0x8 27. "b187,b187" "0,1" bitfld.long 0x8 26. "b186,b186" "0,1" bitfld.long 0x8 25. "b185,b185" "0,1" bitfld.long 0x8 24. "b184,b184" "0,1" newline bitfld.long 0x8 23. "b183,b183" "0,1" bitfld.long 0x8 22. "b182,b182" "0,1" bitfld.long 0x8 21. "b181,b181" "0,1" bitfld.long 0x8 20. "b180,b180" "0,1" newline bitfld.long 0x8 19. "b179,b179" "0,1" bitfld.long 0x8 18. "b178,b178" "0,1" bitfld.long 0x8 17. "b177,b177" "0,1" bitfld.long 0x8 16. "b176,b176" "0,1" newline bitfld.long 0x8 15. "b175,b175" "0,1" bitfld.long 0x8 14. "b174,b174" "0,1" bitfld.long 0x8 13. "b173,b173" "0,1" bitfld.long 0x8 12. "b172,b172" "0,1" newline bitfld.long 0x8 11. "b171,b171" "0,1" bitfld.long 0x8 10. "b170,b170" "0,1" bitfld.long 0x8 9. "b169,b169" "0,1" bitfld.long 0x8 8. "b168,b168" "0,1" newline bitfld.long 0x8 7. "b167,b167" "0,1" bitfld.long 0x8 6. "b166,b166" "0,1" bitfld.long 0x8 5. "b165,b165" "0,1" bitfld.long 0x8 4. "b164,b164" "0,1" newline bitfld.long 0x8 3. "b163,b163" "0,1" bitfld.long 0x8 2. "b162,b162" "0,1" bitfld.long 0x8 1. "b161,b161" "0,1" bitfld.long 0x8 0. "b160,b160" "0,1" endif line.long 0xC "K1RR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0xC 31. "k159,k159" "0,1" bitfld.long 0xC 30. "k158,k158" "0,1" bitfld.long 0xC 29. "k157,k157" "0,1" bitfld.long 0xC 28. "k156,k156" "0,1" newline bitfld.long 0xC 27. "k155,k155" "0,1" bitfld.long 0xC 26. "k154,k154" "0,1" bitfld.long 0xC 25. "k153,k153" "0,1" bitfld.long 0xC 24. "k152,k152" "0,1" newline bitfld.long 0xC 23. "k151,k151" "0,1" bitfld.long 0xC 22. "k150,k150" "0,1" bitfld.long 0xC 21. "k149,k149" "0,1" bitfld.long 0xC 20. "k148,k148" "0,1" newline bitfld.long 0xC 19. "k147,k147" "0,1" bitfld.long 0xC 18. "k146,k146" "0,1" bitfld.long 0xC 17. "k145,k145" "0,1" bitfld.long 0xC 16. "k144,k144" "0,1" newline bitfld.long 0xC 15. "k143,k143" "0,1" bitfld.long 0xC 14. "k142,k142" "0,1" bitfld.long 0xC 13. "k141,k141" "0,1" bitfld.long 0xC 12. "k140,k140" "0,1" newline bitfld.long 0xC 11. "k139,k139" "0,1" bitfld.long 0xC 10. "k138,k138" "0,1" bitfld.long 0xC 9. "k137,k137" "0,1" bitfld.long 0xC 8. "k136,k136" "0,1" newline bitfld.long 0xC 7. "k135,k135" "0,1" bitfld.long 0xC 6. "k134,k134" "0,1" bitfld.long 0xC 5. "k133,k133" "0,1" bitfld.long 0xC 4. "k132,k132" "0,1" newline bitfld.long 0xC 3. "k131,k131" "0,1" bitfld.long 0xC 2. "k130,k130" "0,1" bitfld.long 0xC 1. "k129,k129" "0,1" bitfld.long 0xC 0. "k128,k128" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 31. "b159,b159" "0,1" bitfld.long 0xC 30. "b158,b158" "0,1" bitfld.long 0xC 29. "b157,b157" "0,1" bitfld.long 0xC 28. "b156,b156" "0,1" newline bitfld.long 0xC 27. "b155,b155" "0,1" bitfld.long 0xC 26. "b154,b154" "0,1" bitfld.long 0xC 25. "b153,b153" "0,1" bitfld.long 0xC 24. "b152,b152" "0,1" newline bitfld.long 0xC 23. "b151,b151" "0,1" bitfld.long 0xC 22. "b150,b150" "0,1" bitfld.long 0xC 21. "b149,b149" "0,1" bitfld.long 0xC 20. "b148,b148" "0,1" newline bitfld.long 0xC 19. "b147,b147" "0,1" bitfld.long 0xC 18. "b146,b146" "0,1" bitfld.long 0xC 17. "b145,b145" "0,1" bitfld.long 0xC 16. "b144,b144" "0,1" newline bitfld.long 0xC 15. "b143,b143" "0,1" bitfld.long 0xC 14. "b142,b142" "0,1" bitfld.long 0xC 13. "b141,b141" "0,1" bitfld.long 0xC 12. "b140,b140" "0,1" newline bitfld.long 0xC 11. "b139,b139" "0,1" bitfld.long 0xC 10. "b138,b138" "0,1" bitfld.long 0xC 9. "b137,b137" "0,1" bitfld.long 0xC 8. "b136,b136" "0,1" newline bitfld.long 0xC 7. "b135,b135" "0,1" bitfld.long 0xC 6. "b134,b134" "0,1" bitfld.long 0xC 5. "b133,b133" "0,1" bitfld.long 0xC 4. "b132,b132" "0,1" newline bitfld.long 0xC 3. "b131,b131" "0,1" bitfld.long 0xC 2. "b130,b130" "0,1" bitfld.long 0xC 1. "b129,b129" "0,1" bitfld.long 0xC 0. "b128,b128" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0xC 31. "K159,K159" "0,1" bitfld.long 0xC 30. "K158,K158" "0,1" bitfld.long 0xC 29. "K157,K157" "0,1" bitfld.long 0xC 28. "K156,K156" "0,1" newline bitfld.long 0xC 27. "K155,K155" "0,1" bitfld.long 0xC 26. "K154,K154" "0,1" bitfld.long 0xC 25. "K153,K153" "0,1" bitfld.long 0xC 24. "K152,K152" "0,1" newline bitfld.long 0xC 23. "K151,K151" "0,1" bitfld.long 0xC 22. "K150,K150" "0,1" bitfld.long 0xC 21. "K149,K149" "0,1" bitfld.long 0xC 20. "K148,K148" "0,1" newline bitfld.long 0xC 19. "K147,K147" "0,1" bitfld.long 0xC 18. "K146,K146" "0,1" bitfld.long 0xC 17. "K145,K145" "0,1" bitfld.long 0xC 16. "K144,K144" "0,1" newline bitfld.long 0xC 15. "K143,K143" "0,1" bitfld.long 0xC 14. "K142,K142" "0,1" bitfld.long 0xC 13. "K141,K141" "0,1" bitfld.long 0xC 12. "K140,K140" "0,1" newline bitfld.long 0xC 11. "K139,K139" "0,1" bitfld.long 0xC 10. "K138,K138" "0,1" bitfld.long 0xC 9. "K137,K137" "0,1" bitfld.long 0xC 8. "K136,K136" "0,1" newline bitfld.long 0xC 7. "K135,K135" "0,1" bitfld.long 0xC 6. "K134,K134" "0,1" bitfld.long 0xC 5. "K133,K133" "0,1" bitfld.long 0xC 4. "K132,K132" "0,1" newline bitfld.long 0xC 3. "K131,K131" "0,1" bitfld.long 0xC 2. "K130,K130" "0,1" bitfld.long 0xC 1. "K129,K129" "0,1" bitfld.long 0xC 0. "K128,K128" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 31. "b159,b159" "0,1" bitfld.long 0xC 30. "b158,b158" "0,1" bitfld.long 0xC 29. "b157,b157" "0,1" bitfld.long 0xC 28. "b156,b156" "0,1" newline bitfld.long 0xC 27. "b155,b155" "0,1" bitfld.long 0xC 26. "b154,b154" "0,1" bitfld.long 0xC 25. "b153,b153" "0,1" bitfld.long 0xC 24. "b152,b152" "0,1" newline bitfld.long 0xC 23. "b151,b151" "0,1" bitfld.long 0xC 22. "b150,b150" "0,1" bitfld.long 0xC 21. "b149,b149" "0,1" bitfld.long 0xC 20. "b148,b148" "0,1" newline bitfld.long 0xC 19. "b147,b147" "0,1" bitfld.long 0xC 18. "b146,b146" "0,1" bitfld.long 0xC 17. "b145,b145" "0,1" bitfld.long 0xC 16. "b144,b144" "0,1" newline bitfld.long 0xC 15. "b143,b143" "0,1" bitfld.long 0xC 14. "b142,b142" "0,1" bitfld.long 0xC 13. "b141,b141" "0,1" bitfld.long 0xC 12. "b140,b140" "0,1" newline bitfld.long 0xC 11. "b139,b139" "0,1" bitfld.long 0xC 10. "b138,b138" "0,1" bitfld.long 0xC 9. "b137,b137" "0,1" bitfld.long 0xC 8. "b136,b136" "0,1" newline bitfld.long 0xC 7. "b135,b135" "0,1" bitfld.long 0xC 6. "b134,b134" "0,1" bitfld.long 0xC 5. "b133,b133" "0,1" bitfld.long 0xC 4. "b132,b132" "0,1" newline bitfld.long 0xC 3. "b131,b131" "0,1" bitfld.long 0xC 2. "b130,b130" "0,1" bitfld.long 0xC 1. "b129,b129" "0,1" bitfld.long 0xC 0. "b128,b128" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 31. "b159,b159" "0,1" bitfld.long 0xC 30. "b158,b158" "0,1" bitfld.long 0xC 29. "b157,b157" "0,1" bitfld.long 0xC 28. "b156,b156" "0,1" newline bitfld.long 0xC 27. "b155,b155" "0,1" bitfld.long 0xC 26. "b154,b154" "0,1" bitfld.long 0xC 25. "b153,b153" "0,1" bitfld.long 0xC 24. "b152,b152" "0,1" newline bitfld.long 0xC 23. "b151,b151" "0,1" bitfld.long 0xC 22. "b150,b150" "0,1" bitfld.long 0xC 21. "b149,b149" "0,1" bitfld.long 0xC 20. "b148,b148" "0,1" newline bitfld.long 0xC 19. "b147,b147" "0,1" bitfld.long 0xC 18. "b146,b146" "0,1" bitfld.long 0xC 17. "b145,b145" "0,1" bitfld.long 0xC 16. "b144,b144" "0,1" newline bitfld.long 0xC 15. "b143,b143" "0,1" bitfld.long 0xC 14. "b142,b142" "0,1" bitfld.long 0xC 13. "b141,b141" "0,1" bitfld.long 0xC 12. "b140,b140" "0,1" newline bitfld.long 0xC 11. "b139,b139" "0,1" bitfld.long 0xC 10. "b138,b138" "0,1" bitfld.long 0xC 9. "b137,b137" "0,1" bitfld.long 0xC 8. "b136,b136" "0,1" newline bitfld.long 0xC 7. "b135,b135" "0,1" bitfld.long 0xC 6. "b134,b134" "0,1" bitfld.long 0xC 5. "b133,b133" "0,1" bitfld.long 0xC 4. "b132,b132" "0,1" newline bitfld.long 0xC 3. "b131,b131" "0,1" bitfld.long 0xC 2. "b130,b130" "0,1" bitfld.long 0xC 1. "b129,b129" "0,1" bitfld.long 0xC 0. "b128,b128" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 31. "b159,b159" "0,1" bitfld.long 0xC 30. "b158,b158" "0,1" bitfld.long 0xC 29. "b157,b157" "0,1" bitfld.long 0xC 28. "b156,b156" "0,1" newline bitfld.long 0xC 27. "b155,b155" "0,1" bitfld.long 0xC 26. "b154,b154" "0,1" bitfld.long 0xC 25. "b153,b153" "0,1" bitfld.long 0xC 24. "b152,b152" "0,1" newline bitfld.long 0xC 23. "b151,b151" "0,1" bitfld.long 0xC 22. "b150,b150" "0,1" bitfld.long 0xC 21. "b149,b149" "0,1" bitfld.long 0xC 20. "b148,b148" "0,1" newline bitfld.long 0xC 19. "b147,b147" "0,1" bitfld.long 0xC 18. "b146,b146" "0,1" bitfld.long 0xC 17. "b145,b145" "0,1" bitfld.long 0xC 16. "b144,b144" "0,1" newline bitfld.long 0xC 15. "b143,b143" "0,1" bitfld.long 0xC 14. "b142,b142" "0,1" bitfld.long 0xC 13. "b141,b141" "0,1" bitfld.long 0xC 12. "b140,b140" "0,1" newline bitfld.long 0xC 11. "b139,b139" "0,1" bitfld.long 0xC 10. "b138,b138" "0,1" bitfld.long 0xC 9. "b137,b137" "0,1" bitfld.long 0xC 8. "b136,b136" "0,1" newline bitfld.long 0xC 7. "b135,b135" "0,1" bitfld.long 0xC 6. "b134,b134" "0,1" bitfld.long 0xC 5. "b133,b133" "0,1" bitfld.long 0xC 4. "b132,b132" "0,1" newline bitfld.long 0xC 3. "b131,b131" "0,1" bitfld.long 0xC 2. "b130,b130" "0,1" bitfld.long 0xC 1. "b129,b129" "0,1" bitfld.long 0xC 0. "b128,b128" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 31. "b159,b159" "0,1" bitfld.long 0xC 30. "b158,b158" "0,1" bitfld.long 0xC 29. "b157,b157" "0,1" bitfld.long 0xC 28. "b156,b156" "0,1" newline bitfld.long 0xC 27. "b155,b155" "0,1" bitfld.long 0xC 26. "b154,b154" "0,1" bitfld.long 0xC 25. "b153,b153" "0,1" bitfld.long 0xC 24. "b152,b152" "0,1" newline bitfld.long 0xC 23. "b151,b151" "0,1" bitfld.long 0xC 22. "b150,b150" "0,1" bitfld.long 0xC 21. "b149,b149" "0,1" bitfld.long 0xC 20. "b148,b148" "0,1" newline bitfld.long 0xC 19. "b147,b147" "0,1" bitfld.long 0xC 18. "b146,b146" "0,1" bitfld.long 0xC 17. "b145,b145" "0,1" bitfld.long 0xC 16. "b144,b144" "0,1" newline bitfld.long 0xC 15. "b143,b143" "0,1" bitfld.long 0xC 14. "b142,b142" "0,1" bitfld.long 0xC 13. "b141,b141" "0,1" bitfld.long 0xC 12. "b140,b140" "0,1" newline bitfld.long 0xC 11. "b139,b139" "0,1" bitfld.long 0xC 10. "b138,b138" "0,1" bitfld.long 0xC 9. "b137,b137" "0,1" bitfld.long 0xC 8. "b136,b136" "0,1" newline bitfld.long 0xC 7. "b135,b135" "0,1" bitfld.long 0xC 6. "b134,b134" "0,1" bitfld.long 0xC 5. "b133,b133" "0,1" bitfld.long 0xC 4. "b132,b132" "0,1" newline bitfld.long 0xC 3. "b131,b131" "0,1" bitfld.long 0xC 2. "b130,b130" "0,1" bitfld.long 0xC 1. "b129,b129" "0,1" bitfld.long 0xC 0. "b128,b128" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0xC 31. "b159,b159" "0,1" bitfld.long 0xC 30. "b158,b158" "0,1" bitfld.long 0xC 29. "b157,b157" "0,1" bitfld.long 0xC 28. "b156,b156" "0,1" newline bitfld.long 0xC 27. "b155,b155" "0,1" bitfld.long 0xC 26. "b154,b154" "0,1" bitfld.long 0xC 25. "b153,b153" "0,1" bitfld.long 0xC 24. "b152,b152" "0,1" newline bitfld.long 0xC 23. "b151,b151" "0,1" bitfld.long 0xC 22. "b150,b150" "0,1" bitfld.long 0xC 21. "b149,b149" "0,1" bitfld.long 0xC 20. "b148,b148" "0,1" newline bitfld.long 0xC 19. "b147,b147" "0,1" bitfld.long 0xC 18. "b146,b146" "0,1" bitfld.long 0xC 17. "b145,b145" "0,1" bitfld.long 0xC 16. "b144,b144" "0,1" newline bitfld.long 0xC 15. "b143,b143" "0,1" bitfld.long 0xC 14. "b142,b142" "0,1" bitfld.long 0xC 13. "b141,b141" "0,1" bitfld.long 0xC 12. "b140,b140" "0,1" newline bitfld.long 0xC 11. "b139,b139" "0,1" bitfld.long 0xC 10. "b138,b138" "0,1" bitfld.long 0xC 9. "b137,b137" "0,1" bitfld.long 0xC 8. "b136,b136" "0,1" newline bitfld.long 0xC 7. "b135,b135" "0,1" bitfld.long 0xC 6. "b134,b134" "0,1" bitfld.long 0xC 5. "b133,b133" "0,1" bitfld.long 0xC 4. "b132,b132" "0,1" newline bitfld.long 0xC 3. "b131,b131" "0,1" bitfld.long 0xC 2. "b130,b130" "0,1" bitfld.long 0xC 1. "b129,b129" "0,1" bitfld.long 0xC 0. "b128,b128" "0,1" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0xC 31. "b159,b159" "0,1" bitfld.long 0xC 30. "b158,b158" "0,1" bitfld.long 0xC 29. "b157,b157" "0,1" bitfld.long 0xC 28. "b156,b156" "0,1" newline bitfld.long 0xC 27. "b155,b155" "0,1" bitfld.long 0xC 26. "b154,b154" "0,1" bitfld.long 0xC 25. "b153,b153" "0,1" bitfld.long 0xC 24. "b152,b152" "0,1" newline bitfld.long 0xC 23. "b151,b151" "0,1" bitfld.long 0xC 22. "b150,b150" "0,1" bitfld.long 0xC 21. "b149,b149" "0,1" bitfld.long 0xC 20. "b148,b148" "0,1" newline bitfld.long 0xC 19. "b147,b147" "0,1" bitfld.long 0xC 18. "b146,b146" "0,1" bitfld.long 0xC 17. "b145,b145" "0,1" bitfld.long 0xC 16. "b144,b144" "0,1" newline bitfld.long 0xC 15. "b143,b143" "0,1" bitfld.long 0xC 14. "b142,b142" "0,1" bitfld.long 0xC 13. "b141,b141" "0,1" bitfld.long 0xC 12. "b140,b140" "0,1" newline bitfld.long 0xC 11. "b139,b139" "0,1" bitfld.long 0xC 10. "b138,b138" "0,1" bitfld.long 0xC 9. "b137,b137" "0,1" bitfld.long 0xC 8. "b136,b136" "0,1" newline bitfld.long 0xC 7. "b135,b135" "0,1" bitfld.long 0xC 6. "b134,b134" "0,1" bitfld.long 0xC 5. "b133,b133" "0,1" bitfld.long 0xC 4. "b132,b132" "0,1" newline bitfld.long 0xC 3. "b131,b131" "0,1" bitfld.long 0xC 2. "b130,b130" "0,1" bitfld.long 0xC 1. "b129,b129" "0,1" bitfld.long 0xC 0. "b128,b128" "0,1" endif line.long 0x10 "K2LR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x10 31. "k127,k127" "0,1" bitfld.long 0x10 30. "k126,k126" "0,1" bitfld.long 0x10 29. "k125,k125" "0,1" bitfld.long 0x10 28. "k124,k124" "0,1" newline bitfld.long 0x10 27. "k123,k123" "0,1" bitfld.long 0x10 26. "k122,k122" "0,1" bitfld.long 0x10 24. "k120,k120" "0,1" bitfld.long 0x10 23. "k119,k119" "0,1" newline bitfld.long 0x10 22. "k118,k118" "0,1" bitfld.long 0x10 21. "k117,k117" "0,1" bitfld.long 0x10 20. "k116,k116" "0,1" bitfld.long 0x10 19. "k115,k115" "0,1" newline bitfld.long 0x10 18. "k114,k114" "0,1" bitfld.long 0x10 17. "k113,k113" "0,1" bitfld.long 0x10 16. "k112,k112" "0,1" bitfld.long 0x10 15. "k111,k111" "0,1" newline bitfld.long 0x10 14. "k110,k110" "0,1" bitfld.long 0x10 13. "k109,k109" "0,1" bitfld.long 0x10 12. "k108,k108" "0,1" bitfld.long 0x10 11. "k107,k107" "0,1" newline bitfld.long 0x10 10. "k106,k106" "0,1" bitfld.long 0x10 9. "k105,k105" "0,1" bitfld.long 0x10 8. "k104,k104" "0,1" bitfld.long 0x10 7. "k103,k103" "0,1" newline bitfld.long 0x10 6. "k102,k102" "0,1" bitfld.long 0x10 5. "k101,k101" "0,1" bitfld.long 0x10 4. "k100,k100" "0,1" bitfld.long 0x10 3. "k99,k99" "0,1" newline bitfld.long 0x10 2. "k98,k98" "0,1" bitfld.long 0x10 1. "k97,k97" "0,1" bitfld.long 0x10 0. "k96,k96" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x10 31. "K127,K127" "0,1" newline bitfld.long 0x10 30. "K126,K126" "0,1" bitfld.long 0x10 29. "K125,K125" "0,1" bitfld.long 0x10 28. "K124,K124" "0,1" bitfld.long 0x10 27. "K123,K123" "0,1" newline bitfld.long 0x10 26. "K122,K122" "0,1" bitfld.long 0x10 25. "K121,K121" "0,1" bitfld.long 0x10 24. "K120,K120" "0,1" bitfld.long 0x10 23. "K119,K119" "0,1" newline bitfld.long 0x10 22. "K118,K118" "0,1" bitfld.long 0x10 21. "K117,K117" "0,1" bitfld.long 0x10 20. "K116,K116" "0,1" bitfld.long 0x10 19. "K115,K115" "0,1" newline bitfld.long 0x10 18. "K114,K114" "0,1" bitfld.long 0x10 17. "K113,K113" "0,1" bitfld.long 0x10 16. "K112,K112" "0,1" bitfld.long 0x10 15. "K111,K111" "0,1" newline bitfld.long 0x10 14. "K110,K110" "0,1" bitfld.long 0x10 13. "K109,K109" "0,1" bitfld.long 0x10 12. "K108,K108" "0,1" bitfld.long 0x10 11. "K107,K107" "0,1" newline bitfld.long 0x10 10. "K106,K106" "0,1" bitfld.long 0x10 9. "K105,K105" "0,1" bitfld.long 0x10 8. "K104,K104" "0,1" bitfld.long 0x10 7. "K103,K103" "0,1" newline bitfld.long 0x10 6. "K102,K102" "0,1" bitfld.long 0x10 5. "K101,K101" "0,1" bitfld.long 0x10 4. "K100,K100" "0,1" bitfld.long 0x10 3. "K99,K99" "0,1" newline bitfld.long 0x10 2. "K98,K98" "0,1" bitfld.long 0x10 1. "K97,K97" "0,1" bitfld.long 0x10 0. "K96,K96" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x10 31. "b127,b127" "0,1" newline bitfld.long 0x10 30. "b126,b126" "0,1" bitfld.long 0x10 29. "b125,b125" "0,1" bitfld.long 0x10 28. "b124,b124" "0,1" bitfld.long 0x10 27. "b123,b123" "0,1" newline bitfld.long 0x10 26. "b122,b122" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x10 31. "b127,b127" "0,1" bitfld.long 0x10 30. "b126,b126" "0,1" bitfld.long 0x10 29. "b125,b125" "0,1" newline bitfld.long 0x10 28. "b124,b124" "0,1" bitfld.long 0x10 27. "b123,b123" "0,1" bitfld.long 0x10 26. "b122,b122" "0,1" bitfld.long 0x10 25. "b121,b121" "0,1" newline bitfld.long 0x10 24. "b120,b120" "0,1" bitfld.long 0x10 23. "b119,b119" "0,1" bitfld.long 0x10 22. "b118,b118" "0,1" bitfld.long 0x10 21. "b117,b117" "0,1" newline bitfld.long 0x10 20. "b116,b116" "0,1" bitfld.long 0x10 19. "b115,b115" "0,1" bitfld.long 0x10 18. "b114,b114" "0,1" bitfld.long 0x10 17. "b113,b113" "0,1" newline bitfld.long 0x10 16. "b112,b112" "0,1" bitfld.long 0x10 15. "b111,b111" "0,1" bitfld.long 0x10 14. "b110,b110" "0,1" bitfld.long 0x10 13. "b109,b109" "0,1" newline bitfld.long 0x10 12. "b108,b108" "0,1" bitfld.long 0x10 11. "b107,b107" "0,1" bitfld.long 0x10 10. "b106,b106" "0,1" bitfld.long 0x10 9. "b105,b105" "0,1" newline bitfld.long 0x10 8. "b104,b104" "0,1" bitfld.long 0x10 7. "b103,b103" "0,1" bitfld.long 0x10 6. "b102,b102" "0,1" bitfld.long 0x10 5. "b101,b101" "0,1" newline bitfld.long 0x10 4. "b100,b100" "0,1" bitfld.long 0x10 3. "b99,b99" "0,1" bitfld.long 0x10 2. "b98,b98" "0,1" bitfld.long 0x10 1. "b97,b97" "0,1" newline bitfld.long 0x10 0. "b96,b96" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x10 31. "b127,b127" "0,1" bitfld.long 0x10 30. "b126,b126" "0,1" bitfld.long 0x10 29. "b125,b125" "0,1" newline bitfld.long 0x10 28. "b124,b124" "0,1" bitfld.long 0x10 27. "b123,b123" "0,1" bitfld.long 0x10 26. "b122,b122" "0,1" bitfld.long 0x10 25. "b121,b121" "0,1" newline bitfld.long 0x10 24. "b120,b120" "0,1" bitfld.long 0x10 23. "b119,b119" "0,1" bitfld.long 0x10 22. "b118,b118" "0,1" bitfld.long 0x10 21. "b117,b117" "0,1" newline bitfld.long 0x10 20. "b116,b116" "0,1" bitfld.long 0x10 19. "b115,b115" "0,1" bitfld.long 0x10 18. "b114,b114" "0,1" bitfld.long 0x10 17. "b113,b113" "0,1" newline bitfld.long 0x10 16. "b112,b112" "0,1" bitfld.long 0x10 15. "b111,b111" "0,1" bitfld.long 0x10 14. "b110,b110" "0,1" bitfld.long 0x10 13. "b109,b109" "0,1" newline bitfld.long 0x10 12. "b108,b108" "0,1" bitfld.long 0x10 11. "b107,b107" "0,1" bitfld.long 0x10 10. "b106,b106" "0,1" bitfld.long 0x10 9. "b105,b105" "0,1" newline bitfld.long 0x10 8. "b104,b104" "0,1" bitfld.long 0x10 7. "b103,b103" "0,1" bitfld.long 0x10 6. "b102,b102" "0,1" bitfld.long 0x10 5. "b101,b101" "0,1" newline bitfld.long 0x10 4. "b100,b100" "0,1" bitfld.long 0x10 3. "b99,b99" "0,1" bitfld.long 0x10 2. "b98,b98" "0,1" bitfld.long 0x10 1. "b97,b97" "0,1" newline bitfld.long 0x10 0. "b96,b96" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x10 31. "b127,b127" "0,1" bitfld.long 0x10 30. "b126,b126" "0,1" bitfld.long 0x10 29. "b125,b125" "0,1" newline bitfld.long 0x10 28. "b124,b124" "0,1" bitfld.long 0x10 27. "b123,b123" "0,1" bitfld.long 0x10 26. "b122,b122" "0,1" bitfld.long 0x10 25. "b121,b121" "0,1" newline bitfld.long 0x10 24. "b120,b120" "0,1" bitfld.long 0x10 23. "b119,b119" "0,1" bitfld.long 0x10 22. "b118,b118" "0,1" bitfld.long 0x10 21. "b117,b117" "0,1" newline bitfld.long 0x10 20. "b116,b116" "0,1" bitfld.long 0x10 19. "b115,b115" "0,1" bitfld.long 0x10 18. "b114,b114" "0,1" bitfld.long 0x10 17. "b113,b113" "0,1" newline bitfld.long 0x10 16. "b112,b112" "0,1" bitfld.long 0x10 15. "b111,b111" "0,1" bitfld.long 0x10 14. "b110,b110" "0,1" bitfld.long 0x10 13. "b109,b109" "0,1" newline bitfld.long 0x10 12. "b108,b108" "0,1" bitfld.long 0x10 11. "b107,b107" "0,1" bitfld.long 0x10 10. "b106,b106" "0,1" bitfld.long 0x10 9. "b105,b105" "0,1" newline bitfld.long 0x10 8. "b104,b104" "0,1" bitfld.long 0x10 7. "b103,b103" "0,1" bitfld.long 0x10 6. "b102,b102" "0,1" bitfld.long 0x10 5. "b101,b101" "0,1" newline bitfld.long 0x10 4. "b100,b100" "0,1" bitfld.long 0x10 3. "b99,b99" "0,1" bitfld.long 0x10 2. "b98,b98" "0,1" bitfld.long 0x10 1. "b97,b97" "0,1" newline bitfld.long 0x10 0. "b96,b96" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x10 31. "b127,b127" "0,1" bitfld.long 0x10 30. "b126,b126" "0,1" bitfld.long 0x10 29. "b125,b125" "0,1" newline bitfld.long 0x10 28. "b124,b124" "0,1" bitfld.long 0x10 27. "b123,b123" "0,1" bitfld.long 0x10 26. "b122,b122" "0,1" bitfld.long 0x10 25. "b121,b121" "0,1" newline bitfld.long 0x10 24. "b120,b120" "0,1" bitfld.long 0x10 23. "b119,b119" "0,1" bitfld.long 0x10 22. "b118,b118" "0,1" bitfld.long 0x10 21. "b117,b117" "0,1" newline bitfld.long 0x10 20. "b116,b116" "0,1" bitfld.long 0x10 19. "b115,b115" "0,1" bitfld.long 0x10 18. "b114,b114" "0,1" bitfld.long 0x10 17. "b113,b113" "0,1" newline bitfld.long 0x10 16. "b112,b112" "0,1" bitfld.long 0x10 15. "b111,b111" "0,1" bitfld.long 0x10 14. "b110,b110" "0,1" bitfld.long 0x10 13. "b109,b109" "0,1" newline bitfld.long 0x10 12. "b108,b108" "0,1" bitfld.long 0x10 11. "b107,b107" "0,1" bitfld.long 0x10 10. "b106,b106" "0,1" bitfld.long 0x10 9. "b105,b105" "0,1" newline bitfld.long 0x10 8. "b104,b104" "0,1" bitfld.long 0x10 7. "b103,b103" "0,1" bitfld.long 0x10 6. "b102,b102" "0,1" bitfld.long 0x10 5. "b101,b101" "0,1" newline bitfld.long 0x10 4. "b100,b100" "0,1" bitfld.long 0x10 3. "b99,b99" "0,1" bitfld.long 0x10 2. "b98,b98" "0,1" bitfld.long 0x10 1. "b97,b97" "0,1" newline bitfld.long 0x10 0. "b96,b96" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x10 31. "b127,b127" "0,1" bitfld.long 0x10 30. "b126,b126" "0,1" bitfld.long 0x10 29. "b125,b125" "0,1" newline bitfld.long 0x10 28. "b124,b124" "0,1" bitfld.long 0x10 27. "b123,b123" "0,1" bitfld.long 0x10 26. "b122,b122" "0,1" bitfld.long 0x10 25. "b121,b121" "0,1" newline bitfld.long 0x10 24. "b120,b120" "0,1" bitfld.long 0x10 23. "b119,b119" "0,1" bitfld.long 0x10 22. "b118,b118" "0,1" bitfld.long 0x10 21. "b117,b117" "0,1" newline bitfld.long 0x10 20. "b116,b116" "0,1" bitfld.long 0x10 19. "b115,b115" "0,1" bitfld.long 0x10 18. "b114,b114" "0,1" bitfld.long 0x10 17. "b113,b113" "0,1" newline bitfld.long 0x10 16. "b112,b112" "0,1" bitfld.long 0x10 15. "b111,b111" "0,1" bitfld.long 0x10 14. "b110,b110" "0,1" bitfld.long 0x10 13. "b109,b109" "0,1" newline bitfld.long 0x10 12. "b108,b108" "0,1" bitfld.long 0x10 11. "b107,b107" "0,1" bitfld.long 0x10 10. "b106,b106" "0,1" bitfld.long 0x10 9. "b105,b105" "0,1" newline bitfld.long 0x10 8. "b104,b104" "0,1" bitfld.long 0x10 7. "b103,b103" "0,1" bitfld.long 0x10 6. "b102,b102" "0,1" bitfld.long 0x10 5. "b101,b101" "0,1" newline bitfld.long 0x10 4. "b100,b100" "0,1" bitfld.long 0x10 3. "b99,b99" "0,1" bitfld.long 0x10 2. "b98,b98" "0,1" bitfld.long 0x10 1. "b97,b97" "0,1" newline bitfld.long 0x10 0. "b96,b96" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x10 31. "b127,b127" "0,1" bitfld.long 0x10 30. "b126,b126" "0,1" bitfld.long 0x10 29. "b125,b125" "0,1" newline bitfld.long 0x10 28. "b124,b124" "0,1" bitfld.long 0x10 27. "b123,b123" "0,1" bitfld.long 0x10 26. "b122,b122" "0,1" bitfld.long 0x10 25. "b121,b121" "0,1" newline bitfld.long 0x10 24. "b120,b120" "0,1" bitfld.long 0x10 23. "b119,b119" "0,1" bitfld.long 0x10 22. "b118,b118" "0,1" bitfld.long 0x10 21. "b117,b117" "0,1" newline bitfld.long 0x10 20. "b116,b116" "0,1" bitfld.long 0x10 19. "b115,b115" "0,1" bitfld.long 0x10 18. "b114,b114" "0,1" bitfld.long 0x10 17. "b113,b113" "0,1" newline bitfld.long 0x10 16. "b112,b112" "0,1" bitfld.long 0x10 15. "b111,b111" "0,1" bitfld.long 0x10 14. "b110,b110" "0,1" bitfld.long 0x10 13. "b109,b109" "0,1" newline bitfld.long 0x10 12. "b108,b108" "0,1" bitfld.long 0x10 11. "b107,b107" "0,1" bitfld.long 0x10 10. "b106,b106" "0,1" bitfld.long 0x10 9. "b105,b105" "0,1" newline bitfld.long 0x10 8. "b104,b104" "0,1" bitfld.long 0x10 7. "b103,b103" "0,1" bitfld.long 0x10 6. "b102,b102" "0,1" bitfld.long 0x10 5. "b101,b101" "0,1" newline bitfld.long 0x10 4. "b100,b100" "0,1" bitfld.long 0x10 3. "b99,b99" "0,1" bitfld.long 0x10 2. "b98,b98" "0,1" bitfld.long 0x10 1. "b97,b97" "0,1" newline bitfld.long 0x10 0. "b96,b96" "0,1" endif sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) bitfld.long 0x10 25. "b121,b121" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x10 24. "b120,b120" "0,1" bitfld.long 0x10 23. "b119,b119" "0,1" newline bitfld.long 0x10 22. "b118,b118" "0,1" bitfld.long 0x10 21. "b117,b117" "0,1" bitfld.long 0x10 20. "b116,b116" "0,1" bitfld.long 0x10 19. "b115,b115" "0,1" newline bitfld.long 0x10 18. "b114,b114" "0,1" bitfld.long 0x10 17. "b113,b113" "0,1" bitfld.long 0x10 16. "b112,b112" "0,1" bitfld.long 0x10 15. "b111,b111" "0,1" newline bitfld.long 0x10 14. "b110,b110" "0,1" bitfld.long 0x10 13. "b109,b109" "0,1" bitfld.long 0x10 12. "b108,b108" "0,1" bitfld.long 0x10 11. "b107,b107" "0,1" newline bitfld.long 0x10 10. "b106,b106" "0,1" bitfld.long 0x10 9. "b105,b105" "0,1" bitfld.long 0x10 8. "b104,b104" "0,1" bitfld.long 0x10 7. "b103,b103" "0,1" newline bitfld.long 0x10 6. "b102,b102" "0,1" bitfld.long 0x10 5. "b101,b101" "0,1" bitfld.long 0x10 4. "b100,b100" "0,1" bitfld.long 0x10 3. "b99,b99" "0,1" newline bitfld.long 0x10 2. "b98,b98" "0,1" bitfld.long 0x10 1. "b97,b97" "0,1" bitfld.long 0x10 0. "b96,b96" "0,1" endif line.long 0x14 "K2RR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x14 31. "k95,k95" "0,1" bitfld.long 0x14 30. "k94,k94" "0,1" bitfld.long 0x14 29. "k93,k93" "0,1" bitfld.long 0x14 28. "k92,k92" "0,1" newline bitfld.long 0x14 27. "k91,k91" "0,1" bitfld.long 0x14 26. "k90,k90" "0,1" bitfld.long 0x14 25. "k89,k89" "0,1" bitfld.long 0x14 24. "k88,k88" "0,1" newline bitfld.long 0x14 23. "k87,k87" "0,1" bitfld.long 0x14 22. "k86,k86" "0,1" bitfld.long 0x14 21. "k85,k85" "0,1" bitfld.long 0x14 20. "k84,k84" "0,1" newline bitfld.long 0x14 19. "k83,k83" "0,1" bitfld.long 0x14 18. "k82,k82" "0,1" bitfld.long 0x14 17. "k81,k81" "0,1" bitfld.long 0x14 16. "k80,k80" "0,1" newline bitfld.long 0x14 15. "k79,k79" "0,1" bitfld.long 0x14 14. "k78,k78" "0,1" bitfld.long 0x14 13. "k77,k77" "0,1" bitfld.long 0x14 12. "k76,k76" "0,1" newline bitfld.long 0x14 11. "k75,k75" "0,1" bitfld.long 0x14 10. "k74,k74" "0,1" bitfld.long 0x14 9. "k73,k73" "0,1" bitfld.long 0x14 8. "k72,k72" "0,1" newline bitfld.long 0x14 7. "k71,k71" "0,1" bitfld.long 0x14 6. "k70,k70" "0,1" bitfld.long 0x14 5. "k69,k69" "0,1" bitfld.long 0x14 4. "k68,k68" "0,1" newline bitfld.long 0x14 3. "k67,k67" "0,1" bitfld.long 0x14 2. "k66,k66" "0,1" bitfld.long 0x14 1. "k65,k65" "0,1" bitfld.long 0x14 0. "k64,k64" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x14 31. "b95,b95" "0,1" bitfld.long 0x14 30. "b94,b94" "0,1" bitfld.long 0x14 29. "b93,b93" "0,1" bitfld.long 0x14 28. "b92,b92" "0,1" newline bitfld.long 0x14 27. "b91,b91" "0,1" bitfld.long 0x14 26. "b90,b90" "0,1" bitfld.long 0x14 25. "b89,b89" "0,1" bitfld.long 0x14 24. "b88,b88" "0,1" newline bitfld.long 0x14 23. "b87,b87" "0,1" bitfld.long 0x14 22. "b86,b86" "0,1" bitfld.long 0x14 21. "b85,b85" "0,1" bitfld.long 0x14 20. "b84,b84" "0,1" newline bitfld.long 0x14 19. "b83,b83" "0,1" bitfld.long 0x14 18. "b82,b82" "0,1" bitfld.long 0x14 17. "b81,b81" "0,1" bitfld.long 0x14 16. "b80,b80" "0,1" newline bitfld.long 0x14 15. "b79,b79" "0,1" bitfld.long 0x14 14. "b78,b78" "0,1" bitfld.long 0x14 13. "b77,b77" "0,1" bitfld.long 0x14 12. "b76,b76" "0,1" newline bitfld.long 0x14 11. "b75,b75" "0,1" bitfld.long 0x14 10. "b74,b74" "0,1" bitfld.long 0x14 9. "b73,b73" "0,1" bitfld.long 0x14 8. "b72,b72" "0,1" newline bitfld.long 0x14 7. "b71,b71" "0,1" bitfld.long 0x14 6. "b70,b70" "0,1" bitfld.long 0x14 5. "b69,b69" "0,1" bitfld.long 0x14 4. "b68,b68" "0,1" newline bitfld.long 0x14 3. "b67,b67" "0,1" bitfld.long 0x14 2. "b66,b66" "0,1" bitfld.long 0x14 1. "b65,b65" "0,1" bitfld.long 0x14 0. "b64,b64" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x14 31. "K95,K95" "0,1" bitfld.long 0x14 30. "K94,K94" "0,1" bitfld.long 0x14 29. "K93,K93" "0,1" bitfld.long 0x14 28. "K92,K92" "0,1" newline bitfld.long 0x14 27. "K91,K91" "0,1" bitfld.long 0x14 26. "K90,K90" "0,1" bitfld.long 0x14 25. "K89,K89" "0,1" bitfld.long 0x14 24. "K88,K88" "0,1" newline bitfld.long 0x14 23. "K87,K87" "0,1" bitfld.long 0x14 22. "K86,K86" "0,1" bitfld.long 0x14 21. "K85,K85" "0,1" bitfld.long 0x14 20. "K84,K84" "0,1" newline bitfld.long 0x14 19. "K83,K83" "0,1" bitfld.long 0x14 18. "K82,K82" "0,1" bitfld.long 0x14 17. "K81,K81" "0,1" bitfld.long 0x14 16. "K80,K80" "0,1" newline bitfld.long 0x14 15. "K79,K79" "0,1" bitfld.long 0x14 14. "K78,K78" "0,1" bitfld.long 0x14 13. "K77,K77" "0,1" bitfld.long 0x14 12. "K76,K76" "0,1" newline bitfld.long 0x14 11. "K75,K75" "0,1" bitfld.long 0x14 10. "K74,K74" "0,1" bitfld.long 0x14 9. "K73,K73" "0,1" bitfld.long 0x14 8. "K72,K72" "0,1" newline bitfld.long 0x14 7. "K71,K71" "0,1" bitfld.long 0x14 6. "K70,K70" "0,1" bitfld.long 0x14 5. "K69,K69" "0,1" bitfld.long 0x14 4. "K68,K68" "0,1" newline bitfld.long 0x14 3. "K67,K67" "0,1" bitfld.long 0x14 2. "K66,K66" "0,1" bitfld.long 0x14 1. "K65,K65" "0,1" bitfld.long 0x14 0. "K64,K64" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x14 31. "b95,b95" "0,1" bitfld.long 0x14 30. "b94,b94" "0,1" bitfld.long 0x14 29. "b93,b93" "0,1" bitfld.long 0x14 28. "b92,b92" "0,1" newline bitfld.long 0x14 27. "b91,b91" "0,1" bitfld.long 0x14 26. "b90,b90" "0,1" bitfld.long 0x14 25. "b89,b89" "0,1" bitfld.long 0x14 24. "b88,b88" "0,1" newline bitfld.long 0x14 23. "b87,b87" "0,1" bitfld.long 0x14 22. "b86,b86" "0,1" bitfld.long 0x14 21. "b85,b85" "0,1" bitfld.long 0x14 20. "b84,b84" "0,1" newline bitfld.long 0x14 19. "b83,b83" "0,1" bitfld.long 0x14 18. "b82,b82" "0,1" bitfld.long 0x14 17. "b81,b81" "0,1" bitfld.long 0x14 16. "b80,b80" "0,1" newline bitfld.long 0x14 15. "b79,b79" "0,1" bitfld.long 0x14 14. "b78,b78" "0,1" bitfld.long 0x14 13. "b77,b77" "0,1" bitfld.long 0x14 12. "b76,b76" "0,1" newline bitfld.long 0x14 11. "b75,b75" "0,1" bitfld.long 0x14 10. "b74,b74" "0,1" bitfld.long 0x14 9. "b73,b73" "0,1" bitfld.long 0x14 8. "b72,b72" "0,1" newline bitfld.long 0x14 7. "b71,b71" "0,1" bitfld.long 0x14 6. "b70,b70" "0,1" bitfld.long 0x14 5. "b69,b69" "0,1" bitfld.long 0x14 4. "b68,b68" "0,1" newline bitfld.long 0x14 3. "b67,b67" "0,1" bitfld.long 0x14 2. "b66,b66" "0,1" bitfld.long 0x14 1. "b65,b65" "0,1" bitfld.long 0x14 0. "b64,b64" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x14 31. "b95,b95" "0,1" bitfld.long 0x14 30. "b94,b94" "0,1" bitfld.long 0x14 29. "b93,b93" "0,1" bitfld.long 0x14 28. "b92,b92" "0,1" newline bitfld.long 0x14 27. "b91,b91" "0,1" bitfld.long 0x14 26. "b90,b90" "0,1" bitfld.long 0x14 25. "b89,b89" "0,1" bitfld.long 0x14 24. "b88,b88" "0,1" newline bitfld.long 0x14 23. "b87,b87" "0,1" bitfld.long 0x14 22. "b86,b86" "0,1" bitfld.long 0x14 21. "b85,b85" "0,1" bitfld.long 0x14 20. "b84,b84" "0,1" newline bitfld.long 0x14 19. "b83,b83" "0,1" bitfld.long 0x14 18. "b82,b82" "0,1" bitfld.long 0x14 17. "b81,b81" "0,1" bitfld.long 0x14 16. "b80,b80" "0,1" newline bitfld.long 0x14 15. "b79,b79" "0,1" bitfld.long 0x14 14. "b78,b78" "0,1" bitfld.long 0x14 13. "b77,b77" "0,1" bitfld.long 0x14 12. "b76,b76" "0,1" newline bitfld.long 0x14 11. "b75,b75" "0,1" bitfld.long 0x14 10. "b74,b74" "0,1" bitfld.long 0x14 9. "b73,b73" "0,1" bitfld.long 0x14 8. "b72,b72" "0,1" newline bitfld.long 0x14 7. "b71,b71" "0,1" bitfld.long 0x14 6. "b70,b70" "0,1" bitfld.long 0x14 5. "b69,b69" "0,1" bitfld.long 0x14 4. "b68,b68" "0,1" newline bitfld.long 0x14 3. "b67,b67" "0,1" bitfld.long 0x14 2. "b66,b66" "0,1" bitfld.long 0x14 1. "b65,b65" "0,1" bitfld.long 0x14 0. "b64,b64" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x14 31. "b95,b95" "0,1" bitfld.long 0x14 30. "b94,b94" "0,1" bitfld.long 0x14 29. "b93,b93" "0,1" bitfld.long 0x14 28. "b92,b92" "0,1" newline bitfld.long 0x14 27. "b91,b91" "0,1" bitfld.long 0x14 26. "b90,b90" "0,1" bitfld.long 0x14 25. "b89,b89" "0,1" bitfld.long 0x14 24. "b88,b88" "0,1" newline bitfld.long 0x14 23. "b87,b87" "0,1" bitfld.long 0x14 22. "b86,b86" "0,1" bitfld.long 0x14 21. "b85,b85" "0,1" bitfld.long 0x14 20. "b84,b84" "0,1" newline bitfld.long 0x14 19. "b83,b83" "0,1" bitfld.long 0x14 18. "b82,b82" "0,1" bitfld.long 0x14 17. "b81,b81" "0,1" bitfld.long 0x14 16. "b80,b80" "0,1" newline bitfld.long 0x14 15. "b79,b79" "0,1" bitfld.long 0x14 14. "b78,b78" "0,1" bitfld.long 0x14 13. "b77,b77" "0,1" bitfld.long 0x14 12. "b76,b76" "0,1" newline bitfld.long 0x14 11. "b75,b75" "0,1" bitfld.long 0x14 10. "b74,b74" "0,1" bitfld.long 0x14 9. "b73,b73" "0,1" bitfld.long 0x14 8. "b72,b72" "0,1" newline bitfld.long 0x14 7. "b71,b71" "0,1" bitfld.long 0x14 6. "b70,b70" "0,1" bitfld.long 0x14 5. "b69,b69" "0,1" bitfld.long 0x14 4. "b68,b68" "0,1" newline bitfld.long 0x14 3. "b67,b67" "0,1" bitfld.long 0x14 2. "b66,b66" "0,1" bitfld.long 0x14 1. "b65,b65" "0,1" bitfld.long 0x14 0. "b64,b64" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x14 31. "b95,b95" "0,1" bitfld.long 0x14 30. "b94,b94" "0,1" bitfld.long 0x14 29. "b93,b93" "0,1" bitfld.long 0x14 28. "b92,b92" "0,1" newline bitfld.long 0x14 27. "b91,b91" "0,1" bitfld.long 0x14 26. "b90,b90" "0,1" bitfld.long 0x14 25. "b89,b89" "0,1" bitfld.long 0x14 24. "b88,b88" "0,1" newline bitfld.long 0x14 23. "b87,b87" "0,1" bitfld.long 0x14 22. "b86,b86" "0,1" bitfld.long 0x14 21. "b85,b85" "0,1" bitfld.long 0x14 20. "b84,b84" "0,1" newline bitfld.long 0x14 19. "b83,b83" "0,1" bitfld.long 0x14 18. "b82,b82" "0,1" bitfld.long 0x14 17. "b81,b81" "0,1" bitfld.long 0x14 16. "b80,b80" "0,1" newline bitfld.long 0x14 15. "b79,b79" "0,1" bitfld.long 0x14 14. "b78,b78" "0,1" bitfld.long 0x14 13. "b77,b77" "0,1" bitfld.long 0x14 12. "b76,b76" "0,1" newline bitfld.long 0x14 11. "b75,b75" "0,1" bitfld.long 0x14 10. "b74,b74" "0,1" bitfld.long 0x14 9. "b73,b73" "0,1" bitfld.long 0x14 8. "b72,b72" "0,1" newline bitfld.long 0x14 7. "b71,b71" "0,1" bitfld.long 0x14 6. "b70,b70" "0,1" bitfld.long 0x14 5. "b69,b69" "0,1" bitfld.long 0x14 4. "b68,b68" "0,1" newline bitfld.long 0x14 3. "b67,b67" "0,1" bitfld.long 0x14 2. "b66,b66" "0,1" bitfld.long 0x14 1. "b65,b65" "0,1" bitfld.long 0x14 0. "b64,b64" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x14 31. "b95,b95" "0,1" bitfld.long 0x14 30. "b94,b94" "0,1" bitfld.long 0x14 29. "b93,b93" "0,1" bitfld.long 0x14 28. "b92,b92" "0,1" newline bitfld.long 0x14 27. "b91,b91" "0,1" bitfld.long 0x14 26. "b90,b90" "0,1" bitfld.long 0x14 25. "b89,b89" "0,1" bitfld.long 0x14 24. "b88,b88" "0,1" newline bitfld.long 0x14 23. "b87,b87" "0,1" bitfld.long 0x14 22. "b86,b86" "0,1" bitfld.long 0x14 21. "b85,b85" "0,1" bitfld.long 0x14 20. "b84,b84" "0,1" newline bitfld.long 0x14 19. "b83,b83" "0,1" bitfld.long 0x14 18. "b82,b82" "0,1" bitfld.long 0x14 17. "b81,b81" "0,1" bitfld.long 0x14 16. "b80,b80" "0,1" newline bitfld.long 0x14 15. "b79,b79" "0,1" bitfld.long 0x14 14. "b78,b78" "0,1" bitfld.long 0x14 13. "b77,b77" "0,1" bitfld.long 0x14 12. "b76,b76" "0,1" newline bitfld.long 0x14 11. "b75,b75" "0,1" bitfld.long 0x14 10. "b74,b74" "0,1" bitfld.long 0x14 9. "b73,b73" "0,1" bitfld.long 0x14 8. "b72,b72" "0,1" newline bitfld.long 0x14 7. "b71,b71" "0,1" bitfld.long 0x14 6. "b70,b70" "0,1" bitfld.long 0x14 5. "b69,b69" "0,1" bitfld.long 0x14 4. "b68,b68" "0,1" newline bitfld.long 0x14 3. "b67,b67" "0,1" bitfld.long 0x14 2. "b66,b66" "0,1" bitfld.long 0x14 1. "b65,b65" "0,1" bitfld.long 0x14 0. "b64,b64" "0,1" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0x14 31. "b95,b95" "0,1" bitfld.long 0x14 30. "b94,b94" "0,1" bitfld.long 0x14 29. "b93,b93" "0,1" bitfld.long 0x14 28. "b92,b92" "0,1" newline bitfld.long 0x14 27. "b91,b91" "0,1" bitfld.long 0x14 26. "b90,b90" "0,1" bitfld.long 0x14 25. "b89,b89" "0,1" bitfld.long 0x14 24. "b88,b88" "0,1" newline bitfld.long 0x14 23. "b87,b87" "0,1" bitfld.long 0x14 22. "b86,b86" "0,1" bitfld.long 0x14 21. "b85,b85" "0,1" bitfld.long 0x14 20. "b84,b84" "0,1" newline bitfld.long 0x14 19. "b83,b83" "0,1" bitfld.long 0x14 18. "b82,b82" "0,1" bitfld.long 0x14 17. "b81,b81" "0,1" bitfld.long 0x14 16. "b80,b80" "0,1" newline bitfld.long 0x14 15. "b79,b79" "0,1" bitfld.long 0x14 14. "b78,b78" "0,1" bitfld.long 0x14 13. "b77,b77" "0,1" bitfld.long 0x14 12. "b76,b76" "0,1" newline bitfld.long 0x14 11. "b75,b75" "0,1" bitfld.long 0x14 10. "b74,b74" "0,1" bitfld.long 0x14 9. "b73,b73" "0,1" bitfld.long 0x14 8. "b72,b72" "0,1" newline bitfld.long 0x14 7. "b71,b71" "0,1" bitfld.long 0x14 6. "b70,b70" "0,1" bitfld.long 0x14 5. "b69,b69" "0,1" bitfld.long 0x14 4. "b68,b68" "0,1" newline bitfld.long 0x14 3. "b67,b67" "0,1" bitfld.long 0x14 2. "b66,b66" "0,1" bitfld.long 0x14 1. "b65,b65" "0,1" bitfld.long 0x14 0. "b64,b64" "0,1" endif line.long 0x18 "K3LR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x18 31. "k63,k63" "0,1" bitfld.long 0x18 30. "k62,k62" "0,1" bitfld.long 0x18 29. "k61,k61" "0,1" bitfld.long 0x18 28. "k60,k60" "0,1" newline bitfld.long 0x18 27. "k59,k59" "0,1" bitfld.long 0x18 26. "k58,k58" "0,1" bitfld.long 0x18 25. "k57,k57" "0,1" bitfld.long 0x18 24. "k56,k56" "0,1" newline bitfld.long 0x18 23. "k55,k55" "0,1" bitfld.long 0x18 22. "k54,k54" "0,1" bitfld.long 0x18 21. "k53,k53" "0,1" bitfld.long 0x18 20. "k52,k52" "0,1" newline bitfld.long 0x18 19. "k51,k51" "0,1" bitfld.long 0x18 18. "k50,k50" "0,1" bitfld.long 0x18 17. "k49,k49" "0,1" bitfld.long 0x18 16. "k48,k48" "0,1" newline bitfld.long 0x18 15. "k47,k47" "0,1" bitfld.long 0x18 14. "k46,k46" "0,1" bitfld.long 0x18 13. "k45,k45" "0,1" bitfld.long 0x18 12. "k44,k44" "0,1" newline bitfld.long 0x18 11. "k43,k43" "0,1" bitfld.long 0x18 10. "k42,k42" "0,1" bitfld.long 0x18 9. "k41,k41" "0,1" bitfld.long 0x18 8. "k40,k40" "0,1" newline bitfld.long 0x18 7. "k39,k39" "0,1" bitfld.long 0x18 6. "k38,k38" "0,1" bitfld.long 0x18 5. "k37,k37" "0,1" bitfld.long 0x18 4. "k36,k36" "0,1" newline bitfld.long 0x18 3. "k35,k35" "0,1" bitfld.long 0x18 2. "k34,k34" "0,1" bitfld.long 0x18 1. "k33,k33" "0,1" bitfld.long 0x18 0. "k32,k32" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x18 31. "b63,b63" "0,1" bitfld.long 0x18 30. "b62,b62" "0,1" bitfld.long 0x18 29. "b61,b61" "0,1" bitfld.long 0x18 28. "b60,b60" "0,1" newline bitfld.long 0x18 27. "b59,b59" "0,1" bitfld.long 0x18 26. "b58,b58" "0,1" bitfld.long 0x18 25. "b57,b57" "0,1" bitfld.long 0x18 24. "b56,b56" "0,1" newline bitfld.long 0x18 23. "b55,b55" "0,1" bitfld.long 0x18 22. "b54,b54" "0,1" bitfld.long 0x18 21. "b53,b53" "0,1" bitfld.long 0x18 20. "b52,b52" "0,1" newline bitfld.long 0x18 19. "b51,b51" "0,1" bitfld.long 0x18 18. "b50,b50" "0,1" bitfld.long 0x18 17. "b49,b49" "0,1" bitfld.long 0x18 16. "b48,b48" "0,1" newline bitfld.long 0x18 15. "b47,b47" "0,1" bitfld.long 0x18 14. "b46,b46" "0,1" bitfld.long 0x18 13. "b45,b45" "0,1" bitfld.long 0x18 12. "b44,b44" "0,1" newline bitfld.long 0x18 11. "b43,b43" "0,1" bitfld.long 0x18 10. "b42,b42" "0,1" bitfld.long 0x18 9. "b41,b41" "0,1" bitfld.long 0x18 8. "b40,b40" "0,1" newline bitfld.long 0x18 7. "b39,b39" "0,1" bitfld.long 0x18 6. "b38,b38" "0,1" bitfld.long 0x18 5. "b37,b37" "0,1" bitfld.long 0x18 4. "b36,b36" "0,1" newline bitfld.long 0x18 3. "b35,b35" "0,1" bitfld.long 0x18 2. "b34,b34" "0,1" bitfld.long 0x18 1. "b33,b33" "0,1" bitfld.long 0x18 0. "b32,b32" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x18 31. "K63,K63" "0,1" bitfld.long 0x18 30. "K62,K62" "0,1" bitfld.long 0x18 29. "K61,K61" "0,1" bitfld.long 0x18 28. "K60,K60" "0,1" newline bitfld.long 0x18 27. "K59,K59" "0,1" bitfld.long 0x18 26. "K58,K58" "0,1" bitfld.long 0x18 25. "K57,K57" "0,1" bitfld.long 0x18 24. "K56,K56" "0,1" newline bitfld.long 0x18 23. "K55,K55" "0,1" bitfld.long 0x18 22. "K54,K54" "0,1" bitfld.long 0x18 21. "K53,K53" "0,1" bitfld.long 0x18 20. "K52,K52" "0,1" newline bitfld.long 0x18 19. "K51,K51" "0,1" bitfld.long 0x18 18. "K50,K50" "0,1" bitfld.long 0x18 17. "K49,K49" "0,1" bitfld.long 0x18 16. "K48,K48" "0,1" newline bitfld.long 0x18 15. "K47,K47" "0,1" bitfld.long 0x18 14. "K46,K46" "0,1" bitfld.long 0x18 13. "K45,K45" "0,1" bitfld.long 0x18 12. "K44,K44" "0,1" newline bitfld.long 0x18 11. "K43,K43" "0,1" bitfld.long 0x18 10. "K42,K42" "0,1" bitfld.long 0x18 9. "K41,K41" "0,1" bitfld.long 0x18 8. "K40,K40" "0,1" newline bitfld.long 0x18 7. "K39,K39" "0,1" bitfld.long 0x18 6. "K38,K38" "0,1" bitfld.long 0x18 5. "K37,K37" "0,1" bitfld.long 0x18 4. "K36,K36" "0,1" newline bitfld.long 0x18 3. "K35,K35" "0,1" bitfld.long 0x18 2. "K34,K34" "0,1" bitfld.long 0x18 1. "K33,K33" "0,1" bitfld.long 0x18 0. "K32,K32" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 31. "b63,b63" "0,1" bitfld.long 0x18 30. "b62,b62" "0,1" bitfld.long 0x18 29. "b61,b61" "0,1" bitfld.long 0x18 28. "b60,b60" "0,1" newline bitfld.long 0x18 27. "b59,b59" "0,1" bitfld.long 0x18 26. "b58,b58" "0,1" bitfld.long 0x18 25. "b57,b57" "0,1" bitfld.long 0x18 24. "b56,b56" "0,1" newline bitfld.long 0x18 23. "b55,b55" "0,1" bitfld.long 0x18 22. "b54,b54" "0,1" bitfld.long 0x18 21. "b53,b53" "0,1" bitfld.long 0x18 20. "b52,b52" "0,1" newline bitfld.long 0x18 19. "b51,b51" "0,1" bitfld.long 0x18 18. "b50,b50" "0,1" bitfld.long 0x18 17. "b49,b49" "0,1" bitfld.long 0x18 16. "b48,b48" "0,1" newline bitfld.long 0x18 15. "b47,b47" "0,1" bitfld.long 0x18 14. "b46,b46" "0,1" bitfld.long 0x18 13. "b45,b45" "0,1" bitfld.long 0x18 12. "b44,b44" "0,1" newline bitfld.long 0x18 11. "b43,b43" "0,1" bitfld.long 0x18 10. "b42,b42" "0,1" bitfld.long 0x18 9. "b41,b41" "0,1" bitfld.long 0x18 8. "b40,b40" "0,1" newline bitfld.long 0x18 7. "b39,b39" "0,1" bitfld.long 0x18 6. "b38,b38" "0,1" bitfld.long 0x18 5. "b37,b37" "0,1" bitfld.long 0x18 4. "b36,b36" "0,1" newline bitfld.long 0x18 3. "b35,b35" "0,1" bitfld.long 0x18 2. "b34,b34" "0,1" bitfld.long 0x18 1. "b33,b33" "0,1" bitfld.long 0x18 0. "b32,b32" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 31. "b63,b63" "0,1" bitfld.long 0x18 30. "b62,b62" "0,1" bitfld.long 0x18 29. "b61,b61" "0,1" bitfld.long 0x18 28. "b60,b60" "0,1" newline bitfld.long 0x18 27. "b59,b59" "0,1" bitfld.long 0x18 26. "b58,b58" "0,1" bitfld.long 0x18 25. "b57,b57" "0,1" bitfld.long 0x18 24. "b56,b56" "0,1" newline bitfld.long 0x18 23. "b55,b55" "0,1" bitfld.long 0x18 22. "b54,b54" "0,1" bitfld.long 0x18 21. "b53,b53" "0,1" bitfld.long 0x18 20. "b52,b52" "0,1" newline bitfld.long 0x18 19. "b51,b51" "0,1" bitfld.long 0x18 18. "b50,b50" "0,1" bitfld.long 0x18 17. "b49,b49" "0,1" bitfld.long 0x18 16. "b48,b48" "0,1" newline bitfld.long 0x18 15. "b47,b47" "0,1" bitfld.long 0x18 14. "b46,b46" "0,1" bitfld.long 0x18 13. "b45,b45" "0,1" bitfld.long 0x18 12. "b44,b44" "0,1" newline bitfld.long 0x18 11. "b43,b43" "0,1" bitfld.long 0x18 10. "b42,b42" "0,1" bitfld.long 0x18 9. "b41,b41" "0,1" bitfld.long 0x18 8. "b40,b40" "0,1" newline bitfld.long 0x18 7. "b39,b39" "0,1" bitfld.long 0x18 6. "b38,b38" "0,1" bitfld.long 0x18 5. "b37,b37" "0,1" bitfld.long 0x18 4. "b36,b36" "0,1" newline bitfld.long 0x18 3. "b35,b35" "0,1" bitfld.long 0x18 2. "b34,b34" "0,1" bitfld.long 0x18 1. "b33,b33" "0,1" bitfld.long 0x18 0. "b32,b32" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 31. "b63,b63" "0,1" bitfld.long 0x18 30. "b62,b62" "0,1" bitfld.long 0x18 29. "b61,b61" "0,1" bitfld.long 0x18 28. "b60,b60" "0,1" newline bitfld.long 0x18 27. "b59,b59" "0,1" bitfld.long 0x18 26. "b58,b58" "0,1" bitfld.long 0x18 25. "b57,b57" "0,1" bitfld.long 0x18 24. "b56,b56" "0,1" newline bitfld.long 0x18 23. "b55,b55" "0,1" bitfld.long 0x18 22. "b54,b54" "0,1" bitfld.long 0x18 21. "b53,b53" "0,1" bitfld.long 0x18 20. "b52,b52" "0,1" newline bitfld.long 0x18 19. "b51,b51" "0,1" bitfld.long 0x18 18. "b50,b50" "0,1" bitfld.long 0x18 17. "b49,b49" "0,1" bitfld.long 0x18 16. "b48,b48" "0,1" newline bitfld.long 0x18 15. "b47,b47" "0,1" bitfld.long 0x18 14. "b46,b46" "0,1" bitfld.long 0x18 13. "b45,b45" "0,1" bitfld.long 0x18 12. "b44,b44" "0,1" newline bitfld.long 0x18 11. "b43,b43" "0,1" bitfld.long 0x18 10. "b42,b42" "0,1" bitfld.long 0x18 9. "b41,b41" "0,1" bitfld.long 0x18 8. "b40,b40" "0,1" newline bitfld.long 0x18 7. "b39,b39" "0,1" bitfld.long 0x18 6. "b38,b38" "0,1" bitfld.long 0x18 5. "b37,b37" "0,1" bitfld.long 0x18 4. "b36,b36" "0,1" newline bitfld.long 0x18 3. "b35,b35" "0,1" bitfld.long 0x18 2. "b34,b34" "0,1" bitfld.long 0x18 1. "b33,b33" "0,1" bitfld.long 0x18 0. "b32,b32" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 31. "b63,b63" "0,1" bitfld.long 0x18 30. "b62,b62" "0,1" bitfld.long 0x18 29. "b61,b61" "0,1" bitfld.long 0x18 28. "b60,b60" "0,1" newline bitfld.long 0x18 27. "b59,b59" "0,1" bitfld.long 0x18 26. "b58,b58" "0,1" bitfld.long 0x18 25. "b57,b57" "0,1" bitfld.long 0x18 24. "b56,b56" "0,1" newline bitfld.long 0x18 23. "b55,b55" "0,1" bitfld.long 0x18 22. "b54,b54" "0,1" bitfld.long 0x18 21. "b53,b53" "0,1" bitfld.long 0x18 20. "b52,b52" "0,1" newline bitfld.long 0x18 19. "b51,b51" "0,1" bitfld.long 0x18 18. "b50,b50" "0,1" bitfld.long 0x18 17. "b49,b49" "0,1" bitfld.long 0x18 16. "b48,b48" "0,1" newline bitfld.long 0x18 15. "b47,b47" "0,1" bitfld.long 0x18 14. "b46,b46" "0,1" bitfld.long 0x18 13. "b45,b45" "0,1" bitfld.long 0x18 12. "b44,b44" "0,1" newline bitfld.long 0x18 11. "b43,b43" "0,1" bitfld.long 0x18 10. "b42,b42" "0,1" bitfld.long 0x18 9. "b41,b41" "0,1" bitfld.long 0x18 8. "b40,b40" "0,1" newline bitfld.long 0x18 7. "b39,b39" "0,1" bitfld.long 0x18 6. "b38,b38" "0,1" bitfld.long 0x18 5. "b37,b37" "0,1" bitfld.long 0x18 4. "b36,b36" "0,1" newline bitfld.long 0x18 3. "b35,b35" "0,1" bitfld.long 0x18 2. "b34,b34" "0,1" bitfld.long 0x18 1. "b33,b33" "0,1" bitfld.long 0x18 0. "b32,b32" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x18 31. "b63,b63" "0,1" bitfld.long 0x18 30. "b62,b62" "0,1" bitfld.long 0x18 29. "b61,b61" "0,1" bitfld.long 0x18 28. "b60,b60" "0,1" newline bitfld.long 0x18 27. "b59,b59" "0,1" bitfld.long 0x18 26. "b58,b58" "0,1" bitfld.long 0x18 25. "b57,b57" "0,1" bitfld.long 0x18 24. "b56,b56" "0,1" newline bitfld.long 0x18 23. "b55,b55" "0,1" bitfld.long 0x18 22. "b54,b54" "0,1" bitfld.long 0x18 21. "b53,b53" "0,1" bitfld.long 0x18 20. "b52,b52" "0,1" newline bitfld.long 0x18 19. "b51,b51" "0,1" bitfld.long 0x18 18. "b50,b50" "0,1" bitfld.long 0x18 17. "b49,b49" "0,1" bitfld.long 0x18 16. "b48,b48" "0,1" newline bitfld.long 0x18 15. "b47,b47" "0,1" bitfld.long 0x18 14. "b46,b46" "0,1" bitfld.long 0x18 13. "b45,b45" "0,1" bitfld.long 0x18 12. "b44,b44" "0,1" newline bitfld.long 0x18 11. "b43,b43" "0,1" bitfld.long 0x18 10. "b42,b42" "0,1" bitfld.long 0x18 9. "b41,b41" "0,1" bitfld.long 0x18 8. "b40,b40" "0,1" newline bitfld.long 0x18 7. "b39,b39" "0,1" bitfld.long 0x18 6. "b38,b38" "0,1" bitfld.long 0x18 5. "b37,b37" "0,1" bitfld.long 0x18 4. "b36,b36" "0,1" newline bitfld.long 0x18 3. "b35,b35" "0,1" bitfld.long 0x18 2. "b34,b34" "0,1" bitfld.long 0x18 1. "b33,b33" "0,1" bitfld.long 0x18 0. "b32,b32" "0,1" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0x18 31. "b63,b63" "0,1" bitfld.long 0x18 30. "b62,b62" "0,1" bitfld.long 0x18 29. "b61,b61" "0,1" bitfld.long 0x18 28. "b60,b60" "0,1" newline bitfld.long 0x18 27. "b59,b59" "0,1" bitfld.long 0x18 26. "b58,b58" "0,1" bitfld.long 0x18 25. "b57,b57" "0,1" bitfld.long 0x18 24. "b56,b56" "0,1" newline bitfld.long 0x18 23. "b55,b55" "0,1" bitfld.long 0x18 22. "b54,b54" "0,1" bitfld.long 0x18 21. "b53,b53" "0,1" bitfld.long 0x18 20. "b52,b52" "0,1" newline bitfld.long 0x18 19. "b51,b51" "0,1" bitfld.long 0x18 18. "b50,b50" "0,1" bitfld.long 0x18 17. "b49,b49" "0,1" bitfld.long 0x18 16. "b48,b48" "0,1" newline bitfld.long 0x18 15. "b47,b47" "0,1" bitfld.long 0x18 14. "b46,b46" "0,1" bitfld.long 0x18 13. "b45,b45" "0,1" bitfld.long 0x18 12. "b44,b44" "0,1" newline bitfld.long 0x18 11. "b43,b43" "0,1" bitfld.long 0x18 10. "b42,b42" "0,1" bitfld.long 0x18 9. "b41,b41" "0,1" bitfld.long 0x18 8. "b40,b40" "0,1" newline bitfld.long 0x18 7. "b39,b39" "0,1" bitfld.long 0x18 6. "b38,b38" "0,1" bitfld.long 0x18 5. "b37,b37" "0,1" bitfld.long 0x18 4. "b36,b36" "0,1" newline bitfld.long 0x18 3. "b35,b35" "0,1" bitfld.long 0x18 2. "b34,b34" "0,1" bitfld.long 0x18 1. "b33,b33" "0,1" bitfld.long 0x18 0. "b32,b32" "0,1" endif line.long 0x1C "K3RR,key registers" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x1C 31. "k31,k31" "0,1" bitfld.long 0x1C 30. "k30,k30" "0,1" bitfld.long 0x1C 29. "k29,k29" "0,1" bitfld.long 0x1C 28. "k28,k28" "0,1" newline bitfld.long 0x1C 27. "k27,k27" "0,1" bitfld.long 0x1C 26. "k26,k26" "0,1" bitfld.long 0x1C 25. "k25,k25" "0,1" bitfld.long 0x1C 24. "k24,k24" "0,1" newline bitfld.long 0x1C 23. "k23,k23" "0,1" bitfld.long 0x1C 22. "k22,k22" "0,1" bitfld.long 0x1C 21. "k21,k21" "0,1" bitfld.long 0x1C 20. "k20,k20" "0,1" newline bitfld.long 0x1C 19. "k19,k19" "0,1" bitfld.long 0x1C 18. "k18,k18" "0,1" bitfld.long 0x1C 17. "k17,k17" "0,1" bitfld.long 0x1C 16. "k16,k16" "0,1" newline bitfld.long 0x1C 15. "k15,k15" "0,1" bitfld.long 0x1C 14. "k14,k14" "0,1" bitfld.long 0x1C 13. "k13,k13" "0,1" bitfld.long 0x1C 12. "k12,k12" "0,1" newline bitfld.long 0x1C 11. "k11,k11" "0,1" bitfld.long 0x1C 10. "k10,k10" "0,1" bitfld.long 0x1C 9. "k9,k9" "0,1" bitfld.long 0x1C 8. "k8,k8" "0,1" newline bitfld.long 0x1C 7. "k7,k7" "0,1" bitfld.long 0x1C 6. "k6,k6" "0,1" bitfld.long 0x1C 5. "k5,k5" "0,1" bitfld.long 0x1C 4. "k4,k4" "0,1" newline bitfld.long 0x1C 3. "k3,k3" "0,1" bitfld.long 0x1C 2. "k2,k2" "0,1" bitfld.long 0x1C 1. "k1,k1" "0,1" bitfld.long 0x1C 0. "k0,k0" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 31. "b31,b31" "0,1" bitfld.long 0x1C 30. "b30,b30" "0,1" bitfld.long 0x1C 29. "b29,b29" "0,1" bitfld.long 0x1C 28. "b28,b28" "0,1" newline bitfld.long 0x1C 27. "b27,b27" "0,1" bitfld.long 0x1C 26. "b26,b26" "0,1" bitfld.long 0x1C 25. "b25,b25" "0,1" bitfld.long 0x1C 24. "b24,b24" "0,1" newline bitfld.long 0x1C 23. "b23,b23" "0,1" bitfld.long 0x1C 22. "b22,b22" "0,1" bitfld.long 0x1C 21. "b21,b21" "0,1" bitfld.long 0x1C 20. "b20,b20" "0,1" newline bitfld.long 0x1C 19. "b19,b19" "0,1" bitfld.long 0x1C 18. "b18,b18" "0,1" bitfld.long 0x1C 17. "b17,b17" "0,1" bitfld.long 0x1C 16. "b16,b16" "0,1" newline bitfld.long 0x1C 15. "b15,b15" "0,1" bitfld.long 0x1C 14. "b14,b14" "0,1" bitfld.long 0x1C 13. "b13,b13" "0,1" bitfld.long 0x1C 12. "b12,b12" "0,1" newline bitfld.long 0x1C 11. "b11,b11" "0,1" bitfld.long 0x1C 10. "b10,b10" "0,1" bitfld.long 0x1C 9. "b9,b9" "0,1" bitfld.long 0x1C 8. "b8,b8" "0,1" newline bitfld.long 0x1C 7. "b7,b7" "0,1" bitfld.long 0x1C 6. "b6,b6" "0,1" bitfld.long 0x1C 5. "b5,b5" "0,1" bitfld.long 0x1C 4. "b4,b4" "0,1" newline bitfld.long 0x1C 3. "b3,b3" "0,1" bitfld.long 0x1C 2. "b2,b2" "0,1" bitfld.long 0x1C 1. "b1,b1" "0,1" bitfld.long 0x1C 0. "b0,b0" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 31. "K31,K31" "0,1" bitfld.long 0x1C 30. "K30,K30" "0,1" bitfld.long 0x1C 29. "K29,K29" "0,1" bitfld.long 0x1C 28. "K28,K28" "0,1" newline bitfld.long 0x1C 27. "K27,K27" "0,1" bitfld.long 0x1C 26. "K26,K26" "0,1" bitfld.long 0x1C 25. "K25,K25" "0,1" bitfld.long 0x1C 24. "K24,K24" "0,1" newline bitfld.long 0x1C 23. "K23,K23" "0,1" bitfld.long 0x1C 22. "K22,K22" "0,1" bitfld.long 0x1C 21. "K21,K21" "0,1" bitfld.long 0x1C 20. "K20,K20" "0,1" newline bitfld.long 0x1C 19. "K19,K19" "0,1" bitfld.long 0x1C 18. "K18,K18" "0,1" bitfld.long 0x1C 17. "K17,K17" "0,1" bitfld.long 0x1C 16. "K16,K16" "0,1" newline bitfld.long 0x1C 15. "K15,K15" "0,1" bitfld.long 0x1C 14. "K14,K14" "0,1" bitfld.long 0x1C 13. "K13,K13" "0,1" bitfld.long 0x1C 12. "K12,K12" "0,1" newline bitfld.long 0x1C 11. "K11,K11" "0,1" bitfld.long 0x1C 10. "K10,K10" "0,1" bitfld.long 0x1C 9. "K9,K9" "0,1" bitfld.long 0x1C 8. "K8,K8" "0,1" newline bitfld.long 0x1C 7. "K7,K7" "0,1" bitfld.long 0x1C 6. "K6,K6" "0,1" bitfld.long 0x1C 5. "K5,K5" "0,1" bitfld.long 0x1C 4. "K4,K4" "0,1" newline bitfld.long 0x1C 3. "K3,K3" "0,1" bitfld.long 0x1C 2. "K2,K2" "0,1" bitfld.long 0x1C 1. "K1,K1" "0,1" bitfld.long 0x1C 0. "K0,K0" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 31. "b31,b31" "0,1" bitfld.long 0x1C 30. "b30,b30" "0,1" bitfld.long 0x1C 29. "b29,b29" "0,1" bitfld.long 0x1C 28. "b28,b28" "0,1" newline bitfld.long 0x1C 27. "b27,b27" "0,1" bitfld.long 0x1C 26. "b26,b26" "0,1" bitfld.long 0x1C 25. "b25,b25" "0,1" bitfld.long 0x1C 24. "b24,b24" "0,1" newline bitfld.long 0x1C 23. "b23,b23" "0,1" bitfld.long 0x1C 22. "b22,b22" "0,1" bitfld.long 0x1C 21. "b21,b21" "0,1" bitfld.long 0x1C 20. "b20,b20" "0,1" newline bitfld.long 0x1C 19. "b19,b19" "0,1" bitfld.long 0x1C 18. "b18,b18" "0,1" bitfld.long 0x1C 17. "b17,b17" "0,1" bitfld.long 0x1C 16. "b16,b16" "0,1" newline bitfld.long 0x1C 15. "b15,b15" "0,1" bitfld.long 0x1C 14. "b14,b14" "0,1" bitfld.long 0x1C 13. "b13,b13" "0,1" bitfld.long 0x1C 12. "b12,b12" "0,1" newline bitfld.long 0x1C 11. "b11,b11" "0,1" bitfld.long 0x1C 10. "b10,b10" "0,1" bitfld.long 0x1C 9. "b9,b9" "0,1" bitfld.long 0x1C 8. "b8,b8" "0,1" newline bitfld.long 0x1C 7. "b7,b7" "0,1" bitfld.long 0x1C 6. "b6,b6" "0,1" bitfld.long 0x1C 5. "b5,b5" "0,1" bitfld.long 0x1C 4. "b4,b4" "0,1" newline bitfld.long 0x1C 3. "b3,b3" "0,1" bitfld.long 0x1C 2. "b2,b2" "0,1" bitfld.long 0x1C 1. "b1,b1" "0,1" bitfld.long 0x1C 0. "b0,b0" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 31. "b31,b31" "0,1" bitfld.long 0x1C 30. "b30,b30" "0,1" bitfld.long 0x1C 29. "b29,b29" "0,1" bitfld.long 0x1C 28. "b28,b28" "0,1" newline bitfld.long 0x1C 27. "b27,b27" "0,1" bitfld.long 0x1C 26. "b26,b26" "0,1" bitfld.long 0x1C 25. "b25,b25" "0,1" bitfld.long 0x1C 24. "b24,b24" "0,1" newline bitfld.long 0x1C 23. "b23,b23" "0,1" bitfld.long 0x1C 22. "b22,b22" "0,1" bitfld.long 0x1C 21. "b21,b21" "0,1" bitfld.long 0x1C 20. "b20,b20" "0,1" newline bitfld.long 0x1C 19. "b19,b19" "0,1" bitfld.long 0x1C 18. "b18,b18" "0,1" bitfld.long 0x1C 17. "b17,b17" "0,1" bitfld.long 0x1C 16. "b16,b16" "0,1" newline bitfld.long 0x1C 15. "b15,b15" "0,1" bitfld.long 0x1C 14. "b14,b14" "0,1" bitfld.long 0x1C 13. "b13,b13" "0,1" bitfld.long 0x1C 12. "b12,b12" "0,1" newline bitfld.long 0x1C 11. "b11,b11" "0,1" bitfld.long 0x1C 10. "b10,b10" "0,1" bitfld.long 0x1C 9. "b9,b9" "0,1" bitfld.long 0x1C 8. "b8,b8" "0,1" newline bitfld.long 0x1C 7. "b7,b7" "0,1" bitfld.long 0x1C 6. "b6,b6" "0,1" bitfld.long 0x1C 5. "b5,b5" "0,1" bitfld.long 0x1C 4. "b4,b4" "0,1" newline bitfld.long 0x1C 3. "b3,b3" "0,1" bitfld.long 0x1C 2. "b2,b2" "0,1" bitfld.long 0x1C 1. "b1,b1" "0,1" bitfld.long 0x1C 0. "b0,b0" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 31. "b31,b31" "0,1" bitfld.long 0x1C 30. "b30,b30" "0,1" bitfld.long 0x1C 29. "b29,b29" "0,1" bitfld.long 0x1C 28. "b28,b28" "0,1" newline bitfld.long 0x1C 27. "b27,b27" "0,1" bitfld.long 0x1C 26. "b26,b26" "0,1" bitfld.long 0x1C 25. "b25,b25" "0,1" bitfld.long 0x1C 24. "b24,b24" "0,1" newline bitfld.long 0x1C 23. "b23,b23" "0,1" bitfld.long 0x1C 22. "b22,b22" "0,1" bitfld.long 0x1C 21. "b21,b21" "0,1" bitfld.long 0x1C 20. "b20,b20" "0,1" newline bitfld.long 0x1C 19. "b19,b19" "0,1" bitfld.long 0x1C 18. "b18,b18" "0,1" bitfld.long 0x1C 17. "b17,b17" "0,1" bitfld.long 0x1C 16. "b16,b16" "0,1" newline bitfld.long 0x1C 15. "b15,b15" "0,1" bitfld.long 0x1C 14. "b14,b14" "0,1" bitfld.long 0x1C 13. "b13,b13" "0,1" bitfld.long 0x1C 12. "b12,b12" "0,1" newline bitfld.long 0x1C 11. "b11,b11" "0,1" bitfld.long 0x1C 10. "b10,b10" "0,1" bitfld.long 0x1C 9. "b9,b9" "0,1" bitfld.long 0x1C 8. "b8,b8" "0,1" newline bitfld.long 0x1C 7. "b7,b7" "0,1" bitfld.long 0x1C 6. "b6,b6" "0,1" bitfld.long 0x1C 5. "b5,b5" "0,1" bitfld.long 0x1C 4. "b4,b4" "0,1" newline bitfld.long 0x1C 3. "b3,b3" "0,1" bitfld.long 0x1C 2. "b2,b2" "0,1" bitfld.long 0x1C 1. "b1,b1" "0,1" bitfld.long 0x1C 0. "b0,b0" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 31. "b31,b31" "0,1" bitfld.long 0x1C 30. "b30,b30" "0,1" bitfld.long 0x1C 29. "b29,b29" "0,1" bitfld.long 0x1C 28. "b28,b28" "0,1" newline bitfld.long 0x1C 27. "b27,b27" "0,1" bitfld.long 0x1C 26. "b26,b26" "0,1" bitfld.long 0x1C 25. "b25,b25" "0,1" bitfld.long 0x1C 24. "b24,b24" "0,1" newline bitfld.long 0x1C 23. "b23,b23" "0,1" bitfld.long 0x1C 22. "b22,b22" "0,1" bitfld.long 0x1C 21. "b21,b21" "0,1" bitfld.long 0x1C 20. "b20,b20" "0,1" newline bitfld.long 0x1C 19. "b19,b19" "0,1" bitfld.long 0x1C 18. "b18,b18" "0,1" bitfld.long 0x1C 17. "b17,b17" "0,1" bitfld.long 0x1C 16. "b16,b16" "0,1" newline bitfld.long 0x1C 15. "b15,b15" "0,1" bitfld.long 0x1C 14. "b14,b14" "0,1" bitfld.long 0x1C 13. "b13,b13" "0,1" bitfld.long 0x1C 12. "b12,b12" "0,1" newline bitfld.long 0x1C 11. "b11,b11" "0,1" bitfld.long 0x1C 10. "b10,b10" "0,1" bitfld.long 0x1C 9. "b9,b9" "0,1" bitfld.long 0x1C 8. "b8,b8" "0,1" newline bitfld.long 0x1C 7. "b7,b7" "0,1" bitfld.long 0x1C 6. "b6,b6" "0,1" bitfld.long 0x1C 5. "b5,b5" "0,1" bitfld.long 0x1C 4. "b4,b4" "0,1" newline bitfld.long 0x1C 3. "b3,b3" "0,1" bitfld.long 0x1C 2. "b2,b2" "0,1" bitfld.long 0x1C 1. "b1,b1" "0,1" bitfld.long 0x1C 0. "b0,b0" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x1C 31. "b31,b31" "0,1" bitfld.long 0x1C 30. "b30,b30" "0,1" bitfld.long 0x1C 29. "b29,b29" "0,1" bitfld.long 0x1C 28. "b28,b28" "0,1" newline bitfld.long 0x1C 27. "b27,b27" "0,1" bitfld.long 0x1C 26. "b26,b26" "0,1" bitfld.long 0x1C 25. "b25,b25" "0,1" bitfld.long 0x1C 24. "b24,b24" "0,1" newline bitfld.long 0x1C 23. "b23,b23" "0,1" bitfld.long 0x1C 22. "b22,b22" "0,1" bitfld.long 0x1C 21. "b21,b21" "0,1" bitfld.long 0x1C 20. "b20,b20" "0,1" newline bitfld.long 0x1C 19. "b19,b19" "0,1" bitfld.long 0x1C 18. "b18,b18" "0,1" bitfld.long 0x1C 17. "b17,b17" "0,1" bitfld.long 0x1C 16. "b16,b16" "0,1" newline bitfld.long 0x1C 15. "b15,b15" "0,1" bitfld.long 0x1C 14. "b14,b14" "0,1" bitfld.long 0x1C 13. "b13,b13" "0,1" bitfld.long 0x1C 12. "b12,b12" "0,1" newline bitfld.long 0x1C 11. "b11,b11" "0,1" bitfld.long 0x1C 10. "b10,b10" "0,1" bitfld.long 0x1C 9. "b9,b9" "0,1" bitfld.long 0x1C 8. "b8,b8" "0,1" newline bitfld.long 0x1C 7. "b7,b7" "0,1" bitfld.long 0x1C 6. "b6,b6" "0,1" bitfld.long 0x1C 5. "b5,b5" "0,1" bitfld.long 0x1C 4. "b4,b4" "0,1" newline bitfld.long 0x1C 3. "b3,b3" "0,1" bitfld.long 0x1C 2. "b2,b2" "0,1" bitfld.long 0x1C 1. "b1,b1" "0,1" bitfld.long 0x1C 0. "b0,b0" "0,1" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0x1C 31. "b31,b31" "0,1" bitfld.long 0x1C 30. "b30,b30" "0,1" bitfld.long 0x1C 29. "b29,b29" "0,1" bitfld.long 0x1C 28. "b28,b28" "0,1" newline bitfld.long 0x1C 27. "b27,b27" "0,1" bitfld.long 0x1C 26. "b26,b26" "0,1" bitfld.long 0x1C 25. "b25,b25" "0,1" bitfld.long 0x1C 24. "b24,b24" "0,1" newline bitfld.long 0x1C 23. "b23,b23" "0,1" bitfld.long 0x1C 22. "b22,b22" "0,1" bitfld.long 0x1C 21. "b21,b21" "0,1" bitfld.long 0x1C 20. "b20,b20" "0,1" newline bitfld.long 0x1C 19. "b19,b19" "0,1" bitfld.long 0x1C 18. "b18,b18" "0,1" bitfld.long 0x1C 17. "b17,b17" "0,1" bitfld.long 0x1C 16. "b16,b16" "0,1" newline bitfld.long 0x1C 15. "b15,b15" "0,1" bitfld.long 0x1C 14. "b14,b14" "0,1" bitfld.long 0x1C 13. "b13,b13" "0,1" bitfld.long 0x1C 12. "b12,b12" "0,1" newline bitfld.long 0x1C 11. "b11,b11" "0,1" bitfld.long 0x1C 10. "b10,b10" "0,1" bitfld.long 0x1C 9. "b9,b9" "0,1" bitfld.long 0x1C 8. "b8,b8" "0,1" newline bitfld.long 0x1C 7. "b7,b7" "0,1" bitfld.long 0x1C 6. "b6,b6" "0,1" bitfld.long 0x1C 5. "b5,b5" "0,1" bitfld.long 0x1C 4. "b4,b4" "0,1" newline bitfld.long 0x1C 3. "b3,b3" "0,1" bitfld.long 0x1C 2. "b2,b2" "0,1" bitfld.long 0x1C 1. "b1,b1" "0,1" bitfld.long 0x1C 0. "b0,b0" "0,1" endif group.long 0x40++0x4F line.long 0x0 "IV0LR,Initialization vector register 0L" bitfld.long 0x0 31. "IV0,IV0" "0,1" bitfld.long 0x0 30. "IV1,IV1" "0,1" bitfld.long 0x0 29. "IV2,IV2" "0,1" bitfld.long 0x0 28. "IV3,IV3" "0,1" newline bitfld.long 0x0 27. "IV4,IV4" "0,1" bitfld.long 0x0 26. "IV5,IV5" "0,1" bitfld.long 0x0 25. "IV6,IV6" "0,1" bitfld.long 0x0 24. "IV7,IV7" "0,1" newline bitfld.long 0x0 23. "IV8,IV8" "0,1" bitfld.long 0x0 22. "IV9,IV9" "0,1" bitfld.long 0x0 21. "IV10,IV10" "0,1" bitfld.long 0x0 20. "IV11,IV11" "0,1" newline bitfld.long 0x0 19. "IV12,IV12" "0,1" bitfld.long 0x0 18. "IV13,IV13" "0,1" bitfld.long 0x0 17. "IV14,IV14" "0,1" bitfld.long 0x0 16. "IV15,IV15" "0,1" newline bitfld.long 0x0 15. "IV16,IV16" "0,1" bitfld.long 0x0 14. "IV17,IV17" "0,1" bitfld.long 0x0 13. "IV18,IV18" "0,1" bitfld.long 0x0 12. "IV19,IV19" "0,1" newline bitfld.long 0x0 11. "IV20,IV20" "0,1" bitfld.long 0x0 10. "IV21,IV21" "0,1" bitfld.long 0x0 9. "IV22,IV22" "0,1" bitfld.long 0x0 8. "IV23,IV23" "0,1" newline bitfld.long 0x0 7. "IV24,IV24" "0,1" bitfld.long 0x0 6. "IV25,IV25" "0,1" bitfld.long 0x0 5. "IV26,IV26" "0,1" bitfld.long 0x0 4. "IV27,IV27" "0,1" newline bitfld.long 0x0 3. "IV28,IV28" "0,1" bitfld.long 0x0 2. "IV29,IV29" "0,1" bitfld.long 0x0 1. "IV30,IV30" "0,1" bitfld.long 0x0 0. "IV31,IV31" "0,1" line.long 0x4 "IV0RR,initialization vector register 0R" bitfld.long 0x4 31. "IV32,IV32" "0,1" bitfld.long 0x4 30. "IV33,IV33" "0,1" bitfld.long 0x4 29. "IV34,IV34" "0,1" bitfld.long 0x4 28. "IV35,IV35" "0,1" newline bitfld.long 0x4 27. "IV36,IV36" "0,1" bitfld.long 0x4 26. "IV37,IV37" "0,1" bitfld.long 0x4 25. "IV38,IV38" "0,1" bitfld.long 0x4 24. "IV39,IV39" "0,1" newline bitfld.long 0x4 23. "IV40,IV40" "0,1" bitfld.long 0x4 22. "IV41,IV41" "0,1" bitfld.long 0x4 21. "IV42,IV42" "0,1" bitfld.long 0x4 20. "IV43,IV43" "0,1" newline bitfld.long 0x4 19. "IV44,IV44" "0,1" bitfld.long 0x4 18. "IV45,IV45" "0,1" bitfld.long 0x4 17. "IV46,IV46" "0,1" bitfld.long 0x4 16. "IV47,IV47" "0,1" newline bitfld.long 0x4 15. "IV48,IV48" "0,1" bitfld.long 0x4 14. "IV49,IV49" "0,1" bitfld.long 0x4 13. "IV50,IV50" "0,1" bitfld.long 0x4 12. "IV51,IV51" "0,1" newline bitfld.long 0x4 11. "IV52,IV52" "0,1" bitfld.long 0x4 10. "IV53,IV53" "0,1" bitfld.long 0x4 9. "IV54,IV54" "0,1" bitfld.long 0x4 8. "IV55,IV55" "0,1" newline bitfld.long 0x4 7. "IV56,IV56" "0,1" bitfld.long 0x4 6. "IV57,IV57" "0,1" bitfld.long 0x4 5. "IV58,IV58" "0,1" bitfld.long 0x4 4. "IV59,IV59" "0,1" newline bitfld.long 0x4 3. "IV60,IV60" "0,1" bitfld.long 0x4 2. "IV61,IV61" "0,1" bitfld.long 0x4 1. "IV62,IV62" "0,1" bitfld.long 0x4 0. "IV63,IV63" "0,1" line.long 0x8 "IV1LR,Initialization vector register 1L" bitfld.long 0x8 31. "IV64,IV64" "0,1" bitfld.long 0x8 30. "IV65,IV65" "0,1" bitfld.long 0x8 29. "IV66,IV66" "0,1" bitfld.long 0x8 28. "IV67,IV67" "0,1" newline bitfld.long 0x8 27. "IV68,IV68" "0,1" bitfld.long 0x8 26. "IV69,IV69" "0,1" bitfld.long 0x8 25. "IV70,IV70" "0,1" bitfld.long 0x8 24. "IV71,IV71" "0,1" newline bitfld.long 0x8 23. "IV72,IV72" "0,1" bitfld.long 0x8 22. "IV73,IV73" "0,1" bitfld.long 0x8 21. "IV74,IV74" "0,1" bitfld.long 0x8 20. "IV75,IV75" "0,1" newline bitfld.long 0x8 19. "IV76,IV76" "0,1" bitfld.long 0x8 18. "IV77,IV77" "0,1" bitfld.long 0x8 17. "IV78,IV78" "0,1" bitfld.long 0x8 16. "IV79,IV79" "0,1" newline bitfld.long 0x8 15. "IV80,IV80" "0,1" bitfld.long 0x8 14. "IV81,IV81" "0,1" bitfld.long 0x8 13. "IV82,IV82" "0,1" bitfld.long 0x8 12. "IV83,IV83" "0,1" newline bitfld.long 0x8 11. "IV84,IV84" "0,1" bitfld.long 0x8 10. "IV85,IV85" "0,1" bitfld.long 0x8 9. "IV86,IV86" "0,1" bitfld.long 0x8 8. "IV87,IV87" "0,1" newline bitfld.long 0x8 7. "IV88,IV88" "0,1" bitfld.long 0x8 6. "IV89,IV89" "0,1" bitfld.long 0x8 5. "IV90,IV90" "0,1" bitfld.long 0x8 4. "IV91,IV91" "0,1" newline bitfld.long 0x8 3. "IV92,IV92" "0,1" bitfld.long 0x8 2. "IV93,IV93" "0,1" bitfld.long 0x8 1. "IV94,IV94" "0,1" bitfld.long 0x8 0. "IV95,IV95" "0,1" line.long 0xC "IV1RR,Initialization vector register 1R" bitfld.long 0xC 31. "IV96,IV96" "0,1" bitfld.long 0xC 30. "IV97,IV97" "0,1" bitfld.long 0xC 29. "IV98,IV98" "0,1" bitfld.long 0xC 28. "IV99,IV99" "0,1" newline bitfld.long 0xC 27. "IV100,IV100" "0,1" bitfld.long 0xC 26. "IV101,IV101" "0,1" bitfld.long 0xC 25. "IV102,IV102" "0,1" bitfld.long 0xC 24. "IV103,IV103" "0,1" newline bitfld.long 0xC 23. "IV104,IV104" "0,1" bitfld.long 0xC 22. "IV105,IV105" "0,1" bitfld.long 0xC 21. "IV106,IV106" "0,1" bitfld.long 0xC 20. "IV107,IV107" "0,1" newline bitfld.long 0xC 19. "IV108,IV108" "0,1" bitfld.long 0xC 18. "IV109,IV109" "0,1" bitfld.long 0xC 17. "IV110,IV110" "0,1" bitfld.long 0xC 16. "IV111,IV111" "0,1" newline bitfld.long 0xC 15. "IV112,IV112" "0,1" bitfld.long 0xC 14. "IV113,IV113" "0,1" bitfld.long 0xC 13. "IV114,IV114" "0,1" bitfld.long 0xC 12. "IV115,IV115" "0,1" newline bitfld.long 0xC 11. "IV116,IV116" "0,1" bitfld.long 0xC 10. "IV117,IV117" "0,1" bitfld.long 0xC 9. "IV118,IV118" "0,1" bitfld.long 0xC 8. "IV119,IV119" "0,1" newline bitfld.long 0xC 7. "IV120,IV120" "0,1" bitfld.long 0xC 6. "IV121,IV121" "0,1" bitfld.long 0xC 5. "IV122,IV122" "0,1" bitfld.long 0xC 4. "IV123,IV123" "0,1" newline bitfld.long 0xC 3. "IV124,IV124" "0,1" bitfld.long 0xC 2. "IV125,IV125" "0,1" bitfld.long 0xC 1. "IV126,IV126" "0,1" bitfld.long 0xC 0. "IV127,IV127" "0,1" line.long 0x10 "CSGCMCCM0R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0R,CSGCMCCM0R" endif sif (cpuis("STM32H753*")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0,CSGCMCCM0" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0R,CSGCMCCM0R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0R,CSGCMCCM0R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0R,CSGCMCCM0R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0R,CSGCMCCM0R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0R,CSGCMCCM0R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x10 0.--31. 1. "CSGCMCCM0R,CSGCMCCM0R" endif line.long 0x14 "CSGCMCCM1R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1R,CSGCMCCM1R" endif sif (cpuis("STM32H753*")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1,CSGCMCCM1" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1R,CSGCMCCM1R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1R,CSGCMCCM1R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1R,CSGCMCCM1R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1R,CSGCMCCM1R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1R,CSGCMCCM1R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x14 0.--31. 1. "CSGCMCCM1R,CSGCMCCM1R" endif line.long 0x18 "CSGCMCCM2R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2R,CSGCMCCM2R" endif sif (cpuis("STM32H753*")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2,CSGCMCCM2" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2R,CSGCMCCM2R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2R,CSGCMCCM2R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2R,CSGCMCCM2R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2R,CSGCMCCM2R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2R,CSGCMCCM2R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x18 0.--31. 1. "CSGCMCCM2R,CSGCMCCM2R" endif line.long 0x1C "CSGCMCCM3R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3R,CSGCMCCM3R" endif sif (cpuis("STM32H753*")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3,CSGCMCCM3" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3R,CSGCMCCM3R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3R,CSGCMCCM3R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3R,CSGCMCCM3R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3R,CSGCMCCM3R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3R,CSGCMCCM3R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x1C 0.--31. 1. "CSGCMCCM3R,CSGCMCCM3R" endif line.long 0x20 "CSGCMCCM4R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4R,CSGCMCCM4R" endif sif (cpuis("STM32H753*")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4,CSGCMCCM4" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4R,CSGCMCCM4R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4R,CSGCMCCM4R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4R,CSGCMCCM4R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4R,CSGCMCCM4R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4R,CSGCMCCM4R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x20 0.--31. 1. "CSGCMCCM4R,CSGCMCCM4R" endif line.long 0x24 "CSGCMCCM5R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5R,CSGCMCCM5R" endif sif (cpuis("STM32H753*")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5,CSGCMCCM5" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5R,CSGCMCCM5R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5R,CSGCMCCM5R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5R,CSGCMCCM5R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5R,CSGCMCCM5R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5R,CSGCMCCM5R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x24 0.--31. 1. "CSGCMCCM5R,CSGCMCCM5R" endif line.long 0x28 "CSGCMCCM6R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6R,CSGCMCCM6R" endif sif (cpuis("STM32H753*")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6,CSGCMCCM6" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6R,CSGCMCCM6R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6R,CSGCMCCM6R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6R,CSGCMCCM6R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6R,CSGCMCCM6R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6R,CSGCMCCM6R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x28 0.--31. 1. "CSGCMCCM6R,CSGCMCCM6R" endif line.long 0x2C "CSGCMCCM7R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7R,CSGCMCCM7R" endif sif (cpuis("STM32H753*")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7,CSGCMCCM7" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7R,CSGCMCCM7R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7R,CSGCMCCM7R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7R,CSGCMCCM7R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7R,CSGCMCCM7R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7R,CSGCMCCM7R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x2C 0.--31. 1. "CSGCMCCM7R,CSGCMCCM7R" endif line.long 0x30 "CSGCM0R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x30 0.--31. 1. "CSGCM0R,CSGCM0R" endif sif (cpuis("STM32H753*")) hexmask.long 0x30 0.--31. 1. "CSGCM0,CSGCM0" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x30 0.--31. 1. "CSGCM0R,CSGCM0R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x30 0.--31. 1. "CSGCM0R,CSGCM0R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x30 0.--31. 1. "CSGCM0R,CSGCM0R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x30 0.--31. 1. "CSGCM0R,CSGCM0R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x30 0.--31. 1. "CSGCM0R,CSGCM0R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x30 0.--31. 1. "CSGCM0R,CSGCM0R" endif line.long 0x34 "CSGCM1R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x34 0.--31. 1. "CSGCM1R,CSGCM1R" endif sif (cpuis("STM32H753*")) hexmask.long 0x34 0.--31. 1. "CSGCM1,CSGCM1" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x34 0.--31. 1. "CSGCM1R,CSGCM1R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x34 0.--31. 1. "CSGCM1R,CSGCM1R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x34 0.--31. 1. "CSGCM1R,CSGCM1R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x34 0.--31. 1. "CSGCM1R,CSGCM1R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x34 0.--31. 1. "CSGCM1R,CSGCM1R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x34 0.--31. 1. "CSGCM1R,CSGCM1R" endif line.long 0x38 "CSGCM2R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x38 0.--31. 1. "CSGCM2R,CSGCM2R" endif sif (cpuis("STM32H753*")) hexmask.long 0x38 0.--31. 1. "CSGCM2,CSGCM2" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x38 0.--31. 1. "CSGCM2R,CSGCM2R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x38 0.--31. 1. "CSGCM2R,CSGCM2R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x38 0.--31. 1. "CSGCM2R,CSGCM2R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x38 0.--31. 1. "CSGCM2R,CSGCM2R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x38 0.--31. 1. "CSGCM2R,CSGCM2R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x38 0.--31. 1. "CSGCM2R,CSGCM2R" endif line.long 0x3C "CSGCM3R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x3C 0.--31. 1. "CSGCM3R,CSGCM3R" endif sif (cpuis("STM32H753*")) hexmask.long 0x3C 0.--31. 1. "CSGCM3,CSGCM3" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x3C 0.--31. 1. "CSGCM3R,CSGCM3R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x3C 0.--31. 1. "CSGCM3R,CSGCM3R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x3C 0.--31. 1. "CSGCM3R,CSGCM3R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x3C 0.--31. 1. "CSGCM3R,CSGCM3R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x3C 0.--31. 1. "CSGCM3R,CSGCM3R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x3C 0.--31. 1. "CSGCM3R,CSGCM3R" endif line.long 0x40 "CSGCM4R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x40 0.--31. 1. "CSGCM4R,CSGCM4R" endif sif (cpuis("STM32H753*")) hexmask.long 0x40 0.--31. 1. "CSGCM4,CSGCM4" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x40 0.--31. 1. "CSGCM4R,CSGCM4R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x40 0.--31. 1. "CSGCM4R,CSGCM4R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x40 0.--31. 1. "CSGCM4R,CSGCM4R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x40 0.--31. 1. "CSGCM4R,CSGCM4R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x40 0.--31. 1. "CSGCM4R,CSGCM4R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x40 0.--31. 1. "CSGCM4R,CSGCM4R" endif line.long 0x44 "CSGCM5R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x44 0.--31. 1. "CSGCM5R,CSGCM5R" endif sif (cpuis("STM32H753*")) hexmask.long 0x44 0.--31. 1. "CSGCM5,CSGCM5" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x44 0.--31. 1. "CSGCM5R,CSGCM5R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x44 0.--31. 1. "CSGCM5R,CSGCM5R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x44 0.--31. 1. "CSGCM5R,CSGCM5R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x44 0.--31. 1. "CSGCM5R,CSGCM5R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x44 0.--31. 1. "CSGCM5R,CSGCM5R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x44 0.--31. 1. "CSGCM5R,CSGCM5R" endif line.long 0x48 "CSGCM6R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x48 0.--31. 1. "CSGCM6R,CSGCM6R" endif sif (cpuis("STM32H753*")) hexmask.long 0x48 0.--31. 1. "CSGCM6,CSGCM6" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x48 0.--31. 1. "CSGCM6R,CSGCM6R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x48 0.--31. 1. "CSGCM6R,CSGCM6R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x48 0.--31. 1. "CSGCM6R,CSGCM6R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x48 0.--31. 1. "CSGCM6R,CSGCM6R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x48 0.--31. 1. "CSGCM6R,CSGCM6R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x48 0.--31. 1. "CSGCM6R,CSGCM6R" endif line.long 0x4C "CSGCM7R,context swap register" sif (cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H750*")) hexmask.long 0x4C 0.--31. 1. "CSGCM7R,CSGCM7R" endif sif (cpuis("STM32H753*")) hexmask.long 0x4C 0.--31. 1. "CSGCM7,CSGCM7" endif sif (cpuis("STM32H755??-CM4")) hexmask.long 0x4C 0.--31. 1. "CSGCM7R,CSGCM7R" endif sif (cpuis("STM32H755??-CM7")) hexmask.long 0x4C 0.--31. 1. "CSGCM7R,CSGCM7R" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long 0x4C 0.--31. 1. "CSGCM7R,CSGCM7R" endif sif (cpuis("STM32H757??-CM7")) hexmask.long 0x4C 0.--31. 1. "CSGCM7R,CSGCM7R" endif sif (cpuis("STM32H7B0*")) hexmask.long 0x4C 0.--31. 1. "CSGCM7R,CSGCM7R" endif sif (cpuis("STM32H7B3*")) hexmask.long 0x4C 0.--31. 1. "CSGCM7R,CSGCM7R" endif tree.end endif tree "DAC (Digital-to-Analog Converter)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "DAC" base ad:0x40007400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" newline bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" newline bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" newline bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" newline bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" newline bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" newline bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" newline rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" endif sif (cpuis("STM32H750*")) group.long 0x0++0x3 line.long 0x0 "DAC_CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" newline bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" newline bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" newline bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" newline bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" newline bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "DAC_SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DAC_DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DAC_DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "DAC_SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" newline bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" newline rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "DAC_CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "DAC_MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "DAC_SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" endif tree.end endif sif (cpuis("STM32H753*")) tree "DAC" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "DAC" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "DAC" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "DAC" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "DAC" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif sif (cpuis("STM32H7A3*")) tree "DAC1" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end tree "DAC2" base ad:0x58003400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 18.--20. "TSEL2,DAC channel2 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" bitfld.long 0x0 2.--4. "TSEL1,DAC channel1 trigger selection These" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif sif (cpuis("STM32H7B0*")) tree "DAC1" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" hexmask.long.byte 0x8 16.--19. 1. "MODE2,DAC Channel 2 mode These bits can be" hexmask.long.byte 0x8 0.--3. 1. "MODE1,DAC Channel 1 mode These bits can be" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end tree "DAC2" base ad:0x58003400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" hexmask.long.byte 0x8 16.--19. 1. "MODE2,DAC Channel 2 mode These bits can be" hexmask.long.byte 0x8 0.--3. 1. "MODE1,DAC Channel 1 mode These bits can be" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif sif (cpuis("STM32H7B3*")) tree "DAC1" base ad:0x40007400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" hexmask.long.byte 0x8 16.--19. 1. "MODE2,DAC Channel 2 mode These bits can be" hexmask.long.byte 0x8 0.--3. 1. "MODE1,DAC Channel 1 mode These bits can be" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end tree "DAC2" base ad:0x58003400 group.long 0x0++0x3 line.long 0x0 "CR,DAC control register" bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1" bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1" bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector" bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These" bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1" bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1" bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1" newline bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1" bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1" hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector" bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3" hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These" bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1" bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "SWTRGR,DAC software trigger register" bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1" bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1" group.long 0x8++0x23 line.long 0x0 "DHR12R1,DAC channel1 12-bit right-aligned data" hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x4 "DHR12L1,DAC channel1 12-bit left aligned data" hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x8 "DHR8R1,DAC channel1 8-bit right aligned data" hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" line.long 0xC "DHR12R2,DAC channel2 12-bit right aligned data" hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" line.long 0x10 "DHR12L2,DAC channel2 12-bit left aligned data" hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" line.long 0x14 "DHR8R2,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" line.long 0x18 "DHR12RD,Dual DAC 12-bit right-aligned data holding" hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data" hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data" line.long 0x1C "DHR12LD,DUAL DAC 12-bit left aligned data holding" hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data" hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data" line.long 0x20 "DHR8RD,DUAL DAC 8-bit right aligned data holding" hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data" hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data" rgroup.long 0x2C++0x7 line.long 0x0 "DOR1,DAC channel1 data output" hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are" line.long 0x4 "DOR2,DAC channel2 data output" hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are" group.long 0x34++0x1B line.long 0x0 "SR,DAC status register" rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1" rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1" bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1" rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1" rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1" bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1" line.long 0x4 "CCR,DAC calibration control" hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC Channel 2 offset trimming" hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC Channel 1 offset trimming" line.long 0x8 "MCR,DAC mode control register" hexmask.long.byte 0x8 16.--19. 1. "MODE2,DAC Channel 2 mode These bits can be" hexmask.long.byte 0x8 0.--3. 1. "MODE1,DAC Channel 1 mode These bits can be" line.long 0xC "SHSR1,DAC Sample and Hold sample time register" hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC Channel 1 sample Time (only valid in" line.long 0x10 "SHSR2,DAC Sample and Hold sample time register" hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC Channel 2 sample Time (only valid in" line.long 0x14 "SHHR,DAC Sample and Hold hold time" hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC Channel 2 hold time (only valid in" hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC Channel 1 hold Time (only valid in" line.long 0x18 "SHRR,DAC Sample and Hold refresh time" hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC Channel 2 refresh Time (only valid" hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC Channel 1 refresh Time (only valid" tree.end endif tree.end sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "DBGMCU (MCU Debug Component)" base ad:0x5C001000 rgroup.long 0x0++0x3 line.long 0x0 "IDC,DBGMCU Identity Code Register" hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision" hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device ID" group.long 0x4++0x3 line.long 0x0 "CR,DBGMCU Configuration Register" bitfld.long 0x0 28. "TRGOEN,External trigger output enable" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 22. "D3DBGCKEN,D3 debug clock enable" "0,1" bitfld.long 0x0 21. "D1DBGCKEN,D1 debug clock enable" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 22. "SRDDBGCKEN,SmartRun domain debug clock enable" "0,1" bitfld.long 0x0 21. "CDDBGCKEN,CPU domain debug clock enable" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 22. "SRDDBGCKEN,SmartRun domain debug clock enable" "0,1" bitfld.long 0x0 21. "CDDBGCKEN,CPU domain debug clock enable" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 22. "SRDDBGCKEN,SmartRun domain debug clock enable" "0,1" bitfld.long 0x0 21. "CDDBGCKEN,CPU domain debug clock enable" "0,1" endif bitfld.long 0x0 20. "TRACECLKEN,Trace port clock enable" "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 8. "DBGSTBD3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTPD3,Allow debug in D3 Stop mode" "0,1" bitfld.long 0x0 5. "DBGSTBD2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTPD2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLPD2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBD1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTPD1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLPD1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x0 8. "DBGSTBY_D3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTOP_D3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 8. "DBGSTBY_D3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTOP_D3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 8. "DBGSTBD3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTPD3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 8. "DBGSTBD3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTPD3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 8. "DBGSTBY_D3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTOP_D3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 8. "DBGSTBY_D3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTOP_D3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 8. "DBGSTBD3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTPD3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 8. "DBGSTBD3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTPD3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 8. "DBGSTBD3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTPD3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 8. "DBGSTBD3,Allow debug in D3 Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTPD3,Allow debug in D3 Stop mode" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 8. "DBGSTBY_SRD,debug in SmartRun domain Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTOP_SRD,debug in SmartRun domain Stop mode" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 8. "DBGSTBY_SRD,debug in SmartRun domain Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTOP_SRD,debug in SmartRun domain Stop mode" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 8. "DBGSTBY_SRD,debug in SmartRun domain Standby mode" "0,1" bitfld.long 0x0 7. "DBGSTOP_SRD,debug in SmartRun domain Stop mode" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x0 5. "DBGSTBY_D2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTOP_D2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLEEP_D2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBY_D1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTOP_D1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLEEP_D1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 5. "DBGSTBY_D2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTOP_D2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLEEP_D2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBY_D1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTOP_D1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLEEP_D1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 5. "DBGSTBD2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTPD2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLPD2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBD1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTPD1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLPD1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 5. "DBGSTBD2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTPD2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLPD2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBD1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTPD1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLPD1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 5. "DBGSTBY_D2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTOP_D2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLEEP_D2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBY_D1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTOP_D1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLEEP_D1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 5. "DBGSTBY_D2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTOP_D2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLEEP_D2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBY_D1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTOP_D1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLEEP_D1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 5. "DBGSTBD2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTPD2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLPD2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBD1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTPD1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLPD1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 5. "DBGSTBD2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTPD2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLPD2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBD1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTPD1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLPD1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 5. "DBGSTBD2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTPD2,Allow D2 domain debug in Stop mode" "0,1" bitfld.long 0x0 3. "DBGSLPD2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBD1,Allow D1 domain debug in Standby mode" "0,1" newline bitfld.long 0x0 1. "DBGSTPD1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLPD1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 5. "DBGSTBD2,Allow D2 domain debug in Standby mode" "0,1" bitfld.long 0x0 4. "DBGSTPD2,Allow D2 domain debug in Stop mode" "0,1" newline bitfld.long 0x0 3. "DBGSLPD2,Allow D2 domain debug in Sleep mode" "0,1" bitfld.long 0x0 2. "DBGSTBD1,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTPD1,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLPD1,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 2. "DBGSTBY_CD,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTOP_CD,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLEEP_CD,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 2. "DBGSTBY_CD,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTOP_CD,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLEEP_CD,Allow D1 domain debug in Sleep mode" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 2. "DBGSTBY_CD,Allow D1 domain debug in Standby mode" "0,1" bitfld.long 0x0 1. "DBGSTOP_CD,Allow D1 domain debug in Stop mode" "0,1" bitfld.long 0x0 0. "DBGSLEEP_CD,Allow D1 domain debug in Sleep mode" "0,1" endif group.long 0x34++0x3 line.long 0x0 "APB3FZ1,DBGMCU APB3 peripheral freeze register CPU1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 6. "WWDG,WWDG stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 6. "WWDG,WWDG stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 6. "WWDG,WWDG stop in debug" "0,1" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x38++0x3 line.long 0x0 "APB3FZ2,DBGMCU APB3 peripheral freeze register CPU2" bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" group.long 0x40++0x3 line.long 0x0 "APB1LFZ2,DBGMCU APB1L peripheral freeze register CPU2" bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" newline bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" newline bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_TIM7,TIM4 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" newline bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" group.long 0x50++0x3 line.long 0x0 "APB2FZ2,DBGMCU APB2 peripheral freeze register CPU2" bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" newline bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" group.long 0x58++0x3 line.long 0x0 "APB4FZ2,DBGMCU APB4 peripheral freeze register CPU2" bitfld.long 0x0 19. "DBG_WDGLSD2,LS watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,LS watchdog for D1 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" newline bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H745??-CM4")) group.long 0x38++0x3 line.long 0x0 "APB3FZ2,DBGMCU APB3 peripheral freeze register CPU2" bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" group.long 0x40++0x3 line.long 0x0 "APB1LFZ2,DBGMCU APB1L peripheral freeze register CPU2" bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" newline bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" newline bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_TIM7,TIM4 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" newline bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" group.long 0x50++0x3 line.long 0x0 "APB2FZ2,DBGMCU APB2 peripheral freeze register CPU2" bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" newline bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H747??-CM7")) group.long 0x38++0x3 line.long 0x0 "APB3FZ2,DBGMCU APB3 peripheral freeze register CPU2" bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" group.long 0x40++0x3 line.long 0x0 "APB1LFZ2,DBGMCU APB1L peripheral freeze register CPU2" bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" newline bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" newline bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_TIM7,TIM4 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" newline bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" group.long 0x50++0x3 line.long 0x0 "APB2FZ2,DBGMCU APB2 peripheral freeze register CPU2" bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" newline bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x38++0x3 line.long 0x0 "APB3FZ2,DBGMCU APB3 peripheral freeze register CPU2" bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" group.long 0x40++0x3 line.long 0x0 "APB1LFZ2,DBGMCU APB1L peripheral freeze register CPU2" bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" newline bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" newline bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_TIM7,TIM4 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" newline bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" group.long 0x50++0x3 line.long 0x0 "APB2FZ2,DBGMCU APB2 peripheral freeze register CPU2" bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" newline bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x38++0x3 line.long 0x0 "APB3FZ2,DBGMCU APB3 peripheral freeze register CPU2" bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" group.long 0x40++0x3 line.long 0x0 "APB1LFZ2,DBGMCU APB1L peripheral freeze register CPU2" bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" newline bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" newline bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_TIM7,TIM4 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" newline bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" group.long 0x50++0x3 line.long 0x0 "APB2FZ2,DBGMCU APB2 peripheral freeze register CPU2" bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" newline bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x38++0x3 line.long 0x0 "APB3FZ2,DBGMCU APB3 peripheral freeze register CPU2" bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" group.long 0x40++0x3 line.long 0x0 "APB1LFZ2,DBGMCU APB1L peripheral freeze register CPU2" bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" newline bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" newline bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_TIM7,TIM4 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" newline bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" group.long 0x50++0x3 line.long 0x0 "APB2FZ2,DBGMCU APB2 peripheral freeze register CPU2" bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" newline bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x38++0x3 line.long 0x0 "APB3FZ2,DBGMCU APB3 peripheral freeze register CPU2" bitfld.long 0x0 6. "WWDG1,WWDG1 stop in debug" "0,1" group.long 0x40++0x3 line.long 0x0 "APB1LFZ2,DBGMCU APB1L peripheral freeze register CPU2" bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" newline bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" newline bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" newline bitfld.long 0x0 5. "DBG_TIM7,TIM4 stop in debug" "0,1" bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" newline bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" group.long 0x50++0x3 line.long 0x0 "APB2FZ2,DBGMCU APB2 peripheral freeze register CPU2" bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" newline bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" newline bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" endif group.long 0x3C++0x3 line.long 0x0 "APB1LFZ1,DBGMCU APB1L peripheral freeze register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 23. "DBG_I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "DBG_I2C2,I2C2 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 21. "DBG_I2C1,I2C1 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 9. "DBG_LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "DBG_TIM14,TIM14 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "DBG_TIM12,TIM12 stop in debug" "0,1" bitfld.long 0x0 5. "DBG_TIM7,TIM7 stop in debug" "0,1" newline bitfld.long 0x0 4. "DBG_TIM6,TIM6 stop in debug" "0,1" bitfld.long 0x0 3. "DBG_TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "DBG_TIM4,TIM4 stop in debug" "0,1" bitfld.long 0x0 1. "DBG_TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM2,TIM2 stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 23. "I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "I2C2,I2C2 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 21. "I2C1,I2C1 SMBUS timeout stop in debug" "0,1" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 23. "I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "I2C2,I2C2 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 21. "I2C1,I2C1 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 23. "I2C3,I2C3 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 22. "I2C2,I2C2 SMBUS timeout stop in debug" "0,1" bitfld.long 0x0 21. "I2C1,I2C1 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 11. "DBG_WWDG2,WWDG2 stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 9. "LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "TIM14,TIM14 stop in debug" "0,1" bitfld.long 0x0 7. "TIM13,TIM13 stop in debug" "0,1" newline bitfld.long 0x0 6. "TIM12,TIM12 stop in debug" "0,1" bitfld.long 0x0 5. "TIM7,TIM7 stop in debug" "0,1" bitfld.long 0x0 4. "TIM6,TIM6 stop in debug" "0,1" bitfld.long 0x0 3. "TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "TIM4,TIM4 stop in debug" "0,1" bitfld.long 0x0 1. "TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "TIM2,TIM2 stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 9. "LPTIM1,LPTIM1 stop in debug" "0,1" newline bitfld.long 0x0 8. "TIM14,TIM14 stop in debug" "0,1" bitfld.long 0x0 7. "TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "TIM12,TIM12 stop in debug" "0,1" bitfld.long 0x0 5. "TIM7,TIM7 stop in debug" "0,1" bitfld.long 0x0 4. "TIM6,TIM6 stop in debug" "0,1" bitfld.long 0x0 3. "TIM5,TIM5 stop in debug" "0,1" bitfld.long 0x0 2. "TIM4,TIM4 stop in debug" "0,1" bitfld.long 0x0 1. "TIM3,TIM3 stop in debug" "0,1" newline bitfld.long 0x0 0. "TIM2,TIM2 stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 9. "LPTIM1,LPTIM1 stop in debug" "0,1" bitfld.long 0x0 8. "TIM14,TIM14 stop in debug" "0,1" bitfld.long 0x0 7. "TIM13,TIM13 stop in debug" "0,1" bitfld.long 0x0 6. "TIM12,TIM12 stop in debug" "0,1" bitfld.long 0x0 5. "TIM7,TIM7 stop in debug" "0,1" bitfld.long 0x0 4. "TIM6,TIM6 stop in debug" "0,1" bitfld.long 0x0 3. "TIM5,TIM5 stop in debug" "0,1" newline bitfld.long 0x0 2. "TIM4,TIM4 stop in debug" "0,1" bitfld.long 0x0 1. "TIM3,TIM3 stop in debug" "0,1" bitfld.long 0x0 0. "TIM2,TIM2 stop in debug" "0,1" endif group.long 0x4C++0x3 line.long 0x0 "APB2FZ1,DBGMCU APB2 peripheral freeze register" sif (cpuis("STM32H742*")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 29. "DBG_HRTIM,HRTIM stop in debug" "0,1" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 18. "DBG_TIM17,TIM17 stop in debug" "0,1" bitfld.long 0x0 17. "DBG_TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "DBG_TIM15,TIM15 stop in debug" "0,1" bitfld.long 0x0 1. "DBG_TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "DBG_TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 18. "TIM17,TIM17 stop in debug" "0,1" newline bitfld.long 0x0 17. "TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "TIM15,TIM15 stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 18. "TIM17,TIM17 stop in debug" "0,1" bitfld.long 0x0 17. "TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "TIM15,TIM15 stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 18. "TIM17,TIM17 stop in debug" "0,1" bitfld.long 0x0 17. "TIM16,TIM16 stop in debug" "0,1" bitfld.long 0x0 16. "TIM15,TIM15 stop in debug" "0,1" newline endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 1. "TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 1. "TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "TIM1,TIM1 stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 1. "TIM8,TIM8 stop in debug" "0,1" bitfld.long 0x0 0. "TIM1,TIM1 stop in debug" "0,1" endif group.long 0x54++0x3 line.long 0x0 "APB4FZ1,DBGMCU APB4 peripheral freeze register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 19. "DBG_WDGLSD2,Independent watchdog for D2 stop in debug" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 19. "DBG_WDGLSD2,Independent watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 19. "DBG_WDGLSD2,Independent watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 19. "DBG_WDGLSD2,Independent watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 19. "DBG_WDGLSD2,Independent watchdog for D2 stop in debug" "0,1" newline bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 19. "DBG_WDGLSD2,Independent watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 19. "DBG_WDGLSD2,Independent watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 18. "DBG_IWDG1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 18. "DBG_WDGLSD1,Independent watchdog for D1 stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 18. "WDGLSCD,LS watchdog for CPU domain stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 18. "WDGLSCD,LS watchdog for CPU domain stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 18. "WDGLSCD,LS watchdog for CPU domain stop in debug" "0,1" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 16. "RTC,RTC stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 16. "RTC,RTC stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 16. "RTC,RTC stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 10. "LPTIM3,LPTIM3 stop in debug" "0,1" bitfld.long 0x0 9. "LPTIM2,LPTIM2 stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 10. "LPTIM3,LPTIM3 stop in debug" "0,1" newline bitfld.long 0x0 9. "LPTIM2,LPTIM2 stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 10. "LPTIM3,LPTIM3 stop in debug" "0,1" bitfld.long 0x0 9. "LPTIM2,LPTIM2 stop in debug" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 7. "I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 7. "I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 7. "I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H745??-CM4")) group.long 0x58++0x3 line.long 0x0 "APB4FZ2,DBGMCU APB4 peripheral freeze register CPU2" bitfld.long 0x0 19. "DBG_WDGLSD2,LS watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,LS watchdog for D1 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" newline bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H747??-CM7")) group.long 0x58++0x3 line.long 0x0 "APB4FZ2,DBGMCU APB4 peripheral freeze register CPU2" bitfld.long 0x0 19. "DBG_WDGLSD2,LS watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,LS watchdog for D1 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" newline bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x58++0x3 line.long 0x0 "APB4FZ2,DBGMCU APB4 peripheral freeze register CPU2" bitfld.long 0x0 19. "DBG_WDGLSD2,LS watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,LS watchdog for D1 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" newline bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x58++0x3 line.long 0x0 "APB4FZ2,DBGMCU APB4 peripheral freeze register CPU2" bitfld.long 0x0 19. "DBG_WDGLSD2,LS watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,LS watchdog for D1 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" newline bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x58++0x3 line.long 0x0 "APB4FZ2,DBGMCU APB4 peripheral freeze register CPU2" bitfld.long 0x0 19. "DBG_WDGLSD2,LS watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,LS watchdog for D1 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" newline bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x58++0x3 line.long 0x0 "APB4FZ2,DBGMCU APB4 peripheral freeze register CPU2" bitfld.long 0x0 19. "DBG_WDGLSD2,LS watchdog for D2 stop in debug" "0,1" bitfld.long 0x0 18. "DBG_WDGLSD1,LS watchdog for D1 stop in debug" "0,1" newline bitfld.long 0x0 16. "DBG_RTC,RTC stop in debug" "0,1" bitfld.long 0x0 12. "DBG_LPTIM5,LPTIM5 stop in debug" "0,1" newline bitfld.long 0x0 11. "DBG_LPTIM4,LPTIM4 stop in debug" "0,1" bitfld.long 0x0 10. "DBG_LPTIM3,LPTIM2 stop in debug" "0,1" newline bitfld.long 0x0 9. "DBG_LPTIM2,LPTIM2 stop in debug" "0,1" bitfld.long 0x0 7. "DBG_I2C4,I2C4 SMBUS timeout stop in debug" "0,1" endif tree.end endif tree "DCMI (Digital Camera Interface)" base ad:0x48020000 group.long 0x0++0x3 line.long 0x0 "CR,control register 1" bitfld.long 0x0 20. "OELS,Odd/Even Line Select (Line Select" "0,1" bitfld.long 0x0 19. "LSM,Line Select mode" "0,1" bitfld.long 0x0 18. "OEBS,Odd/Even Byte Select (Byte Select" "0,1" bitfld.long 0x0 16.--17. "BSM,Byte Select mode" "0,1,2,3" bitfld.long 0x0 14. "ENABLE,DCMI enable" "0,1" bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0,1,2,3" bitfld.long 0x0 8.--9. "FCRC,Frame capture rate control" "0,1,2,3" bitfld.long 0x0 7. "VSPOL,Vertical synchronization" "0,1" bitfld.long 0x0 6. "HSPOL,Horizontal synchronization" "0,1" newline bitfld.long 0x0 5. "PCKPOL,Pixel clock polarity" "0,1" bitfld.long 0x0 4. "ESS,Embedded synchronization" "0,1" bitfld.long 0x0 3. "JPEG,JPEG format" "0,1" bitfld.long 0x0 2. "CROP,Crop feature" "0,1" bitfld.long 0x0 1. "CM,Capture mode" "0,1" bitfld.long 0x0 0. "CAPTURE,Capture enable" "0,1" rgroup.long 0x4++0x7 line.long 0x0 "SR,status register" bitfld.long 0x0 2. "FNE,FIFO not empty" "0,1" bitfld.long 0x0 1. "VSYNC,VSYNC" "0,1" bitfld.long 0x0 0. "HSYNC,HSYNC" "0,1" line.long 0x4 "RIS,raw interrupt status register" bitfld.long 0x4 4. "LINE_RIS,Line raw interrupt status" "0,1" bitfld.long 0x4 3. "VSYNC_RIS,VSYNC raw interrupt status" "0,1" bitfld.long 0x4 2. "ERR_RIS,Synchronization error raw interrupt" "0,1" bitfld.long 0x4 1. "OVR_RIS,Overrun raw interrupt" "0,1" bitfld.long 0x4 0. "FRAME_RIS,Capture complete raw interrupt" "0,1" group.long 0xC++0x3 line.long 0x0 "IER,interrupt enable register" bitfld.long 0x0 4. "LINE_IE,Line interrupt enable" "0,1" bitfld.long 0x0 3. "VSYNC_IE,VSYNC interrupt enable" "0,1" bitfld.long 0x0 2. "ERR_IE,Synchronization error interrupt" "0,1" bitfld.long 0x0 1. "OVR_IE,Overrun interrupt enable" "0,1" bitfld.long 0x0 0. "FRAME_IE,Capture complete interrupt" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MIS,masked interrupt status" bitfld.long 0x0 4. "LINE_MIS,Line masked interrupt" "0,1" bitfld.long 0x0 3. "VSYNC_MIS,VSYNC masked interrupt" "0,1" bitfld.long 0x0 2. "ERR_MIS,Synchronization error masked interrupt" "0,1" bitfld.long 0x0 1. "OVR_MIS,Overrun masked interrupt" "0,1" bitfld.long 0x0 0. "FRAME_MIS,Capture complete masked interrupt" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "ICR,interrupt clear register" bitfld.long 0x0 4. "LINE_ISC,line interrupt status" "0,1" bitfld.long 0x0 3. "VSYNC_ISC,Vertical synch interrupt status" "0,1" bitfld.long 0x0 2. "ERR_ISC,Synchronization error interrupt status" "0,1" bitfld.long 0x0 1. "OVR_ISC,Overrun interrupt status" "0,1" bitfld.long 0x0 0. "FRAME_ISC,Capture complete interrupt status" "0,1" group.long 0x18++0xF line.long 0x0 "ESCR,embedded synchronization code" hexmask.long.byte 0x0 24.--31. 1. "FEC,Frame end delimiter code" hexmask.long.byte 0x0 16.--23. 1. "LEC,Line end delimiter code" hexmask.long.byte 0x0 8.--15. 1. "LSC,Line start delimiter code" hexmask.long.byte 0x0 0.--7. 1. "FSC,Frame start delimiter code" line.long 0x4 "ESUR,embedded synchronization unmask" hexmask.long.byte 0x4 24.--31. 1. "FEU,Frame end delimiter unmask" hexmask.long.byte 0x4 16.--23. 1. "LEU,Line end delimiter unmask" hexmask.long.byte 0x4 8.--15. 1. "LSU,Line start delimiter" hexmask.long.byte 0x4 0.--7. 1. "FSU,Frame start delimiter" line.long 0x8 "CWSTRT,crop window start" hexmask.long.word 0x8 16.--28. 1. "VST,Vertical start line count" hexmask.long.word 0x8 0.--13. 1. "HOFFCNT,Horizontal offset count" line.long 0xC "CWSIZE,crop window size" hexmask.long.word 0xC 16.--29. 1. "VLINE,Vertical line count" hexmask.long.word 0xC 0.--13. 1. "CAPCNT,Capture count" rgroup.long 0x28++0x3 line.long 0x0 "DR,data register" hexmask.long.byte 0x0 24.--31. 1. "Byte3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "Byte2,Data byte 2" hexmask.long.byte 0x0 8.--15. 1. "Byte1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "Byte0,Data byte 0" tree.end tree "DFSDM (Digital Filter for Sigma Delta Modulators)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) base ad:0x40017800 elif (cpuis("STM32H742*")) base ad:0x40017000 endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "DFSDM" group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H743*")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x5F line.long 0x0 "DFSDM_CHCFG0R1,DFSDM channel configuration 0 register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0x0 7. "CHEN,Channel 0 enable" "0,1" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0x4 "DFSDM_CHCFG1R1,DFSDM channel configuration 1 register" bitfld.long 0x4 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0x4 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0x4 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0x4 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0x4 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0x4 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0x4 7. "CHEN,Channel 1 enable" "0,1" bitfld.long 0x4 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0x4 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0x4 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0x4 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0x8 "DFSDM_CHCFG2R1,DFSDM channel configuration 2 register" bitfld.long 0x8 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0x8 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0x8 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0x8 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0x8 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0x8 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0x8 7. "CHEN,Channel 2 enable" "0,1" bitfld.long 0x8 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0x8 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0x8 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0x8 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0xC "DFSDM_CHCFG3R1,DFSDM channel configuration 3 register" bitfld.long 0xC 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0xC 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0xC 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0xC 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0xC 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0xC 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0xC 7. "CHEN,Channel 3 enable" "0,1" bitfld.long 0xC 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0xC 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0xC 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0xC 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0x10 "DFSDM_CHCFG4R1,DFSDM channel configuration 4 register" bitfld.long 0x10 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0x10 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0x10 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0x10 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0x10 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0x10 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0x10 7. "CHEN,Channel 4 enable" "0,1" bitfld.long 0x10 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0x10 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0x10 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0x10 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0x14 "DFSDM_CHCFG5R1,DFSDM channel configuration 5 register" bitfld.long 0x14 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0x14 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0x14 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0x14 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0x14 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0x14 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0x14 7. "CHEN,Channel 5 enable" "0,1" bitfld.long 0x14 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0x14 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0x14 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0x14 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0x18 "DFSDM_CHCFG6R1,DFSDM channel configuration 6 register" bitfld.long 0x18 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0x18 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0x18 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0x18 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0x18 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0x18 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0x18 7. "CHEN,Channel 6 enable" "0,1" bitfld.long 0x18 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0x18 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0x18 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0x18 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0x1C "DFSDM_CHCFG7R1,DFSDM channel configuration 7 register" bitfld.long 0x1C 31. "DFSDMEN,Global enable for DFSDM" "0,1" bitfld.long 0x1C 30. "CKOUTSRC,Output serial clock source" "0,1" hexmask.long.byte 0x1C 16.--23. 1. "CKOUTDIV,Output serial clock" bitfld.long 0x1C 14.--15. "DATPACK,Data packing mode in DFSDM_CHDATINyR" "0,1,2,3" bitfld.long 0x1C 12.--13. "DATMPX,Input data multiplexer for channel" "0,1,2,3" bitfld.long 0x1C 8. "CHINSEL,Channel inputs selection" "0,1" bitfld.long 0x1C 7. "CHEN,Channel 7 enable" "0,1" bitfld.long 0x1C 6. "CKABEN,Clock absence detector enable on channel" "0,1" newline bitfld.long 0x1C 5. "SCDEN,Short-circuit detector enable on channel" "0,1" bitfld.long 0x1C 2.--3. "SPICKSEL,SPI clock select for channel" "0,1,2,3" bitfld.long 0x1C 0.--1. "SITP,Serial interface type for channel" "0,1,2,3" line.long 0x20 "DFSDM_CHCFG0R2,DFSDM channel configuration 0 register" hexmask.long.tbyte 0x20 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x20 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x24 "DFSDM_CHCFG1R2,DFSDM channel configuration 1 register" hexmask.long.tbyte 0x24 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x24 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x28 "DFSDM_CHCFG2R2,DFSDM channel configuration 2 register" hexmask.long.tbyte 0x28 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x28 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x2C "DFSDM_CHCFG3R2,DFSDM channel configuration 3 register" hexmask.long.tbyte 0x2C 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x2C 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x30 "DFSDM_CHCFG4R2,DFSDM channel configuration 4 register" hexmask.long.tbyte 0x30 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x30 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x34 "DFSDM_CHCFG5R2,DFSDM channel configuration 5 register" hexmask.long.tbyte 0x34 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x34 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x38 "DFSDM_CHCFG6R2,DFSDM channel configuration 6 register" hexmask.long.tbyte 0x38 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x38 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x3C "DFSDM_CHCFG7R2,DFSDM channel configuration 7 register" hexmask.long.tbyte 0x3C 8.--31. 1. "OFFSET,24-bit calibration offset for channel" hexmask.long.byte 0x3C 3.--7. 1. "DTRBS,Data right bit-shift for channel" line.long 0x40 "DFSDM_AWSCD0R,DFSDM analog watchdog and short-circuit" bitfld.long 0x40 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x40 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x40 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x40 0.--7. 1. "SCDT,short-circuit detector threshold for" line.long 0x44 "DFSDM_AWSCD1R,DFSDM analog watchdog and short-circuit" bitfld.long 0x44 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x44 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x44 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x44 0.--7. 1. "SCDT,short-circuit detector threshold for" line.long 0x48 "DFSDM_AWSCD2R,DFSDM analog watchdog and short-circuit" bitfld.long 0x48 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x48 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x48 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x48 0.--7. 1. "SCDT,short-circuit detector threshold for" line.long 0x4C "DFSDM_AWSCD3R,DFSDM analog watchdog and short-circuit" bitfld.long 0x4C 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x4C 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x4C 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x4C 0.--7. 1. "SCDT,short-circuit detector threshold for" line.long 0x50 "DFSDM_AWSCD4R,DFSDM analog watchdog and short-circuit" bitfld.long 0x50 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x50 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x50 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x50 0.--7. 1. "SCDT,short-circuit detector threshold for" line.long 0x54 "DFSDM_AWSCD5R,DFSDM analog watchdog and short-circuit" bitfld.long 0x54 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x54 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x54 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x54 0.--7. 1. "SCDT,short-circuit detector threshold for" line.long 0x58 "DFSDM_AWSCD6R,DFSDM analog watchdog and short-circuit" bitfld.long 0x58 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x58 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x58 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x58 0.--7. 1. "SCDT,short-circuit detector threshold for" line.long 0x5C "DFSDM_AWSCD7R,DFSDM analog watchdog and short-circuit" bitfld.long 0x5C 22.--23. "AWFORD,Analog watchdog Sinc filter order on" "0,1,2,3" hexmask.long.byte 0x5C 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling" hexmask.long.byte 0x5C 12.--15. 1. "BKSCD,Break signal assignment for" hexmask.long.byte 0x5C 0.--7. 1. "SCDT,short-circuit detector threshold for" rgroup.long 0x60++0x1F line.long 0x0 "DFSDM_CHWDAT0R,DFSDM channel watchdog filter data" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog" line.long 0x4 "DFSDM_CHWDAT1R,DFSDM channel watchdog filter data" hexmask.long.word 0x4 0.--15. 1. "WDATA,Input channel y watchdog" line.long 0x8 "DFSDM_CHWDAT2R,DFSDM channel watchdog filter data" hexmask.long.word 0x8 0.--15. 1. "WDATA,Input channel y watchdog" line.long 0xC "DFSDM_CHWDAT3R,DFSDM channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,Input channel y watchdog" line.long 0x10 "DFSDM_CHWDAT4R,DFSDM channel watchdog filter data" hexmask.long.word 0x10 0.--15. 1. "WDATA,Input channel y watchdog" line.long 0x14 "DFSDM_CHWDAT5R,DFSDM channel watchdog filter data" hexmask.long.word 0x14 0.--15. 1. "WDATA,Input channel y watchdog" line.long 0x18 "DFSDM_CHWDAT6R,DFSDM channel watchdog filter data" hexmask.long.word 0x18 0.--15. 1. "WDATA,Input channel y watchdog" line.long 0x1C "DFSDM_CHWDAT7R,DFSDM channel watchdog filter data" hexmask.long.word 0x1C 0.--15. 1. "WDATA,Input channel y watchdog" group.long 0x80++0x3F line.long 0x0 "DFSDM_CHDATIN0R,DFSDM channel data input" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel 1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel 0" line.long 0x4 "DFSDM_CHDATIN1R,DFSDM channel data input" hexmask.long.word 0x4 16.--31. 1. "INDAT1,Input data for channel 2" hexmask.long.word 0x4 0.--15. 1. "INDAT0,Input data for channel 1" line.long 0x8 "DFSDM_CHDATIN2R,DFSDM channel data input" hexmask.long.word 0x8 16.--31. 1. "INDAT1,Input data for channel 3" hexmask.long.word 0x8 0.--15. 1. "INDAT0,Input data for channel 2" line.long 0xC "DFSDM_CHDATIN3R,DFSDM channel data input" hexmask.long.word 0xC 16.--31. 1. "INDAT1,Input data for channel 4" hexmask.long.word 0xC 0.--15. 1. "INDAT0,Input data for channel 3" line.long 0x10 "DFSDM_CHDATIN4R,DFSDM channel data input" hexmask.long.word 0x10 16.--31. 1. "INDAT1,Input data for channel 5" hexmask.long.word 0x10 0.--15. 1. "INDAT0,Input data for channel 4" line.long 0x14 "DFSDM_CHDATIN5R,DFSDM channel data input" hexmask.long.word 0x14 16.--31. 1. "INDAT1,Input data for channel 6" hexmask.long.word 0x14 0.--15. 1. "INDAT0,Input data for channel 5" line.long 0x18 "DFSDM_CHDATIN6R,DFSDM channel data input" hexmask.long.word 0x18 16.--31. 1. "INDAT1,Input data for channel 7" hexmask.long.word 0x18 0.--15. 1. "INDAT0,Input data for channel 6" line.long 0x1C "DFSDM_CHDATIN7R,DFSDM channel data input" hexmask.long.word 0x1C 16.--31. 1. "INDAT1,Input data for channel 8" hexmask.long.word 0x1C 0.--15. 1. "INDAT0,Input data for channel 7" line.long 0x20 "DFSDM0_CR1,DFSDM control register 1" bitfld.long 0x20 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x20 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x20 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x20 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x20 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x20 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x20 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x20 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline hexmask.long.byte 0x20 8.--12. 1. "JEXTSEL,Trigger signal selection for launching" bitfld.long 0x20 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x20 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x20 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x20 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x20 0. "DFEN,DFSDM enable" "0,1" line.long 0x24 "DFSDM1_CR1,DFSDM control register 1" bitfld.long 0x24 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x24 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x24 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x24 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x24 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x24 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x24 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x24 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline hexmask.long.byte 0x24 8.--12. 1. "JEXTSEL,Trigger signal selection for launching" bitfld.long 0x24 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x24 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x24 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x24 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x24 0. "DFEN,DFSDM enable" "0,1" line.long 0x28 "DFSDM2_CR1,DFSDM control register 1" bitfld.long 0x28 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x28 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x28 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x28 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x28 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x28 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x28 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x28 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline hexmask.long.byte 0x28 8.--12. 1. "JEXTSEL,Trigger signal selection for launching" bitfld.long 0x28 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x28 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x28 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x28 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x28 0. "DFEN,DFSDM enable" "0,1" line.long 0x2C "DFSDM3_CR1,DFSDM control register 1" bitfld.long 0x2C 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x2C 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x2C 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x2C 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x2C 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x2C 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x2C 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline hexmask.long.byte 0x2C 8.--12. 1. "JEXTSEL,Trigger signal selection for launching" bitfld.long 0x2C 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x2C 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x2C 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x2C 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x2C 0. "DFEN,DFSDM enable" "0,1" line.long 0x30 "DFSDM0_CR2,DFSDM control register 2" hexmask.long.byte 0x30 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x30 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x30 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x30 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x30 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x30 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x30 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x30 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x30 0. "JEOCIE,Injected end of conversion interrupt" "0,1" line.long 0x34 "DFSDM1_CR2,DFSDM control register 2" hexmask.long.byte 0x34 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x34 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x34 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x34 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x34 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x34 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x34 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x34 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x34 0. "JEOCIE,Injected end of conversion interrupt" "0,1" line.long 0x38 "DFSDM2_CR2,DFSDM control register 2" hexmask.long.byte 0x38 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x38 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x38 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x38 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x38 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x38 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x38 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x38 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x38 0. "JEOCIE,Injected end of conversion interrupt" "0,1" line.long 0x3C "DFSDM3_CR2,DFSDM control register 2" hexmask.long.byte 0x3C 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x3C 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x3C 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x3C 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x3C 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x3C 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x3C 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x3C 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x3C 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0xC0++0xF line.long 0x0 "DFSDM0_ISR,DFSDM interrupt and status" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" line.long 0x4 "DFSDM1_ISR,DFSDM interrupt and status" hexmask.long.byte 0x4 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x4 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x4 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x4 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x4 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x4 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x4 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x4 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x4 0. "JEOCF,End of injected conversion" "0,1" line.long 0x8 "DFSDM2_ISR,DFSDM interrupt and status" hexmask.long.byte 0x8 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x8 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x8 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x8 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x8 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x8 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x8 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x8 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x8 0. "JEOCF,End of injected conversion" "0,1" line.long 0xC "DFSDM3_ISR,DFSDM interrupt and status" hexmask.long.byte 0xC 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0xC 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0xC 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0xC 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0xC 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0xC 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0xC 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0xC 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0xC 0. "JEOCF,End of injected conversion" "0,1" group.long 0xD0++0x2F line.long 0x0 "DFSDM0_ICR,DFSDM interrupt flag clear" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM1_ICR,DFSDM interrupt flag clear" hexmask.long.byte 0x4 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x4 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x4 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x4 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x8 "DFSDM2_ICR,DFSDM interrupt flag clear" hexmask.long.byte 0x8 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x8 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x8 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x8 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0xC "DFSDM3_ICR,DFSDM interrupt flag clear" hexmask.long.byte 0xC 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0xC 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0xC 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0xC 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x10 "DFSDM0_JCHGR,DFSDM injected channel group selection" hexmask.long.byte 0x10 0.--7. 1. "JCHG,Injected channel group" line.long 0x14 "DFSDM1_JCHGR,DFSDM injected channel group selection" hexmask.long.byte 0x14 0.--7. 1. "JCHG,Injected channel group" line.long 0x18 "DFSDM2_JCHGR,DFSDM injected channel group selection" hexmask.long.byte 0x18 0.--7. 1. "JCHG,Injected channel group" line.long 0x1C "DFSDM3_JCHGR,DFSDM injected channel group selection" hexmask.long.byte 0x1C 0.--7. 1. "JCHG,Injected channel group" line.long 0x20 "DFSDM0_FCR,DFSDM filter control register" bitfld.long 0x20 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x20 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x20 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" line.long 0x24 "DFSDM1_FCR,DFSDM filter control register" bitfld.long 0x24 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x24 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x24 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" line.long 0x28 "DFSDM2_FCR,DFSDM filter control register" bitfld.long 0x28 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x28 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x28 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" line.long 0x2C "DFSDM3_FCR,DFSDM filter control register" bitfld.long 0x2C 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x2C 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x2C 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x100++0x1F line.long 0x0 "DFSDM0_JDATAR,DFSDM data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM1_JDATAR,DFSDM data register for injected" hexmask.long.tbyte 0x4 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x4 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM2_JDATAR,DFSDM data register for injected" hexmask.long.tbyte 0x8 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x8 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0xC "DFSDM3_JDATAR,DFSDM data register for injected" hexmask.long.tbyte 0xC 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0xC 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x10 "DFSDM0_RDATAR,DFSDM data register for the regular" hexmask.long.tbyte 0x10 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x10 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x10 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" line.long 0x14 "DFSDM1_RDATAR,DFSDM data register for the regular" hexmask.long.tbyte 0x14 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x14 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x14 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" line.long 0x18 "DFSDM2_RDATAR,DFSDM data register for the regular" hexmask.long.tbyte 0x18 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x18 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x18 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" line.long 0x1C "DFSDM3_RDATAR,DFSDM data register for the regular" hexmask.long.tbyte 0x1C 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x1C 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x1C 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x1F line.long 0x0 "DFSDM0_AWHTR,DFSDM analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM1_AWHTR,DFSDM analog watchdog high threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x4 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x8 "DFSDM2_AWHTR,DFSDM analog watchdog high threshold" hexmask.long.tbyte 0x8 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x8 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0xC "DFSDM3_AWHTR,DFSDM analog watchdog high threshold" hexmask.long.tbyte 0xC 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0xC 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x10 "DFSDM0_AWLTR,DFSDM analog watchdog low threshold" hexmask.long.tbyte 0x10 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x10 0.--3. 1. "BKAWL,Break signal assignment to analog" line.long 0x14 "DFSDM1_AWLTR,DFSDM analog watchdog low threshold" hexmask.long.tbyte 0x14 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x14 0.--3. 1. "BKAWL,Break signal assignment to analog" line.long 0x18 "DFSDM2_AWLTR,DFSDM analog watchdog low threshold" hexmask.long.tbyte 0x18 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x18 0.--3. 1. "BKAWL,Break signal assignment to analog" line.long 0x1C "DFSDM3_AWLTR,DFSDM analog watchdog low threshold" hexmask.long.tbyte 0x1C 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x1C 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x140++0xF line.long 0x0 "DFSDM0_AWSR,DFSDM analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" line.long 0x4 "DFSDM1_AWSR,DFSDM analog watchdog status" hexmask.long.byte 0x4 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x4 0.--7. 1. "AWLTF,Analog watchdog low threshold" line.long 0x8 "DFSDM2_AWSR,DFSDM analog watchdog status" hexmask.long.byte 0x8 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x8 0.--7. 1. "AWLTF,Analog watchdog low threshold" line.long 0xC "DFSDM3_AWSR,DFSDM analog watchdog status" hexmask.long.byte 0xC 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0xC 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x150++0xF line.long 0x0 "DFSDM0_AWCFR,DFSDM analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" line.long 0x4 "DFSDM1_AWCFR,DFSDM analog watchdog clear flag" hexmask.long.byte 0x4 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x4 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" line.long 0x8 "DFSDM2_AWCFR,DFSDM analog watchdog clear flag" hexmask.long.byte 0x8 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x8 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" line.long 0xC "DFSDM3_AWCFR,DFSDM analog watchdog clear flag" hexmask.long.byte 0xC 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0xC 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x160++0x2F line.long 0x0 "DFSDM0_EXMAX,DFSDM Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM1_EXMAX,DFSDM Extremes detector maximum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x4 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM2_EXMAX,DFSDM Extremes detector maximum" hexmask.long.tbyte 0x8 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x8 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0xC "DFSDM3_EXMAX,DFSDM Extremes detector maximum" hexmask.long.tbyte 0xC 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0xC 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x10 "DFSDM0_EXMIN,DFSDM Extremes detector minimum" hexmask.long.tbyte 0x10 8.--31. 1. "EXMIN,Extremes detector minimum" bitfld.long 0x10 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x14 "DFSDM1_EXMIN,DFSDM Extremes detector minimum" hexmask.long.tbyte 0x14 8.--31. 1. "EXMIN,Extremes detector minimum" bitfld.long 0x14 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x18 "DFSDM2_EXMIN,DFSDM Extremes detector minimum" hexmask.long.tbyte 0x18 8.--31. 1. "EXMIN,Extremes detector minimum" bitfld.long 0x18 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x1C "DFSDM3_EXMIN,DFSDM Extremes detector minimum" hexmask.long.tbyte 0x1C 8.--31. 1. "EXMIN,Extremes detector minimum" bitfld.long 0x1C 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x20 "DFSDM0_CNVTIMR,DFSDM conversion timer" hexmask.long 0x20 4.--31. 1. "CNVCNT,28-bit timer counting conversion" line.long 0x24 "DFSDM1_CNVTIMR,DFSDM conversion timer" hexmask.long 0x24 4.--31. 1. "CNVCNT,28-bit timer counting conversion" line.long 0x28 "DFSDM2_CNVTIMR,DFSDM conversion timer" hexmask.long 0x28 4.--31. 1. "CNVCNT,28-bit timer counting conversion" line.long 0x2C "DFSDM3_CNVTIMR,DFSDM conversion timer" hexmask.long 0x2C 4.--31. 1. "CNVCNT,28-bit timer counting conversion" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H750*")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H753*")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "DFSDM" base ad:0x40017000 group.long 0x0++0x17 line.long 0x0 "CH0CFGR1,channel configuration y" bitfld.long 0x0 31. "DFSDMEN,DFSDMEN" "0,1" bitfld.long 0x0 30. "CKOUTSRC,CKOUTSRC" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,CKOUTDIV" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" newline bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH0CFGR2,channel configuration y" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH0AWSCDR,analog watchdog and short-circuit detector" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH0WDATR,channel watchdog filter data" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH0DATINR,channel data input register" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH0DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x20++0x17 line.long 0x0 "CH1CFGR1,CH1CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH1CFGR2,CH1CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH1AWSCDR,CH1AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH1WDATR,CH1WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH1DATINR,CH1DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH1DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x40++0x17 line.long 0x0 "CH2CFGR1,CH2CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH2CFGR2,CH2CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH2AWSCDR,CH2AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH2WDATR,CH2WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH2DATINR,CH2DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH2DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x60++0x17 line.long 0x0 "CH3CFGR1,CH3CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH3CFGR2,CH3CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH3AWSCDR,CH3AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH3WDATR,CH3WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH3DATINR,CH3DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH3DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x80++0x17 line.long 0x0 "CH4CFGR1,CH4CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH4CFGR2,CH4CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH4AWSCDR,CH4AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH4WDATR,CH4WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH4DATINR,CH4DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH4DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xA0++0x17 line.long 0x0 "CH5CFGR1,CH5CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH5CFGR2,CH5CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH5AWSCDR,CH5AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH5WDATR,CH5WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH5DATINR,CH5DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH5DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xC0++0x17 line.long 0x0 "CH6CFGR1,CH6CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH6CFGR2,CH6CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH6AWSCDR,CH6AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH6WDATR,CH6WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH6DATINR,CH6DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH6DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0xE0++0x17 line.long 0x0 "CH7CFGR1,CH7CFGR1" bitfld.long 0x0 14.--15. "DATPACK,DATPACK" "0,1,2,3" bitfld.long 0x0 12.--13. "DATMPX,DATMPX" "0,1,2,3" bitfld.long 0x0 8. "CHINSEL,CHINSEL" "0,1" bitfld.long 0x0 7. "CHEN,CHEN" "0,1" bitfld.long 0x0 6. "CKABEN,CKABEN" "0,1" bitfld.long 0x0 5. "SCDEN,SCDEN" "0,1" bitfld.long 0x0 2.--3. "SPICKSEL,SPICKSEL" "0,1,2,3" bitfld.long 0x0 0.--1. "SITP,SITP" "0,1,2,3" line.long 0x4 "CH7CFGR2,CH7CFGR2" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,OFFSET" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,DTRBS" line.long 0x8 "CH7AWSCDR,CH7AWSCDR" bitfld.long 0x8 22.--23. "AWFORD,AWFORD" "0,1,2,3" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,AWFOSR" hexmask.long.byte 0x8 12.--15. 1. "BKSCD,BKSCD" hexmask.long.byte 0x8 0.--7. 1. "SCDT,SCDT" line.long 0xC "CH7WDATR,CH7WDATR" hexmask.long.word 0xC 0.--15. 1. "WDATA,WDATA" line.long 0x10 "CH7DATINR,CH7DATINR" hexmask.long.word 0x10 16.--31. 1. "INDAT1,INDAT1" hexmask.long.word 0x10 0.--15. 1. "INDAT0,INDAT0" line.long 0x14 "CH7DLYR,channel y delay register" hexmask.long.byte 0x14 0.--5. 1. "PLSSKP,PLSSKP" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT0CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT0JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT0FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT0AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x130++0xB line.long 0x0 "DFSDM_FLT0EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT0CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT1CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT1CHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT1FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT1AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x1B0++0xB line.long 0x0 "DFSDM_FLT1EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT1CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT2CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT2JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT2FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT2AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x230++0xB line.long 0x0 "DFSDM_FLT2EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT2CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1,control register 1" bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode" "0,1" bitfld.long 0x0 29. "FAST,Fast conversion mode selection for" "0,1" bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously" "0,1" bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular" "0,1" bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the" "0,1" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge" "0,1,2,3" newline bitfld.long 0x0 8.--10. "JEXTSEL,Trigger signal selection for launching" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the" "0,1" bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected" "0,1" bitfld.long 0x0 3. "JSYNC,Launch an injected conversion" "0,1" bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group" "0,1" bitfld.long 0x0 0. "DFEN,DFSDM enable" "0,1" line.long 0x4 "DFSDM_FLT3CR2,control register 2" hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel" bitfld.long 0x4 6. "CKABIE,Clock absence interrupt" "0,1" bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt" "0,1" bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt" "0,1" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt" "0,1" bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt" "0,1" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt" "0,1" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR,interrupt and status register" hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" bitfld.long 0x0 14. "RCIP,Regular conversion in progress" "0,1" bitfld.long 0x0 13. "JCIP,Injected conversion in progress" "0,1" bitfld.long 0x0 4. "AWDF,Analog watchdog" "0,1" bitfld.long 0x0 3. "ROVRF,Regular conversion overrun" "0,1" bitfld.long 0x0 2. "JOVRF,Injected conversion overrun" "0,1" bitfld.long 0x0 1. "REOCF,End of regular conversion" "0,1" newline bitfld.long 0x0 0. "JEOCF,End of injected conversion" "0,1" group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR,interrupt flag clear register" hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence" bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun" "0,1" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun" "0,1" line.long 0x4 "DFSDM_FLT3JCHGR,injected channel group selection" hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group" line.long 0x8 "DFSDM_FLT3FCR,filter control register" bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio" hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR,data register for injected" hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR,data register for the regular" hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion" bitfld.long 0x4 4. "RPEND,Regular channel pending" "0,1" bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR,analog watchdog high threshold" hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog" line.long 0x4 "DFSDM_FLT3AWLTR,analog watchdog low threshold" hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR,analog watchdog status" hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR,analog watchdog clear flag" hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold" rgroup.long 0x2B0++0xB line.long 0x0 "DFSDM_FLT3EXMAX,Extremes detector maximum" hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3EXMIN,Extremes detector minimum" hexmask.long.tbyte 0x4 8.--31. 1. "EXMIN,EXMIN" bitfld.long 0x4 0.--2. "EXMINCH,Extremes detector minimum data" "0,1,2,3,4,5,6,7" line.long 0x8 "DFSDM_FLT3CNVTIMR,conversion timer register" hexmask.long 0x8 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t" tree.end endif sif (cpuis("STM32H7A3*")) tree "DFSDM1" base ad:0x40017800 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,DFSDM channel 0 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH0CFGR2,DFSDM channel 0 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH0AWSCDR,DFSDM channel 0 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,DFSDM channel 0 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,DFSDM channel 0 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH0DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,DFSDM channel 1 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH1CFGR2,DFSDM channel 1 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH1AWSCDR,DFSDM channel 1 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,DFSDM channel 1 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,DFSDM channel 1 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH1DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,DFSDM channel 2 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH2CFGR2,DFSDM channel 2 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH2AWSCDR,DFSDM channel 2 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,DFSDM channel 2 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,DFSDM channel 2 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH2DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,DFSDM channel 3 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH3CFGR2,DFSDM channel 3 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH3AWSCDR,DFSDM channel 3 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,DFSDM channel 3 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,DFSDM channel 3 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH3DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x80++0xB line.long 0x0 "DFSDM_CH4CFGR1,DFSDM channel 4 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH4CFGR2,DFSDM channel 4 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH4AWSCDR,DFSDM channel 4 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x8C++0x3 line.long 0x0 "DFSDM_CH4WDATR,DFSDM channel 4 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x90++0x7 line.long 0x0 "DFSDM_CH4DATINR,DFSDM channel 4 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH4DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xA0++0xB line.long 0x0 "DFSDM_CH5CFGR1,DFSDM channel 5 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH5CFGR2,DFSDM channel 5 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH5AWSCDR,DFSDM channel 5 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xAC++0x3 line.long 0x0 "DFSDM_CH5WDATR,DFSDM channel 5 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xB0++0x7 line.long 0x0 "DFSDM_CH5DATINR,DFSDM channel 5 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH5DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xC0++0xB line.long 0x0 "DFSDM_CH6CFGR1,DFSDM channel 6 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH6CFGR2,DFSDM channel 6 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH6AWSCDR,DFSDM channel 6 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xCC++0x3 line.long 0x0 "DFSDM_CH6WDATR,DFSDM channel 6 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xD0++0x7 line.long 0x0 "DFSDM_CH6DATINR,DFSDM channel 6 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH6DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xE0++0xB line.long 0x0 "DFSDM_CH7CFGR1,DFSDM channel 7 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH7CFGR2,DFSDM channel 7 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH7AWSCDR,DFSDM channel 7 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xEC++0x3 line.long 0x0 "DFSDM_CH7WDATR,DFSDM channel 7 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xF0++0x7 line.long 0x0 "DFSDM_CH7DATINR,DFSDM channel 7 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH7DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT0CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT0JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT0FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT0AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT1CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT1JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT1FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT1AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT2CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT2JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT2FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT2AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x230++0x3 line.long 0x0 "DFSDM_FLT2EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x234++0x3 line.long 0x0 "DFSDM_FLT2EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x238++0x3 line.long 0x0 "DFSDM_FLT2CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT3CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT3JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT3FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT3AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x2B0++0x3 line.long 0x0 "DFSDM_FLT3EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x2B4++0x3 line.long 0x0 "DFSDM_FLT3EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x2B8++0x3 line.long 0x0 "DFSDM_FLT3CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x300++0x7 line.long 0x0 "DFSDM_FLT4CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT4CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x308++0x3 line.long 0x0 "DFSDM_FLT4ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x30C++0xB line.long 0x0 "DFSDM_FLT4ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT4JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT4FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x318++0x7 line.long 0x0 "DFSDM_FLT4JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT4RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x320++0x7 line.long 0x0 "DFSDM_FLT4AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT4AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x328++0x3 line.long 0x0 "DFSDM_FLT4AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x32C++0x3 line.long 0x0 "DFSDM_FLT4AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x330++0x3 line.long 0x0 "DFSDM_FLT4EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x334++0x3 line.long 0x0 "DFSDM_FLT4EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x338++0x3 line.long 0x0 "DFSDM_FLT4CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x380++0x7 line.long 0x0 "DFSDM_FLT5CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT5CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x388++0x3 line.long 0x0 "DFSDM_FLT5ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x38C++0xB line.long 0x0 "DFSDM_FLT5ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT5JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT5FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x398++0x7 line.long 0x0 "DFSDM_FLT5JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT5RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x3A0++0x7 line.long 0x0 "DFSDM_FLT5AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT5AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x3A8++0x3 line.long 0x0 "DFSDM_FLT5AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x3AC++0x3 line.long 0x0 "DFSDM_FLT5AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x3B0++0x3 line.long 0x0 "DFSDM_FLT5EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x3B4++0x3 line.long 0x0 "DFSDM_FLT5EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x3B8++0x3 line.long 0x0 "DFSDM_FLT5CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x400++0x7 line.long 0x0 "DFSDM_FLT6CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT6CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x408++0x3 line.long 0x0 "DFSDM_FLT6ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x40C++0xB line.long 0x0 "DFSDM_FLT6ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT6JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT6FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x418++0x7 line.long 0x0 "DFSDM_FLT6JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT6RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x420++0x7 line.long 0x0 "DFSDM_FLT6AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT6AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x428++0x3 line.long 0x0 "DFSDM_FLT6AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x42C++0x3 line.long 0x0 "DFSDM_FLT6AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x430++0x3 line.long 0x0 "DFSDM_FLT6EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x434++0x3 line.long 0x0 "DFSDM_FLT6EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x438++0x3 line.long 0x0 "DFSDM_FLT6CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x480++0x7 line.long 0x0 "DFSDM_FLT7CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT7CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x488++0x3 line.long 0x0 "DFSDM_FLT7ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x48C++0xB line.long 0x0 "DFSDM_FLT7ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT7JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT7FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x498++0x7 line.long 0x0 "DFSDM_FLT7JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT7RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x4A0++0x7 line.long 0x0 "DFSDM_FLT7AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT7AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x4A8++0x3 line.long 0x0 "DFSDM_FLT7AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x4AC++0x3 line.long 0x0 "DFSDM_FLT7AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x4B0++0x3 line.long 0x0 "DFSDM_FLT7EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x4B4++0x3 line.long 0x0 "DFSDM_FLT7EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x4B8++0x3 line.long 0x0 "DFSDM_FLT7CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" tree.end tree "DFSDM2" base ad:0x58006C00 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,DFSDM channel 0 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH0CFGR2,DFSDM channel 0 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH0AWSCDR,DFSDM channel 0 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,DFSDM channel 0 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,DFSDM channel 0 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH0DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,DFSDM channel 1 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH1CFGR2,DFSDM channel 1 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH1AWSCDR,DFSDM channel 1 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,DFSDM channel 1 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,DFSDM channel 1 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH1DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,DFSDM channel 2 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH2CFGR2,DFSDM channel 2 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH2AWSCDR,DFSDM channel 2 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,DFSDM channel 2 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,DFSDM channel 2 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH2DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,DFSDM channel 3 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH3CFGR2,DFSDM channel 3 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH3AWSCDR,DFSDM channel 3 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,DFSDM channel 3 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,DFSDM channel 3 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH3DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x80++0xB line.long 0x0 "DFSDM_CH4CFGR1,DFSDM channel 4 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH4CFGR2,DFSDM channel 4 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH4AWSCDR,DFSDM channel 4 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x8C++0x3 line.long 0x0 "DFSDM_CH4WDATR,DFSDM channel 4 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x90++0x7 line.long 0x0 "DFSDM_CH4DATINR,DFSDM channel 4 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH4DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xA0++0xB line.long 0x0 "DFSDM_CH5CFGR1,DFSDM channel 5 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH5CFGR2,DFSDM channel 5 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH5AWSCDR,DFSDM channel 5 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xAC++0x3 line.long 0x0 "DFSDM_CH5WDATR,DFSDM channel 5 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xB0++0x7 line.long 0x0 "DFSDM_CH5DATINR,DFSDM channel 5 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH5DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xC0++0xB line.long 0x0 "DFSDM_CH6CFGR1,DFSDM channel 6 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH6CFGR2,DFSDM channel 6 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH6AWSCDR,DFSDM channel 6 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xCC++0x3 line.long 0x0 "DFSDM_CH6WDATR,DFSDM channel 6 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xD0++0x7 line.long 0x0 "DFSDM_CH6DATINR,DFSDM channel 6 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH6DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xE0++0xB line.long 0x0 "DFSDM_CH7CFGR1,DFSDM channel 7 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH7CFGR2,DFSDM channel 7 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH7AWSCDR,DFSDM channel 7 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xEC++0x3 line.long 0x0 "DFSDM_CH7WDATR,DFSDM channel 7 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xF0++0x7 line.long 0x0 "DFSDM_CH7DATINR,DFSDM channel 7 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH7DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT0CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT0JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT0FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT0RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT0AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT1CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT1JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT1FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT1RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT1AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT2CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT2JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT2FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT2RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT2AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x230++0x3 line.long 0x0 "DFSDM_FLT2EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x234++0x3 line.long 0x0 "DFSDM_FLT2EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x238++0x3 line.long 0x0 "DFSDM_FLT2CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT3CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT3JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT3FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT3RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT3AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x2B0++0x3 line.long 0x0 "DFSDM_FLT3EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x2B4++0x3 line.long 0x0 "DFSDM_FLT3EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x2B8++0x3 line.long 0x0 "DFSDM_FLT3CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x300++0x7 line.long 0x0 "DFSDM_FLT4CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT4CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x308++0x3 line.long 0x0 "DFSDM_FLT4ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x30C++0xB line.long 0x0 "DFSDM_FLT4ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT4JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT4FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x318++0x7 line.long 0x0 "DFSDM_FLT4JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT4RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x320++0x7 line.long 0x0 "DFSDM_FLT4AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT4AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x328++0x3 line.long 0x0 "DFSDM_FLT4AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x32C++0x3 line.long 0x0 "DFSDM_FLT4AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x330++0x3 line.long 0x0 "DFSDM_FLT4EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x334++0x3 line.long 0x0 "DFSDM_FLT4EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x338++0x3 line.long 0x0 "DFSDM_FLT4CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x380++0x7 line.long 0x0 "DFSDM_FLT5CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT5CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x388++0x3 line.long 0x0 "DFSDM_FLT5ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x38C++0xB line.long 0x0 "DFSDM_FLT5ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT5JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT5FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x398++0x7 line.long 0x0 "DFSDM_FLT5JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT5RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x3A0++0x7 line.long 0x0 "DFSDM_FLT5AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT5AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x3A8++0x3 line.long 0x0 "DFSDM_FLT5AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x3AC++0x3 line.long 0x0 "DFSDM_FLT5AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x3B0++0x3 line.long 0x0 "DFSDM_FLT5EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x3B4++0x3 line.long 0x0 "DFSDM_FLT5EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x3B8++0x3 line.long 0x0 "DFSDM_FLT5CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x400++0x7 line.long 0x0 "DFSDM_FLT6CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT6CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x408++0x3 line.long 0x0 "DFSDM_FLT6ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x40C++0xB line.long 0x0 "DFSDM_FLT6ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT6JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT6FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x418++0x7 line.long 0x0 "DFSDM_FLT6JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT6RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x420++0x7 line.long 0x0 "DFSDM_FLT6AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT6AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x428++0x3 line.long 0x0 "DFSDM_FLT6AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x42C++0x3 line.long 0x0 "DFSDM_FLT6AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x430++0x3 line.long 0x0 "DFSDM_FLT6EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x434++0x3 line.long 0x0 "DFSDM_FLT6EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x438++0x3 line.long 0x0 "DFSDM_FLT6CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x480++0x7 line.long 0x0 "DFSDM_FLT7CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline bitfld.long 0x0 24.--26. "RCH,Regular channel selection" "0: Channel 0 is selected as the regular channel,1: Channel 1 is selected as the regular channel,?,?,?,?,?,7: Channel 7 is selected as the regular channel" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT7CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x488++0x3 line.long 0x0 "DFSDM_FLT7ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x48C++0xB line.long 0x0 "DFSDM_FLT7ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT7JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT7FCR," bitfld.long 0x8 29.--31. "FORD,Sinc filter order" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type,4: Sinc4 filter type,5: Sinc5 filter type,?,?" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x498++0x7 line.long 0x0 "DFSDM_FLT7JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" bitfld.long 0x0 0.--2. "JDATACH,Injected channel most recently converted" "0,1,2,3,4,5,6,7" line.long 0x4 "DFSDM_FLT7RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline bitfld.long 0x4 0.--2. "RDATACH,Regular channel most recently converted" "0,1,2,3,4,5,6,7" group.long 0x4A0++0x7 line.long 0x0 "DFSDM_FLT7AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT7AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x4A8++0x3 line.long 0x0 "DFSDM_FLT7AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x4AC++0x3 line.long 0x0 "DFSDM_FLT7AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x4B0++0x3 line.long 0x0 "DFSDM_FLT7EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" bitfld.long 0x0 0.--2. "EXMAXCH,Extremes detector maximum data channel." "0,1,2,3,4,5,6,7" group.long 0x4B4++0x3 line.long 0x0 "DFSDM_FLT7EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" rbitfld.long 0x0 0.--2. "EXMINCH,Extremes detector minimum data channel" "0,1,2,3,4,5,6,7" rgroup.long 0x4B8++0x3 line.long 0x0 "DFSDM_FLT7CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" tree.end endif sif (cpuis("STM32H7B0*")) tree "DFSDM1" base ad:0x40017800 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,DFSDM channel 0 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH0CFGR2,DFSDM channel 0 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH0AWSCDR,DFSDM channel 0 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,DFSDM channel 0 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,DFSDM channel 0 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH0DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,DFSDM channel 1 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH1CFGR2,DFSDM channel 1 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH1AWSCDR,DFSDM channel 1 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,DFSDM channel 1 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,DFSDM channel 1 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH1DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,DFSDM channel 2 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH2CFGR2,DFSDM channel 2 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH2AWSCDR,DFSDM channel 2 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,DFSDM channel 2 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,DFSDM channel 2 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH2DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,DFSDM channel 3 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH3CFGR2,DFSDM channel 3 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH3AWSCDR,DFSDM channel 3 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,DFSDM channel 3 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,DFSDM channel 3 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH3DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x80++0xB line.long 0x0 "DFSDM_CH4CFGR1,DFSDM channel 4 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH4CFGR2,DFSDM channel 4 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH4AWSCDR,DFSDM channel 4 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x8C++0x3 line.long 0x0 "DFSDM_CH4WDATR,DFSDM channel 4 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x90++0x7 line.long 0x0 "DFSDM_CH4DATINR,DFSDM channel 4 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH4DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xA0++0xB line.long 0x0 "DFSDM_CH5CFGR1,DFSDM channel 5 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH5CFGR2,DFSDM channel 5 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH5AWSCDR,DFSDM channel 5 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xAC++0x3 line.long 0x0 "DFSDM_CH5WDATR,DFSDM channel 5 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xB0++0x7 line.long 0x0 "DFSDM_CH5DATINR,DFSDM channel 5 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH5DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xC0++0xB line.long 0x0 "DFSDM_CH6CFGR1,DFSDM channel 6 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH6CFGR2,DFSDM channel 6 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH6AWSCDR,DFSDM channel 6 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xCC++0x3 line.long 0x0 "DFSDM_CH6WDATR,DFSDM channel 6 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xD0++0x7 line.long 0x0 "DFSDM_CH6DATINR,DFSDM channel 6 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH6DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xE0++0xB line.long 0x0 "DFSDM_CH7CFGR1,DFSDM channel 7 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH7CFGR2,DFSDM channel 7 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH7AWSCDR,DFSDM channel 7 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xEC++0x3 line.long 0x0 "DFSDM_CH7WDATR,DFSDM channel 7 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xF0++0x7 line.long 0x0 "DFSDM_CH7DATINR,DFSDM channel 7 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH7DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT0CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT0JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT0FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT0RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT0AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT1CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT1JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT1FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT1RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT1AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT2CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT2JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT2FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT2RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT2AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x230++0x3 line.long 0x0 "DFSDM_FLT2EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x234++0x3 line.long 0x0 "DFSDM_FLT2EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x238++0x3 line.long 0x0 "DFSDM_FLT2CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT3CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT3JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT3FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT3RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT3AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x2B0++0x3 line.long 0x0 "DFSDM_FLT3EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x2B4++0x3 line.long 0x0 "DFSDM_FLT3EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x2B8++0x3 line.long 0x0 "DFSDM_FLT3CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x300++0x7 line.long 0x0 "DFSDM_FLT4CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT4CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x308++0x3 line.long 0x0 "DFSDM_FLT4ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x30C++0xB line.long 0x0 "DFSDM_FLT4ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT4JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT4FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x318++0x7 line.long 0x0 "DFSDM_FLT4JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT4RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x320++0x7 line.long 0x0 "DFSDM_FLT4AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT4AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x328++0x3 line.long 0x0 "DFSDM_FLT4AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x32C++0x3 line.long 0x0 "DFSDM_FLT4AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x330++0x3 line.long 0x0 "DFSDM_FLT4EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x334++0x3 line.long 0x0 "DFSDM_FLT4EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x338++0x3 line.long 0x0 "DFSDM_FLT4CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x380++0x7 line.long 0x0 "DFSDM_FLT5CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT5CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x388++0x3 line.long 0x0 "DFSDM_FLT5ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x38C++0xB line.long 0x0 "DFSDM_FLT5ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT5JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT5FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x398++0x7 line.long 0x0 "DFSDM_FLT5JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT5RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x3A0++0x7 line.long 0x0 "DFSDM_FLT5AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT5AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x3A8++0x3 line.long 0x0 "DFSDM_FLT5AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x3AC++0x3 line.long 0x0 "DFSDM_FLT5AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x3B0++0x3 line.long 0x0 "DFSDM_FLT5EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x3B4++0x3 line.long 0x0 "DFSDM_FLT5EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x3B8++0x3 line.long 0x0 "DFSDM_FLT5CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x400++0x7 line.long 0x0 "DFSDM_FLT6CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT6CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x408++0x3 line.long 0x0 "DFSDM_FLT6ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x40C++0xB line.long 0x0 "DFSDM_FLT6ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT6JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT6FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x418++0x7 line.long 0x0 "DFSDM_FLT6JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT6RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x420++0x7 line.long 0x0 "DFSDM_FLT6AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT6AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x428++0x3 line.long 0x0 "DFSDM_FLT6AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x42C++0x3 line.long 0x0 "DFSDM_FLT6AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x430++0x3 line.long 0x0 "DFSDM_FLT6EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x434++0x3 line.long 0x0 "DFSDM_FLT6EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x438++0x3 line.long 0x0 "DFSDM_FLT6CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x480++0x7 line.long 0x0 "DFSDM_FLT7CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT7CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x488++0x3 line.long 0x0 "DFSDM_FLT7ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x48C++0xB line.long 0x0 "DFSDM_FLT7ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT7JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT7FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x498++0x7 line.long 0x0 "DFSDM_FLT7JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT7RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x4A0++0x7 line.long 0x0 "DFSDM_FLT7AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT7AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x4A8++0x3 line.long 0x0 "DFSDM_FLT7AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x4AC++0x3 line.long 0x0 "DFSDM_FLT7AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x4B0++0x3 line.long 0x0 "DFSDM_FLT7EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x4B4++0x3 line.long 0x0 "DFSDM_FLT7EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x4B8++0x3 line.long 0x0 "DFSDM_FLT7CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" tree.end tree "DFSDM2" base ad:0x58006C00 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,DFSDM channel 0 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH0CFGR2,DFSDM channel 0 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH0AWSCDR,DFSDM channel 0 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,DFSDM channel 0 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,DFSDM channel 0 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH0DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,DFSDM channel 1 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH1CFGR2,DFSDM channel 1 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH1AWSCDR,DFSDM channel 1 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,DFSDM channel 1 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,DFSDM channel 1 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH1DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,DFSDM channel 2 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH2CFGR2,DFSDM channel 2 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH2AWSCDR,DFSDM channel 2 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,DFSDM channel 2 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,DFSDM channel 2 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH2DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,DFSDM channel 3 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH3CFGR2,DFSDM channel 3 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH3AWSCDR,DFSDM channel 3 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,DFSDM channel 3 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,DFSDM channel 3 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH3DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x80++0xB line.long 0x0 "DFSDM_CH4CFGR1,DFSDM channel 4 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH4CFGR2,DFSDM channel 4 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH4AWSCDR,DFSDM channel 4 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x8C++0x3 line.long 0x0 "DFSDM_CH4WDATR,DFSDM channel 4 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x90++0x7 line.long 0x0 "DFSDM_CH4DATINR,DFSDM channel 4 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH4DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xA0++0xB line.long 0x0 "DFSDM_CH5CFGR1,DFSDM channel 5 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH5CFGR2,DFSDM channel 5 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH5AWSCDR,DFSDM channel 5 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xAC++0x3 line.long 0x0 "DFSDM_CH5WDATR,DFSDM channel 5 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xB0++0x7 line.long 0x0 "DFSDM_CH5DATINR,DFSDM channel 5 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH5DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xC0++0xB line.long 0x0 "DFSDM_CH6CFGR1,DFSDM channel 6 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH6CFGR2,DFSDM channel 6 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH6AWSCDR,DFSDM channel 6 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xCC++0x3 line.long 0x0 "DFSDM_CH6WDATR,DFSDM channel 6 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xD0++0x7 line.long 0x0 "DFSDM_CH6DATINR,DFSDM channel 6 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH6DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xE0++0xB line.long 0x0 "DFSDM_CH7CFGR1,DFSDM channel 7 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH7CFGR2,DFSDM channel 7 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH7AWSCDR,DFSDM channel 7 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xEC++0x3 line.long 0x0 "DFSDM_CH7WDATR,DFSDM channel 7 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xF0++0x7 line.long 0x0 "DFSDM_CH7DATINR,DFSDM channel 7 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH7DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT0CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT0JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT0FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT0RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT0AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT1CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT1JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT1FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT1RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT1AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT2CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT2JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT2FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT2RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT2AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x230++0x3 line.long 0x0 "DFSDM_FLT2EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x234++0x3 line.long 0x0 "DFSDM_FLT2EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x238++0x3 line.long 0x0 "DFSDM_FLT2CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT3CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT3JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT3FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT3RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT3AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x2B0++0x3 line.long 0x0 "DFSDM_FLT3EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x2B4++0x3 line.long 0x0 "DFSDM_FLT3EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x2B8++0x3 line.long 0x0 "DFSDM_FLT3CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x300++0x7 line.long 0x0 "DFSDM_FLT4CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT4CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x308++0x3 line.long 0x0 "DFSDM_FLT4ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x30C++0xB line.long 0x0 "DFSDM_FLT4ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT4JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT4FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x318++0x7 line.long 0x0 "DFSDM_FLT4JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT4RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x320++0x7 line.long 0x0 "DFSDM_FLT4AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT4AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x328++0x3 line.long 0x0 "DFSDM_FLT4AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x32C++0x3 line.long 0x0 "DFSDM_FLT4AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x330++0x3 line.long 0x0 "DFSDM_FLT4EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x334++0x3 line.long 0x0 "DFSDM_FLT4EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x338++0x3 line.long 0x0 "DFSDM_FLT4CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x380++0x7 line.long 0x0 "DFSDM_FLT5CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT5CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x388++0x3 line.long 0x0 "DFSDM_FLT5ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x38C++0xB line.long 0x0 "DFSDM_FLT5ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT5JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT5FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x398++0x7 line.long 0x0 "DFSDM_FLT5JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT5RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x3A0++0x7 line.long 0x0 "DFSDM_FLT5AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT5AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x3A8++0x3 line.long 0x0 "DFSDM_FLT5AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x3AC++0x3 line.long 0x0 "DFSDM_FLT5AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x3B0++0x3 line.long 0x0 "DFSDM_FLT5EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x3B4++0x3 line.long 0x0 "DFSDM_FLT5EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x3B8++0x3 line.long 0x0 "DFSDM_FLT5CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x400++0x7 line.long 0x0 "DFSDM_FLT6CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT6CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x408++0x3 line.long 0x0 "DFSDM_FLT6ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x40C++0xB line.long 0x0 "DFSDM_FLT6ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT6JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT6FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x418++0x7 line.long 0x0 "DFSDM_FLT6JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT6RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x420++0x7 line.long 0x0 "DFSDM_FLT6AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT6AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x428++0x3 line.long 0x0 "DFSDM_FLT6AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x42C++0x3 line.long 0x0 "DFSDM_FLT6AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x430++0x3 line.long 0x0 "DFSDM_FLT6EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x434++0x3 line.long 0x0 "DFSDM_FLT6EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x438++0x3 line.long 0x0 "DFSDM_FLT6CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x480++0x7 line.long 0x0 "DFSDM_FLT7CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT7CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x488++0x3 line.long 0x0 "DFSDM_FLT7ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x48C++0xB line.long 0x0 "DFSDM_FLT7ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT7JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT7FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x498++0x7 line.long 0x0 "DFSDM_FLT7JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT7RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x4A0++0x7 line.long 0x0 "DFSDM_FLT7AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT7AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x4A8++0x3 line.long 0x0 "DFSDM_FLT7AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x4AC++0x3 line.long 0x0 "DFSDM_FLT7AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x4B0++0x3 line.long 0x0 "DFSDM_FLT7EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x4B4++0x3 line.long 0x0 "DFSDM_FLT7EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x4B8++0x3 line.long 0x0 "DFSDM_FLT7CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" tree.end endif sif (cpuis("STM32H7B3*")) tree "DFSDM1" base ad:0x40017800 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,DFSDM channel 0 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH0CFGR2,DFSDM channel 0 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH0AWSCDR,DFSDM channel 0 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,DFSDM channel 0 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,DFSDM channel 0 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH0DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,DFSDM channel 1 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH1CFGR2,DFSDM channel 1 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH1AWSCDR,DFSDM channel 1 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,DFSDM channel 1 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,DFSDM channel 1 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH1DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,DFSDM channel 2 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH2CFGR2,DFSDM channel 2 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH2AWSCDR,DFSDM channel 2 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,DFSDM channel 2 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,DFSDM channel 2 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH2DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,DFSDM channel 3 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH3CFGR2,DFSDM channel 3 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH3AWSCDR,DFSDM channel 3 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,DFSDM channel 3 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,DFSDM channel 3 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH3DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x80++0xB line.long 0x0 "DFSDM_CH4CFGR1,DFSDM channel 4 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH4CFGR2,DFSDM channel 4 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH4AWSCDR,DFSDM channel 4 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x8C++0x3 line.long 0x0 "DFSDM_CH4WDATR,DFSDM channel 4 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x90++0x7 line.long 0x0 "DFSDM_CH4DATINR,DFSDM channel 4 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH4DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xA0++0xB line.long 0x0 "DFSDM_CH5CFGR1,DFSDM channel 5 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH5CFGR2,DFSDM channel 5 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH5AWSCDR,DFSDM channel 5 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xAC++0x3 line.long 0x0 "DFSDM_CH5WDATR,DFSDM channel 5 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xB0++0x7 line.long 0x0 "DFSDM_CH5DATINR,DFSDM channel 5 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH5DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xC0++0xB line.long 0x0 "DFSDM_CH6CFGR1,DFSDM channel 6 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH6CFGR2,DFSDM channel 6 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH6AWSCDR,DFSDM channel 6 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xCC++0x3 line.long 0x0 "DFSDM_CH6WDATR,DFSDM channel 6 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xD0++0x7 line.long 0x0 "DFSDM_CH6DATINR,DFSDM channel 6 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH6DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xE0++0xB line.long 0x0 "DFSDM_CH7CFGR1,DFSDM channel 7 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH7CFGR2,DFSDM channel 7 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH7AWSCDR,DFSDM channel 7 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xEC++0x3 line.long 0x0 "DFSDM_CH7WDATR,DFSDM channel 7 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xF0++0x7 line.long 0x0 "DFSDM_CH7DATINR,DFSDM channel 7 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH7DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT0CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT0JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT0FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT0RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT0AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT1CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT1JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT1FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT1RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT1AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT2CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT2JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT2FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT2RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT2AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x230++0x3 line.long 0x0 "DFSDM_FLT2EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x234++0x3 line.long 0x0 "DFSDM_FLT2EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x238++0x3 line.long 0x0 "DFSDM_FLT2CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT3CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT3JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT3FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT3RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT3AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x2B0++0x3 line.long 0x0 "DFSDM_FLT3EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x2B4++0x3 line.long 0x0 "DFSDM_FLT3EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x2B8++0x3 line.long 0x0 "DFSDM_FLT3CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x300++0x7 line.long 0x0 "DFSDM_FLT4CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT4CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x308++0x3 line.long 0x0 "DFSDM_FLT4ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x30C++0xB line.long 0x0 "DFSDM_FLT4ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT4JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT4FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x318++0x7 line.long 0x0 "DFSDM_FLT4JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT4RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x320++0x7 line.long 0x0 "DFSDM_FLT4AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT4AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x328++0x3 line.long 0x0 "DFSDM_FLT4AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x32C++0x3 line.long 0x0 "DFSDM_FLT4AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x330++0x3 line.long 0x0 "DFSDM_FLT4EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x334++0x3 line.long 0x0 "DFSDM_FLT4EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x338++0x3 line.long 0x0 "DFSDM_FLT4CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x380++0x7 line.long 0x0 "DFSDM_FLT5CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT5CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x388++0x3 line.long 0x0 "DFSDM_FLT5ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x38C++0xB line.long 0x0 "DFSDM_FLT5ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT5JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT5FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x398++0x7 line.long 0x0 "DFSDM_FLT5JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT5RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x3A0++0x7 line.long 0x0 "DFSDM_FLT5AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT5AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x3A8++0x3 line.long 0x0 "DFSDM_FLT5AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x3AC++0x3 line.long 0x0 "DFSDM_FLT5AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x3B0++0x3 line.long 0x0 "DFSDM_FLT5EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x3B4++0x3 line.long 0x0 "DFSDM_FLT5EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x3B8++0x3 line.long 0x0 "DFSDM_FLT5CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x400++0x7 line.long 0x0 "DFSDM_FLT6CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT6CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x408++0x3 line.long 0x0 "DFSDM_FLT6ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x40C++0xB line.long 0x0 "DFSDM_FLT6ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT6JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT6FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x418++0x7 line.long 0x0 "DFSDM_FLT6JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT6RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x420++0x7 line.long 0x0 "DFSDM_FLT6AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT6AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x428++0x3 line.long 0x0 "DFSDM_FLT6AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x42C++0x3 line.long 0x0 "DFSDM_FLT6AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x430++0x3 line.long 0x0 "DFSDM_FLT6EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x434++0x3 line.long 0x0 "DFSDM_FLT6EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x438++0x3 line.long 0x0 "DFSDM_FLT6CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x480++0x7 line.long 0x0 "DFSDM_FLT7CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT7CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x488++0x3 line.long 0x0 "DFSDM_FLT7ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x48C++0xB line.long 0x0 "DFSDM_FLT7ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT7JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT7FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x498++0x7 line.long 0x0 "DFSDM_FLT7JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT7RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x4A0++0x7 line.long 0x0 "DFSDM_FLT7AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT7AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x4A8++0x3 line.long 0x0 "DFSDM_FLT7AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x4AC++0x3 line.long 0x0 "DFSDM_FLT7AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x4B0++0x3 line.long 0x0 "DFSDM_FLT7EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x4B4++0x3 line.long 0x0 "DFSDM_FLT7EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x4B8++0x3 line.long 0x0 "DFSDM_FLT7CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" tree.end tree "DFSDM2" base ad:0x58006C00 group.long 0x0++0xB line.long 0x0 "DFSDM_CH0CFGR1,DFSDM channel 0 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH0CFGR2,DFSDM channel 0 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH0AWSCDR,DFSDM channel 0 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xC++0x3 line.long 0x0 "DFSDM_CH0WDATR,DFSDM channel 0 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x10++0x7 line.long 0x0 "DFSDM_CH0DATINR,DFSDM channel 0 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH0DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x20++0xB line.long 0x0 "DFSDM_CH1CFGR1,DFSDM channel 1 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH1CFGR2,DFSDM channel 1 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH1AWSCDR,DFSDM channel 1 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x2C++0x3 line.long 0x0 "DFSDM_CH1WDATR,DFSDM channel 1 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x30++0x7 line.long 0x0 "DFSDM_CH1DATINR,DFSDM channel 1 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH1DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x40++0xB line.long 0x0 "DFSDM_CH2CFGR1,DFSDM channel 2 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH2CFGR2,DFSDM channel 2 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH2AWSCDR,DFSDM channel 2 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x4C++0x3 line.long 0x0 "DFSDM_CH2WDATR,DFSDM channel 2 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x50++0x7 line.long 0x0 "DFSDM_CH2DATINR,DFSDM channel 2 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH2DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x60++0xB line.long 0x0 "DFSDM_CH3CFGR1,DFSDM channel 3 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH3CFGR2,DFSDM channel 3 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH3AWSCDR,DFSDM channel 3 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x6C++0x3 line.long 0x0 "DFSDM_CH3WDATR,DFSDM channel 3 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x70++0x7 line.long 0x0 "DFSDM_CH3DATINR,DFSDM channel 3 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH3DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x80++0xB line.long 0x0 "DFSDM_CH4CFGR1,DFSDM channel 4 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH4CFGR2,DFSDM channel 4 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH4AWSCDR,DFSDM channel 4 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0x8C++0x3 line.long 0x0 "DFSDM_CH4WDATR,DFSDM channel 4 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0x90++0x7 line.long 0x0 "DFSDM_CH4DATINR,DFSDM channel 4 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH4DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xA0++0xB line.long 0x0 "DFSDM_CH5CFGR1,DFSDM channel 5 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH5CFGR2,DFSDM channel 5 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH5AWSCDR,DFSDM channel 5 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xAC++0x3 line.long 0x0 "DFSDM_CH5WDATR,DFSDM channel 5 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xB0++0x7 line.long 0x0 "DFSDM_CH5DATINR,DFSDM channel 5 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH5DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xC0++0xB line.long 0x0 "DFSDM_CH6CFGR1,DFSDM channel 6 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH6CFGR2,DFSDM channel 6 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH6AWSCDR,DFSDM channel 6 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xCC++0x3 line.long 0x0 "DFSDM_CH6WDATR,DFSDM channel 6 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xD0++0x7 line.long 0x0 "DFSDM_CH6DATINR,DFSDM channel 6 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH6DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0xE0++0xB line.long 0x0 "DFSDM_CH7CFGR1,DFSDM channel 7 configuration register" bitfld.long 0x0 31. "DFSDMEN,Global enable for DFSDM interface" "0: all registers DFSDM_FLTxISR are set to reset..,1: DFSDM interface enabled" bitfld.long 0x0 30. "CKOUTSRC,Output serial clock source selection" "0: Source for output clock is from system clock,1: Source for output clock is from audio clock" newline hexmask.long.byte 0x0 16.--23. 1. "CKOUTDIV,Output serial clock divider" bitfld.long 0x0 14.--15. "DATPACK,Data packing mode in DFSDM_CHyDATINR register." "0: Standard: input data in DFSDM_CHyDATINR register..,1: Interleaved: input data in DFSDM_CHyDATINR..,2: Dual: input data in DFSDM_CHyDATINR register are..,3: Reserved" newline bitfld.long 0x0 12.--13. "DATMPX,Input data multiplexer for channel y" "0: Data to channel y are taken from external serial..,1: Data to channel y are taken from internal analog..,2: Data to channel y are taken from internal..,3: Reserved" bitfld.long 0x0 8. "CHINSEL,Channel inputs selection" "0: Channel inputs are taken from pins of the same..,1: Channel inputs are taken from pins of the.." newline bitfld.long 0x0 7. "CHEN,Channel y enable" "0: Channel y disabled,1: Channel y enabled" bitfld.long 0x0 6. "CKABEN,Clock absence detector enable on channel y" "0: Clock absence detector disabled on channel y,1: Clock absence detector enabled on channel y" newline bitfld.long 0x0 5. "SCDEN,Short-circuit detector enable on channel y" "0: Input channel y will not be guarded by the..,1: Input channel y will be continuously guarded by.." bitfld.long 0x0 2.--3. "SPICKSEL,SPI clock select for channel y" "0: clock coming from external CKINy input -..,1: clock coming from internal CKOUT output -..,2: clock coming from internal CKOUT,3: clock coming from internal CKOUT output" newline bitfld.long 0x0 0.--1. "SITP,Serial interface type for channel y" "0: SPI with rising edge to strobe data,1: SPI with falling edge to strobe data,2: Manchester coded input on DATINy pin: rising..,3: Manchester coded input on DATINy pin: rising.." line.long 0x4 "DFSDM_CH7CFGR2,DFSDM channel 7 configuration register" hexmask.long.tbyte 0x4 8.--31. 1. "OFFSET,24-bit calibration offset for channel y" hexmask.long.byte 0x4 3.--7. 1. "DTRBS,Data right bit-shift for channel y" line.long 0x8 "DFSDM_CH7AWSCDR,DFSDM channel 7 analog watchdog and short-circuit detector register" bitfld.long 0x8 22.--23. "AWFORD,Analog watchdog Sinc filter order on channel y" "0: FastSinc filter type,1: Sinc1 filter type,2: Sinc2 filter type,3: Sinc3 filter type" hexmask.long.byte 0x8 16.--20. 1. "AWFOSR,Analog watchdog filter oversampling ratio (decimation rate) on channel y" newline hexmask.long.byte 0x8 12.--15. 1. "BKSCD,Break signal assignment for short-circuit detector on channel y" hexmask.long.byte 0x8 0.--7. 1. "SCDT,short-circuit detector threshold for channel y" rgroup.long 0xEC++0x3 line.long 0x0 "DFSDM_CH7WDATR,DFSDM channel 7 watchdog filter data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Input channel y watchdog data" group.long 0xF0++0x7 line.long 0x0 "DFSDM_CH7DATINR,DFSDM channel 7 data input register" hexmask.long.word 0x0 16.--31. 1. "INDAT1,Input data for channel y or channel y+1" hexmask.long.word 0x0 0.--15. 1. "INDAT0,Input data for channel y" line.long 0x4 "DFSDM_CH7DLYR," hexmask.long.byte 0x4 0.--5. 1. "PLSSKP,Pulses to skip for input data skipping function" group.long 0x100++0x7 line.long 0x0 "DFSDM_FLT0CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT0CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x108++0x3 line.long 0x0 "DFSDM_FLT0ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x10C++0xB line.long 0x0 "DFSDM_FLT0ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT0JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT0FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x118++0x7 line.long 0x0 "DFSDM_FLT0JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT0RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x120++0x7 line.long 0x0 "DFSDM_FLT0AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT0AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x128++0x3 line.long 0x0 "DFSDM_FLT0AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x12C++0x3 line.long 0x0 "DFSDM_FLT0AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x130++0x3 line.long 0x0 "DFSDM_FLT0EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x134++0x3 line.long 0x0 "DFSDM_FLT0EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x138++0x3 line.long 0x0 "DFSDM_FLT0CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x180++0x7 line.long 0x0 "DFSDM_FLT1CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT1CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x188++0x3 line.long 0x0 "DFSDM_FLT1ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x18C++0xB line.long 0x0 "DFSDM_FLT1ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT1JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT1FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x198++0x7 line.long 0x0 "DFSDM_FLT1JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT1RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x1A0++0x7 line.long 0x0 "DFSDM_FLT1AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT1AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x1A8++0x3 line.long 0x0 "DFSDM_FLT1AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x1AC++0x3 line.long 0x0 "DFSDM_FLT1AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x1B0++0x3 line.long 0x0 "DFSDM_FLT1EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x1B4++0x3 line.long 0x0 "DFSDM_FLT1EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x1B8++0x3 line.long 0x0 "DFSDM_FLT1CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x200++0x7 line.long 0x0 "DFSDM_FLT2CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT2CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x208++0x3 line.long 0x0 "DFSDM_FLT2ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x20C++0xB line.long 0x0 "DFSDM_FLT2ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT2JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT2FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x218++0x7 line.long 0x0 "DFSDM_FLT2JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT2RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x220++0x7 line.long 0x0 "DFSDM_FLT2AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT2AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x228++0x3 line.long 0x0 "DFSDM_FLT2AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x22C++0x3 line.long 0x0 "DFSDM_FLT2AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x230++0x3 line.long 0x0 "DFSDM_FLT2EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x234++0x3 line.long 0x0 "DFSDM_FLT2EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x238++0x3 line.long 0x0 "DFSDM_FLT2CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x280++0x7 line.long 0x0 "DFSDM_FLT3CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT3CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x288++0x3 line.long 0x0 "DFSDM_FLT3ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x28C++0xB line.long 0x0 "DFSDM_FLT3ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT3JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT3FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x298++0x7 line.long 0x0 "DFSDM_FLT3JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT3RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x2A0++0x7 line.long 0x0 "DFSDM_FLT3AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT3AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x2A8++0x3 line.long 0x0 "DFSDM_FLT3AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x2AC++0x3 line.long 0x0 "DFSDM_FLT3AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x2B0++0x3 line.long 0x0 "DFSDM_FLT3EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x2B4++0x3 line.long 0x0 "DFSDM_FLT3EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x2B8++0x3 line.long 0x0 "DFSDM_FLT3CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x300++0x7 line.long 0x0 "DFSDM_FLT4CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT4CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x308++0x3 line.long 0x0 "DFSDM_FLT4ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x30C++0xB line.long 0x0 "DFSDM_FLT4ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT4JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT4FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x318++0x7 line.long 0x0 "DFSDM_FLT4JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT4RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x320++0x7 line.long 0x0 "DFSDM_FLT4AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT4AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x328++0x3 line.long 0x0 "DFSDM_FLT4AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x32C++0x3 line.long 0x0 "DFSDM_FLT4AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x330++0x3 line.long 0x0 "DFSDM_FLT4EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x334++0x3 line.long 0x0 "DFSDM_FLT4EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x338++0x3 line.long 0x0 "DFSDM_FLT4CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x380++0x7 line.long 0x0 "DFSDM_FLT5CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT5CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x388++0x3 line.long 0x0 "DFSDM_FLT5ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x38C++0xB line.long 0x0 "DFSDM_FLT5ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT5JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT5FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x398++0x7 line.long 0x0 "DFSDM_FLT5JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT5RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x3A0++0x7 line.long 0x0 "DFSDM_FLT5AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT5AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x3A8++0x3 line.long 0x0 "DFSDM_FLT5AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x3AC++0x3 line.long 0x0 "DFSDM_FLT5AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x3B0++0x3 line.long 0x0 "DFSDM_FLT5EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x3B4++0x3 line.long 0x0 "DFSDM_FLT5EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x3B8++0x3 line.long 0x0 "DFSDM_FLT5CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x400++0x7 line.long 0x0 "DFSDM_FLT6CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT6CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x408++0x3 line.long 0x0 "DFSDM_FLT6ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x40C++0xB line.long 0x0 "DFSDM_FLT6ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT6JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT6FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x418++0x7 line.long 0x0 "DFSDM_FLT6JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT6RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x420++0x7 line.long 0x0 "DFSDM_FLT6AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT6AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x428++0x3 line.long 0x0 "DFSDM_FLT6AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x42C++0x3 line.long 0x0 "DFSDM_FLT6AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x430++0x3 line.long 0x0 "DFSDM_FLT6EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x434++0x3 line.long 0x0 "DFSDM_FLT6EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x438++0x3 line.long 0x0 "DFSDM_FLT6CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" group.long 0x480++0x7 line.long 0x0 "DFSDM_FLT7CR1," bitfld.long 0x0 30. "AWFSEL,Analog watchdog fast mode select" "0: Analog watchdog on data output value (after the..,1: Analog watchdog on channel transceivers value.." bitfld.long 0x0 29. "FAST,Fast conversion mode selection for regular conversions" "0: Fast conversion mode disabled,1: Fast conversion mode enabled" newline hexmask.long.byte 0x0 24.--27. 1. "RCH,Regular channel selection" bitfld.long 0x0 21. "RDMAEN,DMA channel enabled to read data for the regular conversion" "0: The DMA channel is not enabled to read regular..,1: The DMA channel is enabled to read regular data" newline bitfld.long 0x0 19. "RSYNC,Launch regular conversion synchronously with DFSDM_FLT0" "0: Do not launch a regular conversion synchronously..,1: Launch a regular conversion in this DFSDM_FLTx.." bitfld.long 0x0 18. "RCONT,Continuous mode selection for regular conversions" "0: The regular channel is converted just once for..,1: The regular channel is converted repeatedly.." newline bitfld.long 0x0 17. "RSWSTART,Software start of a conversion on the regular channel" "0: Writing '0' has no effect,1: Writing '1' makes a request to start" bitfld.long 0x0 13.--14. "JEXTEN,Trigger enable and trigger edge selection for injected conversions" "0: Trigger detection is disabled,1: Each rising edge on the selected trigger makes a..,2: Each falling edge on the selected trigger makes..,3: Both rising edges and falling edges on the.." newline hexmask.long.byte 0x0 8.--12. 1. "JEXTSEL,Trigger signal selection for launching injected conversions" bitfld.long 0x0 5. "JDMAEN,DMA channel enabled to read data for the injected channel group" "0: The DMA channel is not enabled to read injected..,1: The DMA channel is enabled to read injected data" newline bitfld.long 0x0 4. "JSCAN,Scanning conversion mode for injected conversions" "0: One channel conversion is performed from the..,1: The series of conversions for the injected group.." bitfld.long 0x0 3. "JSYNC,Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger" "0: Do not launch an injected conversion..,1: Launch an injected conversion in this DFSDM_FLTx.." newline bitfld.long 0x0 1. "JSWSTART,Start a conversion of the injected group of channels" "0: Writing '0' has no effect,1: Writing '1' makes a request to convert" bitfld.long 0x0 0. "DFEN,DFSDM_FLTx enable" "0: register DFSDM_FLTxISR is set to the reset state,1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled.." line.long 0x4 "DFSDM_FLT7CR2," hexmask.long.byte 0x4 16.--23. 1. "AWDCH,Analog watchdog channel selection" hexmask.long.byte 0x4 8.--15. 1. "EXCH,Extremes detector channel selection" newline bitfld.long 0x4 6. "CKABIE,Clock absence interrupt enable" "0: Detection of channel input clock absence..,1: Detection of channel input clock absence.." bitfld.long 0x4 5. "SCDIE,Short-circuit detector interrupt enable" "0: short-circuit detector interrupt is disabled,1: short-circuit detector interrupt is enabled" newline bitfld.long 0x4 4. "AWDIE,Analog watchdog interrupt enable" "0: Analog watchdog interrupt is disabled,1: Analog watchdog interrupt is enabled" bitfld.long 0x4 3. "ROVRIE,Regular data overrun interrupt enable" "0: Regular data overrun interrupt is disabled,1: Regular data overrun interrupt is enabled" newline bitfld.long 0x4 2. "JOVRIE,Injected data overrun interrupt enable" "0: Injected data overrun interrupt is disabled,1: Injected data overrun interrupt is enabled" bitfld.long 0x4 1. "REOCIE,Regular end of conversion interrupt enable" "0: Regular end of conversion interrupt is disabled,1: Regular end of conversion interrupt is enabled" newline bitfld.long 0x4 0. "JEOCIE,Injected end of conversion interrupt enable" "0: Injected end of conversion interrupt is disabled,1: Injected end of conversion interrupt is enabled" rgroup.long 0x488++0x3 line.long 0x0 "DFSDM_FLT7ISR," hexmask.long.byte 0x0 24.--31. 1. "SCDF,short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CKABF,Clock absence flag" newline bitfld.long 0x0 14. "RCIP,Regular conversion in progress status" "0: No request to convert the regular channel has..,1: The conversion of the regular channel is in.." bitfld.long 0x0 13. "JCIP,Injected conversion in progress status" "0: No request to convert the injected channel group..,1: The conversion of the injected channel group is.." newline bitfld.long 0x0 4. "AWDF,Analog watchdog" "0: No Analog watchdog event occurred,1: The analog watchdog block detected voltage which.." bitfld.long 0x0 3. "ROVRF,Regular conversion overrun flag" "0: No regular conversion overrun has occurred,1: A regular conversion overrun has occurred which.." newline bitfld.long 0x0 2. "JOVRF,Injected conversion overrun flag" "0: No injected conversion overrun has occurred,1: An injected conversion overrun has occurred.." bitfld.long 0x0 1. "REOCF,End of regular conversion flag" "0: No regular conversion has completed,1: A regular conversion has completed and its data.." newline bitfld.long 0x0 0. "JEOCF,End of injected conversion flag" "0: No injected conversion has completed,1: An injected conversion has completed and its.." group.long 0x48C++0xB line.long 0x0 "DFSDM_FLT7ICR," hexmask.long.byte 0x0 24.--31. 1. "CLRSCDF,Clear the short-circuit detector flag" hexmask.long.byte 0x0 16.--23. 1. "CLRCKABF,Clear the clock absence flag" newline bitfld.long 0x0 3. "CLRROVRF,Clear the regular conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the ROVRF bit" bitfld.long 0x0 2. "CLRJOVRF,Clear the injected conversion overrun flag" "0: Writing '0' has no effect,1: Writing '0' clears the JOVRF bit" line.long 0x4 "DFSDM_FLT7JCHGR," hexmask.long.byte 0x4 0.--7. 1. "JCHG,Injected channel group selection" line.long 0x8 "DFSDM_FLT7FCR," hexmask.long.byte 0x8 29.--31. 1. "FORD,Sinc filter order" hexmask.long.word 0x8 16.--25. 1. "FOSR,Sinc filter oversampling ratio (decimation rate)" newline hexmask.long.byte 0x8 0.--7. 1. "IOSR,Integrator oversampling ratio (averaging length)" rgroup.long 0x498++0x7 line.long 0x0 "DFSDM_FLT7JDATAR," hexmask.long.tbyte 0x0 8.--31. 1. "JDATA,Injected group conversion data" hexmask.long.byte 0x0 0.--3. 1. "JDATACH,Injected channel most recently converted" line.long 0x4 "DFSDM_FLT7RDATAR," hexmask.long.tbyte 0x4 8.--31. 1. "RDATA,Regular channel conversion data" bitfld.long 0x4 4. "RPEND,Regular channel pending data" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "RDATACH,Regular channel most recently converted" group.long 0x4A0++0x7 line.long 0x0 "DFSDM_FLT7AWHTR," hexmask.long.tbyte 0x0 8.--31. 1. "AWHT,Analog watchdog high threshold" hexmask.long.byte 0x0 0.--3. 1. "BKAWH,Break signal assignment to analog watchdog high threshold event" line.long 0x4 "DFSDM_FLT7AWLTR," hexmask.long.tbyte 0x4 8.--31. 1. "AWLT,Analog watchdog low threshold" hexmask.long.byte 0x4 0.--3. 1. "BKAWL,Break signal assignment to analog watchdog low threshold event" rgroup.long 0x4A8++0x3 line.long 0x0 "DFSDM_FLT7AWSR," hexmask.long.byte 0x0 8.--15. 1. "AWHTF,Analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "AWLTF,Analog watchdog low threshold flag" group.long 0x4AC++0x3 line.long 0x0 "DFSDM_FLT7AWCFR," hexmask.long.byte 0x0 8.--15. 1. "CLRAWHTF,Clear the analog watchdog high threshold flag" hexmask.long.byte 0x0 0.--7. 1. "CLRAWLTF,Clear the analog watchdog low threshold flag" rgroup.long 0x4B0++0x3 line.long 0x0 "DFSDM_FLT7EXMAX," hexmask.long.tbyte 0x0 8.--31. 1. "EXMAX,Extremes detector maximum value" hexmask.long.byte 0x0 0.--3. 1. "EXMAXCH,Extremes detector maximum data channel." group.long 0x4B4++0x3 line.long 0x0 "DFSDM_FLT7EXMIN," hexmask.long.tbyte 0x0 8.--31. 1. "EXMIN,Extremes detector minimum value" hexmask.long.byte 0x0 0.--3. 1. "EXMINCH,Extremes detector minimum data channel" rgroup.long 0x4B8++0x3 line.long 0x0 "DFSDM_FLT7CNVTIMR," hexmask.long 0x0 4.--31. 1. "CNVCNT,28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK" tree.end endif tree.end tree "DLYB (Delay Block)" base ad:0x0 sif (cpuis("STM32H742*")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H743*")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H750*")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H753*")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "DELAY_Block_QUADSPI" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H7A3*")) tree "Delay_Block_OCTOSPI1 (DELAY_Block_SDMMC1)" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H7B0*")) tree "Delay_Block_OCTOSPI1 (DELAY_Block_SDMMC1)" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H7B3*")) tree "Delay_Block_OCTOSPI1 (DELAY_Block_SDMMC1)" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif tree "DELAY_Block_SDMMC1" base ad:0x52008000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end tree "DELAY_Block_SDMMC2" base ad:0x48022800 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "Delay_Block_OCTOSPI1 (DELAY_Block_SDMMC1)" base ad:0x52006000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end tree "Delay_Block_OCTOSPI2 (DELAY_Block_SDMMC1)" base ad:0x5200B000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H7A3*")) tree "Delay_Block_OCTOSPI2 (DELAY_Block_SDMMC1)" base ad:0x5200B000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H7B0*")) tree "Delay_Block_OCTOSPI2 (DELAY_Block_SDMMC1)" base ad:0x5200B000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif sif (cpuis("STM32H7B3*")) tree "Delay_Block_OCTOSPI2 (DELAY_Block_SDMMC1)" base ad:0x5200B000 group.long 0x0++0x7 line.long 0x0 "CR,DLYB control register" bitfld.long 0x0 1. "SEN,Sampler length enable bit" "0,1" bitfld.long 0x0 0. "DEN,Delay block enable bit" "0,1" line.long 0x4 "CFGR,DLYB configuration register" bitfld.long 0x4 31. "LNGF,Length valid flag" "0,1" hexmask.long.word 0x4 16.--27. 1. "LNG,Delay line length value" hexmask.long.byte 0x4 8.--14. 1. "UNIT,Delay Defines the delay of a Unit delay" hexmask.long.byte 0x4 0.--3. 1. "SEL,Select the phase for the Output" tree.end endif tree.end tree "DMA (Direct Memory Access Controller)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "DMA1" base ad:0x40020000 rgroup.long 0x0++0x7 line.long 0x0 "LISR,low interrupt status register" bitfld.long 0x0 27. "TCIF3,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 26. "HTIF3,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 25. "TEIF3,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 24. "DMEIF3,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 22. "FEIF3,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "TCIF2,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 20. "HTIF2,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 19. "TEIF2,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 18. "DMEIF2,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 16. "FEIF2,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "TCIF1,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x0 10. "HTIF1,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 9. "TEIF1,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 8. "DMEIF1,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 6. "FEIF1,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "TCIF0,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 4. "HTIF0,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 3. "TEIF0,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 2. "DMEIF0,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 0. "FEIF0,Stream x FIFO error interrupt flag" "0,1" line.long 0x4 "HISR,high interrupt status register" bitfld.long 0x4 27. "TCIF7,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 26. "HTIF7,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 25. "TEIF7,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 24. "DMEIF7,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 22. "FEIF7,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "TCIF6,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 20. "HTIF6,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 19. "TEIF6,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 18. "DMEIF6,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 16. "FEIF6,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "TCIF5,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x4 10. "HTIF5,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 9. "TEIF5,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 8. "DMEIF5,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 6. "FEIF5,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "TCIF4,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 4. "HTIF4,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 3. "TEIF4,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 2. "DMEIF4,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 0. "FEIF4,Stream x FIFO error interrupt flag" "0,1" group.long 0x8++0xC7 line.long 0x0 "LIFCR,low interrupt flag clear" bitfld.long 0x0 27. "CTCIF3,Stream x clear transfer complete" "0,1" bitfld.long 0x0 26. "CHTIF3,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 25. "CTEIF3,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 24. "CDMEIF3,Stream x clear direct mode error" "0,1" bitfld.long 0x0 22. "CFEIF3,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "CTCIF2,Stream x clear transfer complete" "0,1" bitfld.long 0x0 20. "CHTIF2,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 19. "CTEIF2,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 18. "CDMEIF2,Stream x clear direct mode error" "0,1" bitfld.long 0x0 16. "CFEIF2,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "CTCIF1,Stream x clear transfer complete" "0,1" newline bitfld.long 0x0 10. "CHTIF1,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 9. "CTEIF1,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 8. "CDMEIF1,Stream x clear direct mode error" "0,1" bitfld.long 0x0 6. "CFEIF1,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "CTCIF0,Stream x clear transfer complete" "0,1" bitfld.long 0x0 4. "CHTIF0,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 3. "CTEIF0,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 2. "CDMEIF0,Stream x clear direct mode error" "0,1" bitfld.long 0x0 0. "CFEIF0,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x4 "HIFCR,high interrupt flag clear" bitfld.long 0x4 27. "CTCIF7,Stream x clear transfer complete" "0,1" bitfld.long 0x4 26. "CHTIF7,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 25. "CTEIF7,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 24. "CDMEIF7,Stream x clear direct mode error" "0,1" bitfld.long 0x4 22. "CFEIF7,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "CTCIF6,Stream x clear transfer complete" "0,1" bitfld.long 0x4 20. "CHTIF6,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 19. "CTEIF6,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 18. "CDMEIF6,Stream x clear direct mode error" "0,1" bitfld.long 0x4 16. "CFEIF6,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "CTCIF5,Stream x clear transfer complete" "0,1" newline bitfld.long 0x4 10. "CHTIF5,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 9. "CTEIF5,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 8. "CDMEIF5,Stream x clear direct mode error" "0,1" bitfld.long 0x4 6. "CFEIF5,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "CTCIF4,Stream x clear transfer complete" "0,1" bitfld.long 0x4 4. "CHTIF4,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 3. "CTEIF4,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 2. "CDMEIF4,Stream x clear direct mode error" "0,1" bitfld.long 0x4 0. "CFEIF4,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x8 "S0CR,stream x configuration" bitfld.long 0x8 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x8 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x8 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x8 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x8 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x8 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x8 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x8 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x8 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x8 9. "PINC,Peripheral increment mode" "0,1" bitfld.long 0x8 8. "CIRC,Circular mode" "0,1" newline bitfld.long 0x8 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x8 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x8 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x8 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x8 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x8 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x8 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xC "S0NDTR,stream x number of data" hexmask.long.word 0xC 0.--15. 1. "NDT,Number of data items to" line.long 0x10 "S0PAR,stream x peripheral address" hexmask.long 0x10 0.--31. 1. "PA,Peripheral address" line.long 0x14 "S0M0AR,stream x memory 0 address" hexmask.long 0x14 0.--31. 1. "M0A,Memory 0 address" line.long 0x18 "S0M1AR,stream x memory 1 address" hexmask.long 0x18 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x1C "S0FCR,stream x FIFO control register" bitfld.long 0x1C 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x1C 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x1C 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x1C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x1C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x20 "S1CR,stream x configuration" bitfld.long 0x20 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x20 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x20 20. "ACK,ACK" "0,1" bitfld.long 0x20 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x20 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x20 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x20 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x20 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x20 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x20 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x20 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x20 8. "CIRC,Circular mode" "0,1" bitfld.long 0x20 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x20 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x20 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x20 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x20 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x20 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x20 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x24 "S1NDTR,stream x number of data" hexmask.long.word 0x24 0.--15. 1. "NDT,Number of data items to" line.long 0x28 "S1PAR,stream x peripheral address" hexmask.long 0x28 0.--31. 1. "PA,Peripheral address" line.long 0x2C "S1M0AR,stream x memory 0 address" hexmask.long 0x2C 0.--31. 1. "M0A,Memory 0 address" line.long 0x30 "S1M1AR,stream x memory 1 address" hexmask.long 0x30 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x34 "S1FCR,stream x FIFO control register" bitfld.long 0x34 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x34 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x34 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x34 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x34 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x38 "S2CR,stream x configuration" bitfld.long 0x38 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x38 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x38 20. "ACK,ACK" "0,1" bitfld.long 0x38 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x38 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x38 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x38 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x38 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x38 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x38 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x38 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x38 8. "CIRC,Circular mode" "0,1" bitfld.long 0x38 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x38 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x38 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x38 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x38 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x38 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x38 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x3C "S2NDTR,stream x number of data" hexmask.long.word 0x3C 0.--15. 1. "NDT,Number of data items to" line.long 0x40 "S2PAR,stream x peripheral address" hexmask.long 0x40 0.--31. 1. "PA,Peripheral address" line.long 0x44 "S2M0AR,stream x memory 0 address" hexmask.long 0x44 0.--31. 1. "M0A,Memory 0 address" line.long 0x48 "S2M1AR,stream x memory 1 address" hexmask.long 0x48 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x4C "S2FCR,stream x FIFO control register" bitfld.long 0x4C 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4C 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x4C 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x4C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x4C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x50 "S3CR,stream x configuration" bitfld.long 0x50 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x50 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x50 20. "ACK,ACK" "0,1" bitfld.long 0x50 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x50 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x50 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x50 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x50 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x50 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x50 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x50 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x50 8. "CIRC,Circular mode" "0,1" bitfld.long 0x50 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x50 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x50 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x50 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x50 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x50 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x50 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x54 "S3NDTR,stream x number of data" hexmask.long.word 0x54 0.--15. 1. "NDT,Number of data items to" line.long 0x58 "S3PAR,stream x peripheral address" hexmask.long 0x58 0.--31. 1. "PA,Peripheral address" line.long 0x5C "S3M0AR,stream x memory 0 address" hexmask.long 0x5C 0.--31. 1. "M0A,Memory 0 address" line.long 0x60 "S3M1AR,stream x memory 1 address" hexmask.long 0x60 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x64 "S3FCR,stream x FIFO control register" bitfld.long 0x64 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x64 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x64 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x64 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x64 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x68 "S4CR,stream x configuration" bitfld.long 0x68 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x68 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x68 20. "ACK,ACK" "0,1" bitfld.long 0x68 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x68 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x68 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x68 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x68 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x68 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x68 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x68 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x68 8. "CIRC,Circular mode" "0,1" bitfld.long 0x68 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x68 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x68 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x68 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x68 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x68 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x68 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x6C "S4NDTR,stream x number of data" hexmask.long.word 0x6C 0.--15. 1. "NDT,Number of data items to" line.long 0x70 "S4PAR,stream x peripheral address" hexmask.long 0x70 0.--31. 1. "PA,Peripheral address" line.long 0x74 "S4M0AR,stream x memory 0 address" hexmask.long 0x74 0.--31. 1. "M0A,Memory 0 address" line.long 0x78 "S4M1AR,stream x memory 1 address" hexmask.long 0x78 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x7C "S4FCR,stream x FIFO control register" bitfld.long 0x7C 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x7C 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x7C 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x7C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x7C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x80 "S5CR,stream x configuration" bitfld.long 0x80 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x80 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x80 20. "ACK,ACK" "0,1" bitfld.long 0x80 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x80 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x80 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x80 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x80 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x80 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x80 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x80 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x80 8. "CIRC,Circular mode" "0,1" bitfld.long 0x80 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x80 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x80 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x80 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x80 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x80 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x80 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x84 "S5NDTR,stream x number of data" hexmask.long.word 0x84 0.--15. 1. "NDT,Number of data items to" line.long 0x88 "S5PAR,stream x peripheral address" hexmask.long 0x88 0.--31. 1. "PA,Peripheral address" line.long 0x8C "S5M0AR,stream x memory 0 address" hexmask.long 0x8C 0.--31. 1. "M0A,Memory 0 address" line.long 0x90 "S5M1AR,stream x memory 1 address" hexmask.long 0x90 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x94 "S5FCR,stream x FIFO control register" bitfld.long 0x94 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x94 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x94 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x94 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x94 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x98 "S6CR,stream x configuration" bitfld.long 0x98 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x98 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x98 20. "ACK,ACK" "0,1" bitfld.long 0x98 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x98 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x98 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x98 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x98 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x98 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x98 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x98 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x98 8. "CIRC,Circular mode" "0,1" bitfld.long 0x98 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x98 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x98 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x98 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x98 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x98 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x98 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x9C "S6NDTR,stream x number of data" hexmask.long.word 0x9C 0.--15. 1. "NDT,Number of data items to" line.long 0xA0 "S6PAR,stream x peripheral address" hexmask.long 0xA0 0.--31. 1. "PA,Peripheral address" line.long 0xA4 "S6M0AR,stream x memory 0 address" hexmask.long 0xA4 0.--31. 1. "M0A,Memory 0 address" line.long 0xA8 "S6M1AR,stream x memory 1 address" hexmask.long 0xA8 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xAC "S6FCR,stream x FIFO control register" bitfld.long 0xAC 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0xAC 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0xAC 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0xAC 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xAC 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0xB0 "S7CR,stream x configuration" bitfld.long 0xB0 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0xB0 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0xB0 20. "ACK,ACK" "0,1" bitfld.long 0xB0 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0xB0 18. "DBM,Double buffer mode" "0,1" bitfld.long 0xB0 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0xB0 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0xB0 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0xB0 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0xB0 10. "MINC,Memory increment mode" "0,1" bitfld.long 0xB0 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0xB0 8. "CIRC,Circular mode" "0,1" bitfld.long 0xB0 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0xB0 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0xB0 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0xB0 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0xB0 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0xB0 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0xB0 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xB4 "S7NDTR,stream x number of data" hexmask.long.word 0xB4 0.--15. 1. "NDT,Number of data items to" line.long 0xB8 "S7PAR,stream x peripheral address" hexmask.long 0xB8 0.--31. 1. "PA,Peripheral address" line.long 0xBC "S7M0AR,stream x memory 0 address" hexmask.long 0xBC 0.--31. 1. "M0A,Memory 0 address" line.long 0xC0 "S7M1AR,stream x memory 1 address" hexmask.long 0xC0 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xC4 "S7FCR,stream x FIFO control register" bitfld.long 0xC4 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0xC4 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0xC4 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0xC4 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xC4 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "DMA2" base ad:0x40020400 rgroup.long 0x0++0x7 line.long 0x0 "LISR,low interrupt status register" bitfld.long 0x0 27. "TCIF3,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 26. "HTIF3,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 25. "TEIF3,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 24. "DMEIF3,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 22. "FEIF3,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "TCIF2,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 20. "HTIF2,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 19. "TEIF2,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 18. "DMEIF2,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 16. "FEIF2,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "TCIF1,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x0 10. "HTIF1,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 9. "TEIF1,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 8. "DMEIF1,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 6. "FEIF1,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "TCIF0,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 4. "HTIF0,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 3. "TEIF0,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 2. "DMEIF0,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 0. "FEIF0,Stream x FIFO error interrupt flag" "0,1" line.long 0x4 "HISR,high interrupt status register" bitfld.long 0x4 27. "TCIF7,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 26. "HTIF7,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 25. "TEIF7,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 24. "DMEIF7,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 22. "FEIF7,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "TCIF6,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 20. "HTIF6,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 19. "TEIF6,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 18. "DMEIF6,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 16. "FEIF6,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "TCIF5,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x4 10. "HTIF5,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 9. "TEIF5,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 8. "DMEIF5,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 6. "FEIF5,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "TCIF4,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 4. "HTIF4,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 3. "TEIF4,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 2. "DMEIF4,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 0. "FEIF4,Stream x FIFO error interrupt flag" "0,1" group.long 0x8++0xC7 line.long 0x0 "LIFCR,low interrupt flag clear" bitfld.long 0x0 27. "CTCIF3,Stream x clear transfer complete" "0,1" bitfld.long 0x0 26. "CHTIF3,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 25. "CTEIF3,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 24. "CDMEIF3,Stream x clear direct mode error" "0,1" bitfld.long 0x0 22. "CFEIF3,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "CTCIF2,Stream x clear transfer complete" "0,1" bitfld.long 0x0 20. "CHTIF2,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 19. "CTEIF2,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 18. "CDMEIF2,Stream x clear direct mode error" "0,1" bitfld.long 0x0 16. "CFEIF2,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "CTCIF1,Stream x clear transfer complete" "0,1" newline bitfld.long 0x0 10. "CHTIF1,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 9. "CTEIF1,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 8. "CDMEIF1,Stream x clear direct mode error" "0,1" bitfld.long 0x0 6. "CFEIF1,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "CTCIF0,Stream x clear transfer complete" "0,1" bitfld.long 0x0 4. "CHTIF0,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 3. "CTEIF0,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 2. "CDMEIF0,Stream x clear direct mode error" "0,1" bitfld.long 0x0 0. "CFEIF0,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x4 "HIFCR,high interrupt flag clear" bitfld.long 0x4 27. "CTCIF7,Stream x clear transfer complete" "0,1" bitfld.long 0x4 26. "CHTIF7,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 25. "CTEIF7,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 24. "CDMEIF7,Stream x clear direct mode error" "0,1" bitfld.long 0x4 22. "CFEIF7,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "CTCIF6,Stream x clear transfer complete" "0,1" bitfld.long 0x4 20. "CHTIF6,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 19. "CTEIF6,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 18. "CDMEIF6,Stream x clear direct mode error" "0,1" bitfld.long 0x4 16. "CFEIF6,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "CTCIF5,Stream x clear transfer complete" "0,1" newline bitfld.long 0x4 10. "CHTIF5,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 9. "CTEIF5,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 8. "CDMEIF5,Stream x clear direct mode error" "0,1" bitfld.long 0x4 6. "CFEIF5,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "CTCIF4,Stream x clear transfer complete" "0,1" bitfld.long 0x4 4. "CHTIF4,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 3. "CTEIF4,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 2. "CDMEIF4,Stream x clear direct mode error" "0,1" bitfld.long 0x4 0. "CFEIF4,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x8 "S0CR,stream x configuration" bitfld.long 0x8 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x8 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x8 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x8 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x8 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x8 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x8 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x8 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x8 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x8 9. "PINC,Peripheral increment mode" "0,1" bitfld.long 0x8 8. "CIRC,Circular mode" "0,1" newline bitfld.long 0x8 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x8 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x8 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x8 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x8 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x8 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x8 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xC "S0NDTR,stream x number of data" hexmask.long.word 0xC 0.--15. 1. "NDT,Number of data items to" line.long 0x10 "S0PAR,stream x peripheral address" hexmask.long 0x10 0.--31. 1. "PA,Peripheral address" line.long 0x14 "S0M0AR,stream x memory 0 address" hexmask.long 0x14 0.--31. 1. "M0A,Memory 0 address" line.long 0x18 "S0M1AR,stream x memory 1 address" hexmask.long 0x18 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x1C "S0FCR,stream x FIFO control register" bitfld.long 0x1C 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x1C 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x1C 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x1C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x1C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x20 "S1CR,stream x configuration" bitfld.long 0x20 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x20 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x20 20. "ACK,ACK" "0,1" bitfld.long 0x20 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x20 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x20 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x20 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x20 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x20 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x20 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x20 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x20 8. "CIRC,Circular mode" "0,1" bitfld.long 0x20 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x20 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x20 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x20 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x20 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x20 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x20 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x24 "S1NDTR,stream x number of data" hexmask.long.word 0x24 0.--15. 1. "NDT,Number of data items to" line.long 0x28 "S1PAR,stream x peripheral address" hexmask.long 0x28 0.--31. 1. "PA,Peripheral address" line.long 0x2C "S1M0AR,stream x memory 0 address" hexmask.long 0x2C 0.--31. 1. "M0A,Memory 0 address" line.long 0x30 "S1M1AR,stream x memory 1 address" hexmask.long 0x30 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x34 "S1FCR,stream x FIFO control register" bitfld.long 0x34 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x34 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x34 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x34 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x34 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x38 "S2CR,stream x configuration" bitfld.long 0x38 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x38 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x38 20. "ACK,ACK" "0,1" bitfld.long 0x38 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x38 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x38 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x38 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x38 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x38 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x38 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x38 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x38 8. "CIRC,Circular mode" "0,1" bitfld.long 0x38 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x38 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x38 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x38 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x38 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x38 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x38 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x3C "S2NDTR,stream x number of data" hexmask.long.word 0x3C 0.--15. 1. "NDT,Number of data items to" line.long 0x40 "S2PAR,stream x peripheral address" hexmask.long 0x40 0.--31. 1. "PA,Peripheral address" line.long 0x44 "S2M0AR,stream x memory 0 address" hexmask.long 0x44 0.--31. 1. "M0A,Memory 0 address" line.long 0x48 "S2M1AR,stream x memory 1 address" hexmask.long 0x48 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x4C "S2FCR,stream x FIFO control register" bitfld.long 0x4C 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4C 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x4C 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x4C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x4C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x50 "S3CR,stream x configuration" bitfld.long 0x50 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x50 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x50 20. "ACK,ACK" "0,1" bitfld.long 0x50 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x50 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x50 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x50 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x50 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x50 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x50 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x50 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x50 8. "CIRC,Circular mode" "0,1" bitfld.long 0x50 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x50 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x50 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x50 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x50 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x50 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x50 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x54 "S3NDTR,stream x number of data" hexmask.long.word 0x54 0.--15. 1. "NDT,Number of data items to" line.long 0x58 "S3PAR,stream x peripheral address" hexmask.long 0x58 0.--31. 1. "PA,Peripheral address" line.long 0x5C "S3M0AR,stream x memory 0 address" hexmask.long 0x5C 0.--31. 1. "M0A,Memory 0 address" line.long 0x60 "S3M1AR,stream x memory 1 address" hexmask.long 0x60 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x64 "S3FCR,stream x FIFO control register" bitfld.long 0x64 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x64 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x64 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x64 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x64 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x68 "S4CR,stream x configuration" bitfld.long 0x68 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x68 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x68 20. "ACK,ACK" "0,1" bitfld.long 0x68 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x68 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x68 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x68 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x68 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x68 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x68 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x68 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x68 8. "CIRC,Circular mode" "0,1" bitfld.long 0x68 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x68 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x68 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x68 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x68 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x68 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x68 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x6C "S4NDTR,stream x number of data" hexmask.long.word 0x6C 0.--15. 1. "NDT,Number of data items to" line.long 0x70 "S4PAR,stream x peripheral address" hexmask.long 0x70 0.--31. 1. "PA,Peripheral address" line.long 0x74 "S4M0AR,stream x memory 0 address" hexmask.long 0x74 0.--31. 1. "M0A,Memory 0 address" line.long 0x78 "S4M1AR,stream x memory 1 address" hexmask.long 0x78 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x7C "S4FCR,stream x FIFO control register" bitfld.long 0x7C 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x7C 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x7C 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x7C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x7C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x80 "S5CR,stream x configuration" bitfld.long 0x80 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x80 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x80 20. "ACK,ACK" "0,1" bitfld.long 0x80 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x80 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x80 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x80 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x80 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x80 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x80 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x80 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x80 8. "CIRC,Circular mode" "0,1" bitfld.long 0x80 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x80 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x80 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x80 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x80 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x80 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x80 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x84 "S5NDTR,stream x number of data" hexmask.long.word 0x84 0.--15. 1. "NDT,Number of data items to" line.long 0x88 "S5PAR,stream x peripheral address" hexmask.long 0x88 0.--31. 1. "PA,Peripheral address" line.long 0x8C "S5M0AR,stream x memory 0 address" hexmask.long 0x8C 0.--31. 1. "M0A,Memory 0 address" line.long 0x90 "S5M1AR,stream x memory 1 address" hexmask.long 0x90 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x94 "S5FCR,stream x FIFO control register" bitfld.long 0x94 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x94 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x94 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0x94 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x94 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x98 "S6CR,stream x configuration" bitfld.long 0x98 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x98 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x98 20. "ACK,ACK" "0,1" bitfld.long 0x98 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x98 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x98 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x98 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x98 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x98 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x98 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x98 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x98 8. "CIRC,Circular mode" "0,1" bitfld.long 0x98 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x98 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x98 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x98 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x98 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x98 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x98 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x9C "S6NDTR,stream x number of data" hexmask.long.word 0x9C 0.--15. 1. "NDT,Number of data items to" line.long 0xA0 "S6PAR,stream x peripheral address" hexmask.long 0xA0 0.--31. 1. "PA,Peripheral address" line.long 0xA4 "S6M0AR,stream x memory 0 address" hexmask.long 0xA4 0.--31. 1. "M0A,Memory 0 address" line.long 0xA8 "S6M1AR,stream x memory 1 address" hexmask.long 0xA8 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xAC "S6FCR,stream x FIFO control register" bitfld.long 0xAC 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0xAC 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0xAC 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0xAC 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xAC 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0xB0 "S7CR,stream x configuration" bitfld.long 0xB0 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0xB0 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0xB0 20. "ACK,ACK" "0,1" bitfld.long 0xB0 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0xB0 18. "DBM,Double buffer mode" "0,1" bitfld.long 0xB0 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0xB0 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0xB0 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0xB0 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0xB0 10. "MINC,Memory increment mode" "0,1" bitfld.long 0xB0 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0xB0 8. "CIRC,Circular mode" "0,1" bitfld.long 0xB0 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0xB0 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0xB0 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0xB0 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0xB0 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0xB0 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0xB0 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xB4 "S7NDTR,stream x number of data" hexmask.long.word 0xB4 0.--15. 1. "NDT,Number of data items to" line.long 0xB8 "S7PAR,stream x peripheral address" hexmask.long 0xB8 0.--31. 1. "PA,Peripheral address" line.long 0xBC "S7M0AR,stream x memory 0 address" hexmask.long 0xBC 0.--31. 1. "M0A,Memory 0 address" line.long 0xC0 "S7M1AR,stream x memory 1 address" hexmask.long 0xC0 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xC4 "S7FCR,stream x FIFO control register" bitfld.long 0xC4 7. "FEIE,FIFO error interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0xC4 3.--6. 1. "FS,FIFO status" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0xC4 3.--5. "FS,FIFO status" "0,1,2,3,4,5,6,7" endif bitfld.long 0xC4 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xC4 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H7B3*")) tree "DMA1" base ad:0x40020000 rgroup.long 0x0++0x7 line.long 0x0 "LISR,low interrupt status register" bitfld.long 0x0 27. "TCIF3,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 26. "HTIF3,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 25. "TEIF3,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 24. "DMEIF3,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 22. "FEIF3,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "TCIF2,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 20. "HTIF2,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 19. "TEIF2,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 18. "DMEIF2,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 16. "FEIF2,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "TCIF1,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x0 10. "HTIF1,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 9. "TEIF1,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 8. "DMEIF1,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 6. "FEIF1,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "TCIF0,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 4. "HTIF0,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 3. "TEIF0,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 2. "DMEIF0,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 0. "FEIF0,Stream x FIFO error interrupt flag" "0,1" line.long 0x4 "HISR,high interrupt status register" bitfld.long 0x4 27. "TCIF7,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 26. "HTIF7,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 25. "TEIF7,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 24. "DMEIF7,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 22. "FEIF7,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "TCIF6,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 20. "HTIF6,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 19. "TEIF6,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 18. "DMEIF6,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 16. "FEIF6,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "TCIF5,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x4 10. "HTIF5,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 9. "TEIF5,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 8. "DMEIF5,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 6. "FEIF5,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "TCIF4,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 4. "HTIF4,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 3. "TEIF4,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 2. "DMEIF4,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 0. "FEIF4,Stream x FIFO error interrupt flag" "0,1" group.long 0x8++0xC7 line.long 0x0 "LIFCR,low interrupt flag clear" bitfld.long 0x0 27. "CTCIF3,Stream x clear transfer complete" "0,1" bitfld.long 0x0 26. "CHTIF3,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 25. "CTEIF3,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 24. "CDMEIF3,Stream x clear direct mode error" "0,1" bitfld.long 0x0 22. "CFEIF3,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "CTCIF2,Stream x clear transfer complete" "0,1" bitfld.long 0x0 20. "CHTIF2,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 19. "CTEIF2,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 18. "CDMEIF2,Stream x clear direct mode error" "0,1" bitfld.long 0x0 16. "CFEIF2,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "CTCIF1,Stream x clear transfer complete" "0,1" newline bitfld.long 0x0 10. "CHTIF1,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 9. "CTEIF1,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 8. "CDMEIF1,Stream x clear direct mode error" "0,1" bitfld.long 0x0 6. "CFEIF1,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "CTCIF0,Stream x clear transfer complete" "0,1" bitfld.long 0x0 4. "CHTIF0,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 3. "CTEIF0,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 2. "CDMEIF0,Stream x clear direct mode error" "0,1" bitfld.long 0x0 0. "CFEIF0,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x4 "HIFCR,high interrupt flag clear" bitfld.long 0x4 27. "CTCIF7,Stream x clear transfer complete" "0,1" bitfld.long 0x4 26. "CHTIF7,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 25. "CTEIF7,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 24. "CDMEIF7,Stream x clear direct mode error" "0,1" bitfld.long 0x4 22. "CFEIF7,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "CTCIF6,Stream x clear transfer complete" "0,1" bitfld.long 0x4 20. "CHTIF6,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 19. "CTEIF6,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 18. "CDMEIF6,Stream x clear direct mode error" "0,1" bitfld.long 0x4 16. "CFEIF6,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "CTCIF5,Stream x clear transfer complete" "0,1" newline bitfld.long 0x4 10. "CHTIF5,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 9. "CTEIF5,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 8. "CDMEIF5,Stream x clear direct mode error" "0,1" bitfld.long 0x4 6. "CFEIF5,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "CTCIF4,Stream x clear transfer complete" "0,1" bitfld.long 0x4 4. "CHTIF4,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 3. "CTEIF4,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 2. "CDMEIF4,Stream x clear direct mode error" "0,1" bitfld.long 0x4 0. "CFEIF4,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x8 "S0CR,stream x configuration" bitfld.long 0x8 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x8 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x8 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x8 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x8 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x8 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x8 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x8 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x8 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x8 9. "PINC,Peripheral increment mode" "0,1" bitfld.long 0x8 8. "CIRC,Circular mode" "0,1" newline bitfld.long 0x8 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x8 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x8 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x8 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x8 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x8 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x8 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xC "S0NDTR,stream x number of data" hexmask.long.word 0xC 0.--15. 1. "NDT,Number of data items to" line.long 0x10 "S0PAR,stream x peripheral address" hexmask.long 0x10 0.--31. 1. "PA,Peripheral address" line.long 0x14 "S0M0AR,stream x memory 0 address" hexmask.long 0x14 0.--31. 1. "M0A,Memory 0 address" line.long 0x18 "S0M1AR,stream x memory 1 address" hexmask.long 0x18 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x1C "S0FCR,stream x FIFO control register" bitfld.long 0x1C 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x1C 3.--6. 1. "FS,FIFO status" bitfld.long 0x1C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x1C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x20 "S1CR,stream x configuration" bitfld.long 0x20 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x20 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x20 20. "ACK,ACK" "0,1" bitfld.long 0x20 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x20 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x20 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x20 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x20 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x20 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x20 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x20 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x20 8. "CIRC,Circular mode" "0,1" bitfld.long 0x20 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x20 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x20 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x20 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x20 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x20 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x20 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x24 "S1NDTR,stream x number of data" hexmask.long.word 0x24 0.--15. 1. "NDT,Number of data items to" line.long 0x28 "S1PAR,stream x peripheral address" hexmask.long 0x28 0.--31. 1. "PA,Peripheral address" line.long 0x2C "S1M0AR,stream x memory 0 address" hexmask.long 0x2C 0.--31. 1. "M0A,Memory 0 address" line.long 0x30 "S1M1AR,stream x memory 1 address" hexmask.long 0x30 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x34 "S1FCR,stream x FIFO control register" bitfld.long 0x34 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x34 3.--6. 1. "FS,FIFO status" bitfld.long 0x34 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x34 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x38 "S2CR,stream x configuration" bitfld.long 0x38 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x38 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x38 20. "ACK,ACK" "0,1" bitfld.long 0x38 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x38 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x38 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x38 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x38 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x38 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x38 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x38 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x38 8. "CIRC,Circular mode" "0,1" bitfld.long 0x38 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x38 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x38 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x38 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x38 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x38 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x38 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x3C "S2NDTR,stream x number of data" hexmask.long.word 0x3C 0.--15. 1. "NDT,Number of data items to" line.long 0x40 "S2PAR,stream x peripheral address" hexmask.long 0x40 0.--31. 1. "PA,Peripheral address" line.long 0x44 "S2M0AR,stream x memory 0 address" hexmask.long 0x44 0.--31. 1. "M0A,Memory 0 address" line.long 0x48 "S2M1AR,stream x memory 1 address" hexmask.long 0x48 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x4C "S2FCR,stream x FIFO control register" bitfld.long 0x4C 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x4C 3.--6. 1. "FS,FIFO status" bitfld.long 0x4C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x4C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x50 "S3CR,stream x configuration" bitfld.long 0x50 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x50 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x50 20. "ACK,ACK" "0,1" bitfld.long 0x50 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x50 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x50 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x50 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x50 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x50 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x50 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x50 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x50 8. "CIRC,Circular mode" "0,1" bitfld.long 0x50 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x50 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x50 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x50 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x50 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x50 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x50 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x54 "S3NDTR,stream x number of data" hexmask.long.word 0x54 0.--15. 1. "NDT,Number of data items to" line.long 0x58 "S3PAR,stream x peripheral address" hexmask.long 0x58 0.--31. 1. "PA,Peripheral address" line.long 0x5C "S3M0AR,stream x memory 0 address" hexmask.long 0x5C 0.--31. 1. "M0A,Memory 0 address" line.long 0x60 "S3M1AR,stream x memory 1 address" hexmask.long 0x60 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x64 "S3FCR,stream x FIFO control register" bitfld.long 0x64 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x64 3.--6. 1. "FS,FIFO status" bitfld.long 0x64 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x64 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x68 "S4CR,stream x configuration" bitfld.long 0x68 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x68 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x68 20. "ACK,ACK" "0,1" bitfld.long 0x68 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x68 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x68 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x68 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x68 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x68 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x68 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x68 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x68 8. "CIRC,Circular mode" "0,1" bitfld.long 0x68 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x68 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x68 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x68 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x68 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x68 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x68 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x6C "S4NDTR,stream x number of data" hexmask.long.word 0x6C 0.--15. 1. "NDT,Number of data items to" line.long 0x70 "S4PAR,stream x peripheral address" hexmask.long 0x70 0.--31. 1. "PA,Peripheral address" line.long 0x74 "S4M0AR,stream x memory 0 address" hexmask.long 0x74 0.--31. 1. "M0A,Memory 0 address" line.long 0x78 "S4M1AR,stream x memory 1 address" hexmask.long 0x78 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x7C "S4FCR,stream x FIFO control register" bitfld.long 0x7C 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x7C 3.--6. 1. "FS,FIFO status" bitfld.long 0x7C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x7C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x80 "S5CR,stream x configuration" bitfld.long 0x80 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x80 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x80 20. "ACK,ACK" "0,1" bitfld.long 0x80 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x80 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x80 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x80 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x80 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x80 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x80 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x80 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x80 8. "CIRC,Circular mode" "0,1" bitfld.long 0x80 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x80 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x80 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x80 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x80 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x80 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x80 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x84 "S5NDTR,stream x number of data" hexmask.long.word 0x84 0.--15. 1. "NDT,Number of data items to" line.long 0x88 "S5PAR,stream x peripheral address" hexmask.long 0x88 0.--31. 1. "PA,Peripheral address" line.long 0x8C "S5M0AR,stream x memory 0 address" hexmask.long 0x8C 0.--31. 1. "M0A,Memory 0 address" line.long 0x90 "S5M1AR,stream x memory 1 address" hexmask.long 0x90 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x94 "S5FCR,stream x FIFO control register" bitfld.long 0x94 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x94 3.--6. 1. "FS,FIFO status" bitfld.long 0x94 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x94 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x98 "S6CR,stream x configuration" bitfld.long 0x98 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x98 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x98 20. "ACK,ACK" "0,1" bitfld.long 0x98 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x98 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x98 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x98 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x98 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x98 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x98 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x98 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x98 8. "CIRC,Circular mode" "0,1" bitfld.long 0x98 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x98 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x98 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x98 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x98 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x98 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x98 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x9C "S6NDTR,stream x number of data" hexmask.long.word 0x9C 0.--15. 1. "NDT,Number of data items to" line.long 0xA0 "S6PAR,stream x peripheral address" hexmask.long 0xA0 0.--31. 1. "PA,Peripheral address" line.long 0xA4 "S6M0AR,stream x memory 0 address" hexmask.long 0xA4 0.--31. 1. "M0A,Memory 0 address" line.long 0xA8 "S6M1AR,stream x memory 1 address" hexmask.long 0xA8 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xAC "S6FCR,stream x FIFO control register" bitfld.long 0xAC 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0xAC 3.--6. 1. "FS,FIFO status" bitfld.long 0xAC 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xAC 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0xB0 "S7CR,stream x configuration" bitfld.long 0xB0 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0xB0 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0xB0 20. "ACK,ACK" "0,1" bitfld.long 0xB0 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0xB0 18. "DBM,Double buffer mode" "0,1" bitfld.long 0xB0 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0xB0 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0xB0 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0xB0 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0xB0 10. "MINC,Memory increment mode" "0,1" bitfld.long 0xB0 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0xB0 8. "CIRC,Circular mode" "0,1" bitfld.long 0xB0 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0xB0 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0xB0 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0xB0 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0xB0 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0xB0 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0xB0 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xB4 "S7NDTR,stream x number of data" hexmask.long.word 0xB4 0.--15. 1. "NDT,Number of data items to" line.long 0xB8 "S7PAR,stream x peripheral address" hexmask.long 0xB8 0.--31. 1. "PA,Peripheral address" line.long 0xBC "S7M0AR,stream x memory 0 address" hexmask.long 0xBC 0.--31. 1. "M0A,Memory 0 address" line.long 0xC0 "S7M1AR,stream x memory 1 address" hexmask.long 0xC0 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xC4 "S7FCR,stream x FIFO control register" bitfld.long 0xC4 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0xC4 3.--6. 1. "FS,FIFO status" bitfld.long 0xC4 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xC4 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" tree.end tree "DMA2" base ad:0x40020400 rgroup.long 0x0++0x7 line.long 0x0 "LISR,low interrupt status register" bitfld.long 0x0 27. "TCIF3,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 26. "HTIF3,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 25. "TEIF3,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 24. "DMEIF3,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 22. "FEIF3,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "TCIF2,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 20. "HTIF2,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 19. "TEIF2,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 18. "DMEIF2,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 16. "FEIF2,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "TCIF1,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x0 10. "HTIF1,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 9. "TEIF1,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 8. "DMEIF1,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 6. "FEIF1,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "TCIF0,Stream x transfer complete interrupt" "0,1" bitfld.long 0x0 4. "HTIF0,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x0 3. "TEIF0,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x0 2. "DMEIF0,Stream x direct mode error interrupt" "0,1" bitfld.long 0x0 0. "FEIF0,Stream x FIFO error interrupt flag" "0,1" line.long 0x4 "HISR,high interrupt status register" bitfld.long 0x4 27. "TCIF7,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 26. "HTIF7,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 25. "TEIF7,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 24. "DMEIF7,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 22. "FEIF7,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "TCIF6,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 20. "HTIF6,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 19. "TEIF6,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 18. "DMEIF6,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 16. "FEIF6,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "TCIF5,Stream x transfer complete interrupt" "0,1" newline bitfld.long 0x4 10. "HTIF5,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 9. "TEIF5,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 8. "DMEIF5,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 6. "FEIF5,Stream x FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "TCIF4,Stream x transfer complete interrupt" "0,1" bitfld.long 0x4 4. "HTIF4,Stream x half transfer interrupt flag" "0,1" bitfld.long 0x4 3. "TEIF4,Stream x transfer error interrupt flag" "0,1" bitfld.long 0x4 2. "DMEIF4,Stream x direct mode error interrupt" "0,1" bitfld.long 0x4 0. "FEIF4,Stream x FIFO error interrupt flag" "0,1" group.long 0x8++0xC7 line.long 0x0 "LIFCR,low interrupt flag clear" bitfld.long 0x0 27. "CTCIF3,Stream x clear transfer complete" "0,1" bitfld.long 0x0 26. "CHTIF3,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 25. "CTEIF3,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 24. "CDMEIF3,Stream x clear direct mode error" "0,1" bitfld.long 0x0 22. "CFEIF3,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 21. "CTCIF2,Stream x clear transfer complete" "0,1" bitfld.long 0x0 20. "CHTIF2,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 19. "CTEIF2,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 18. "CDMEIF2,Stream x clear direct mode error" "0,1" bitfld.long 0x0 16. "CFEIF2,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 11. "CTCIF1,Stream x clear transfer complete" "0,1" newline bitfld.long 0x0 10. "CHTIF1,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 9. "CTEIF1,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 8. "CDMEIF1,Stream x clear direct mode error" "0,1" bitfld.long 0x0 6. "CFEIF1,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x0 5. "CTCIF0,Stream x clear transfer complete" "0,1" bitfld.long 0x0 4. "CHTIF0,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x0 3. "CTEIF0,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x0 2. "CDMEIF0,Stream x clear direct mode error" "0,1" bitfld.long 0x0 0. "CFEIF0,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x4 "HIFCR,high interrupt flag clear" bitfld.long 0x4 27. "CTCIF7,Stream x clear transfer complete" "0,1" bitfld.long 0x4 26. "CHTIF7,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 25. "CTEIF7,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 24. "CDMEIF7,Stream x clear direct mode error" "0,1" bitfld.long 0x4 22. "CFEIF7,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 21. "CTCIF6,Stream x clear transfer complete" "0,1" bitfld.long 0x4 20. "CHTIF6,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 19. "CTEIF6,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 18. "CDMEIF6,Stream x clear direct mode error" "0,1" bitfld.long 0x4 16. "CFEIF6,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 11. "CTCIF5,Stream x clear transfer complete" "0,1" newline bitfld.long 0x4 10. "CHTIF5,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 9. "CTEIF5,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 8. "CDMEIF5,Stream x clear direct mode error" "0,1" bitfld.long 0x4 6. "CFEIF5,Stream x clear FIFO error interrupt flag" "0,1" bitfld.long 0x4 5. "CTCIF4,Stream x clear transfer complete" "0,1" bitfld.long 0x4 4. "CHTIF4,Stream x clear half transfer interrupt" "0,1" bitfld.long 0x4 3. "CTEIF4,Stream x clear transfer error interrupt" "0,1" bitfld.long 0x4 2. "CDMEIF4,Stream x clear direct mode error" "0,1" bitfld.long 0x4 0. "CFEIF4,Stream x clear FIFO error interrupt flag" "0,1" line.long 0x8 "S0CR,stream x configuration" bitfld.long 0x8 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x8 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x8 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x8 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x8 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x8 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x8 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x8 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x8 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x8 9. "PINC,Peripheral increment mode" "0,1" bitfld.long 0x8 8. "CIRC,Circular mode" "0,1" newline bitfld.long 0x8 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x8 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x8 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x8 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x8 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x8 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x8 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xC "S0NDTR,stream x number of data" hexmask.long.word 0xC 0.--15. 1. "NDT,Number of data items to" line.long 0x10 "S0PAR,stream x peripheral address" hexmask.long 0x10 0.--31. 1. "PA,Peripheral address" line.long 0x14 "S0M0AR,stream x memory 0 address" hexmask.long 0x14 0.--31. 1. "M0A,Memory 0 address" line.long 0x18 "S0M1AR,stream x memory 1 address" hexmask.long 0x18 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x1C "S0FCR,stream x FIFO control register" bitfld.long 0x1C 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x1C 3.--6. 1. "FS,FIFO status" bitfld.long 0x1C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x1C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x20 "S1CR,stream x configuration" bitfld.long 0x20 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x20 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x20 20. "ACK,ACK" "0,1" bitfld.long 0x20 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x20 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x20 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x20 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x20 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x20 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x20 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x20 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x20 8. "CIRC,Circular mode" "0,1" bitfld.long 0x20 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x20 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x20 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x20 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x20 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x20 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x20 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x24 "S1NDTR,stream x number of data" hexmask.long.word 0x24 0.--15. 1. "NDT,Number of data items to" line.long 0x28 "S1PAR,stream x peripheral address" hexmask.long 0x28 0.--31. 1. "PA,Peripheral address" line.long 0x2C "S1M0AR,stream x memory 0 address" hexmask.long 0x2C 0.--31. 1. "M0A,Memory 0 address" line.long 0x30 "S1M1AR,stream x memory 1 address" hexmask.long 0x30 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x34 "S1FCR,stream x FIFO control register" bitfld.long 0x34 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x34 3.--6. 1. "FS,FIFO status" bitfld.long 0x34 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x34 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x38 "S2CR,stream x configuration" bitfld.long 0x38 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x38 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x38 20. "ACK,ACK" "0,1" bitfld.long 0x38 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x38 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x38 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x38 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x38 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x38 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x38 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x38 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x38 8. "CIRC,Circular mode" "0,1" bitfld.long 0x38 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x38 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x38 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x38 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x38 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x38 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x38 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x3C "S2NDTR,stream x number of data" hexmask.long.word 0x3C 0.--15. 1. "NDT,Number of data items to" line.long 0x40 "S2PAR,stream x peripheral address" hexmask.long 0x40 0.--31. 1. "PA,Peripheral address" line.long 0x44 "S2M0AR,stream x memory 0 address" hexmask.long 0x44 0.--31. 1. "M0A,Memory 0 address" line.long 0x48 "S2M1AR,stream x memory 1 address" hexmask.long 0x48 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x4C "S2FCR,stream x FIFO control register" bitfld.long 0x4C 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x4C 3.--6. 1. "FS,FIFO status" bitfld.long 0x4C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x4C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x50 "S3CR,stream x configuration" bitfld.long 0x50 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x50 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x50 20. "ACK,ACK" "0,1" bitfld.long 0x50 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x50 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x50 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x50 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x50 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x50 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x50 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x50 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x50 8. "CIRC,Circular mode" "0,1" bitfld.long 0x50 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x50 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x50 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x50 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x50 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x50 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x50 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x54 "S3NDTR,stream x number of data" hexmask.long.word 0x54 0.--15. 1. "NDT,Number of data items to" line.long 0x58 "S3PAR,stream x peripheral address" hexmask.long 0x58 0.--31. 1. "PA,Peripheral address" line.long 0x5C "S3M0AR,stream x memory 0 address" hexmask.long 0x5C 0.--31. 1. "M0A,Memory 0 address" line.long 0x60 "S3M1AR,stream x memory 1 address" hexmask.long 0x60 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x64 "S3FCR,stream x FIFO control register" bitfld.long 0x64 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x64 3.--6. 1. "FS,FIFO status" bitfld.long 0x64 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x64 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x68 "S4CR,stream x configuration" bitfld.long 0x68 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x68 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x68 20. "ACK,ACK" "0,1" bitfld.long 0x68 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x68 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x68 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x68 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x68 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x68 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x68 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x68 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x68 8. "CIRC,Circular mode" "0,1" bitfld.long 0x68 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x68 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x68 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x68 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x68 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x68 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x68 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x6C "S4NDTR,stream x number of data" hexmask.long.word 0x6C 0.--15. 1. "NDT,Number of data items to" line.long 0x70 "S4PAR,stream x peripheral address" hexmask.long 0x70 0.--31. 1. "PA,Peripheral address" line.long 0x74 "S4M0AR,stream x memory 0 address" hexmask.long 0x74 0.--31. 1. "M0A,Memory 0 address" line.long 0x78 "S4M1AR,stream x memory 1 address" hexmask.long 0x78 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x7C "S4FCR,stream x FIFO control register" bitfld.long 0x7C 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x7C 3.--6. 1. "FS,FIFO status" bitfld.long 0x7C 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x7C 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x80 "S5CR,stream x configuration" bitfld.long 0x80 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x80 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x80 20. "ACK,ACK" "0,1" bitfld.long 0x80 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x80 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x80 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x80 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x80 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x80 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x80 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x80 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x80 8. "CIRC,Circular mode" "0,1" bitfld.long 0x80 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x80 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x80 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x80 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x80 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x80 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x80 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x84 "S5NDTR,stream x number of data" hexmask.long.word 0x84 0.--15. 1. "NDT,Number of data items to" line.long 0x88 "S5PAR,stream x peripheral address" hexmask.long 0x88 0.--31. 1. "PA,Peripheral address" line.long 0x8C "S5M0AR,stream x memory 0 address" hexmask.long 0x8C 0.--31. 1. "M0A,Memory 0 address" line.long 0x90 "S5M1AR,stream x memory 1 address" hexmask.long 0x90 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0x94 "S5FCR,stream x FIFO control register" bitfld.long 0x94 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0x94 3.--6. 1. "FS,FIFO status" bitfld.long 0x94 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0x94 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0x98 "S6CR,stream x configuration" bitfld.long 0x98 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0x98 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0x98 20. "ACK,ACK" "0,1" bitfld.long 0x98 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0x98 18. "DBM,Double buffer mode" "0,1" bitfld.long 0x98 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0x98 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0x98 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0x98 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0x98 10. "MINC,Memory increment mode" "0,1" bitfld.long 0x98 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0x98 8. "CIRC,Circular mode" "0,1" bitfld.long 0x98 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0x98 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0x98 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x98 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0x98 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0x98 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0x98 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0x9C "S6NDTR,stream x number of data" hexmask.long.word 0x9C 0.--15. 1. "NDT,Number of data items to" line.long 0xA0 "S6PAR,stream x peripheral address" hexmask.long 0xA0 0.--31. 1. "PA,Peripheral address" line.long 0xA4 "S6M0AR,stream x memory 0 address" hexmask.long 0xA4 0.--31. 1. "M0A,Memory 0 address" line.long 0xA8 "S6M1AR,stream x memory 1 address" hexmask.long 0xA8 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xAC "S6FCR,stream x FIFO control register" bitfld.long 0xAC 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0xAC 3.--6. 1. "FS,FIFO status" bitfld.long 0xAC 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xAC 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" line.long 0xB0 "S7CR,stream x configuration" bitfld.long 0xB0 23.--24. "MBURST,Memory burst transfer" "0,1,2,3" bitfld.long 0xB0 21.--22. "PBURST,Peripheral burst transfer" "0,1,2,3" bitfld.long 0xB0 20. "ACK,ACK" "0,1" bitfld.long 0xB0 19. "CT,Current target (only in double buffer" "0,1" bitfld.long 0xB0 18. "DBM,Double buffer mode" "0,1" bitfld.long 0xB0 16.--17. "PL,Priority level" "0,1,2,3" bitfld.long 0xB0 15. "PINCOS,Peripheral increment offset" "0,1" bitfld.long 0xB0 13.--14. "MSIZE,Memory data size" "0,1,2,3" bitfld.long 0xB0 11.--12. "PSIZE,Peripheral data size" "0,1,2,3" bitfld.long 0xB0 10. "MINC,Memory increment mode" "0,1" bitfld.long 0xB0 9. "PINC,Peripheral increment mode" "0,1" newline bitfld.long 0xB0 8. "CIRC,Circular mode" "0,1" bitfld.long 0xB0 6.--7. "DIR,Data transfer direction" "0,1,2,3" bitfld.long 0xB0 5. "PFCTRL,Peripheral flow controller" "0,1" bitfld.long 0xB0 4. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0xB0 3. "HTIE,Half transfer interrupt" "0,1" bitfld.long 0xB0 2. "TEIE,Transfer error interrupt" "0,1" bitfld.long 0xB0 1. "DMEIE,Direct mode error interrupt" "0,1" bitfld.long 0xB0 0. "EN,Stream enable / flag stream ready when" "0,1" line.long 0xB4 "S7NDTR,stream x number of data" hexmask.long.word 0xB4 0.--15. 1. "NDT,Number of data items to" line.long 0xB8 "S7PAR,stream x peripheral address" hexmask.long 0xB8 0.--31. 1. "PA,Peripheral address" line.long 0xBC "S7M0AR,stream x memory 0 address" hexmask.long 0xBC 0.--31. 1. "M0A,Memory 0 address" line.long 0xC0 "S7M1AR,stream x memory 1 address" hexmask.long 0xC0 0.--31. 1. "M1A,Memory 1 address (used in case of Double" line.long 0xC4 "S7FCR,stream x FIFO control register" bitfld.long 0xC4 7. "FEIE,FIFO error interrupt" "0,1" hexmask.long.byte 0xC4 3.--6. 1. "FS,FIFO status" bitfld.long 0xC4 2. "DMDIS,Direct mode disable" "0,1" bitfld.long 0xC4 0.--1. "FTH,FIFO threshold selection" "0,1,2,3" tree.end endif tree.end tree "DMA2D (Chrom-ART Accelerator Controller)" base ad:0x52001000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H750*")) group.long 0x0++0x3 line.long 0x0 "DMA2D_CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DMA2D_ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "DMA2D_IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "DMA2D_FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "DMA2D_FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "DMA2D_BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "DMA2D_BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "DMA2D_FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "DMA2D_FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "DMA2D_BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "DMA2D_BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "DMA2D_FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "DMA2D_BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "DMA2D_OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "DMA2D_OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "DMA2D_OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "DMA2D_OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "DMA2D_NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "DMA2D_LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "DMA2D_AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H753*")) group.long 0x0++0x3 line.long 0x0 "CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x3 line.long 0x0 "CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x3 line.long 0x0 "CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x3 line.long 0x0 "CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "DFGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline bitfld.long 0x2C 0.--2. "CM,Color mode These bits define the color" "0,1,2,3,4,5,6,7" line.long 0x30 "OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x3 line.long 0x0 "DMA2D_CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DMA2D_ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "DMA2D_IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "DMA2D_FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "DMA2D_FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "DMA2D_BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "DMA2D_BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "DMA2D_FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "DMA2D_FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "DMA2D_BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "DMA2D_BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "DMA2D_FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "DMA2D_BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "DMA2D_OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline hexmask.long.byte 0x2C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x30 "DMA2D_OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "DMA2D_OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "DMA2D_OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "DMA2D_NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "DMA2D_LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "DMA2D_AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x3 line.long 0x0 "DMA2D_CR,DMA2D control register" bitfld.long 0x0 16.--17. "MODE,DMA2D mode This bit is set and cleared" "0,1,2,3" bitfld.long 0x0 13. "CEIE,Configuration Error Interrupt Enable" "0,1" newline bitfld.long 0x0 12. "CTCIE,CLUT transfer complete interrupt enable" "0,1" bitfld.long 0x0 11. "CAEIE,CLUT access error interrupt enable This" "0,1" newline bitfld.long 0x0 10. "TWIE,Transfer watermark interrupt enable This" "0,1" bitfld.long 0x0 9. "TCIE,Transfer complete interrupt enable This" "0,1" newline bitfld.long 0x0 8. "TEIE,Transfer error interrupt enable This bit" "0,1" bitfld.long 0x0 2. "ABORT,Abort This bit can be used to abort the" "0,1" newline bitfld.long 0x0 1. "SUSP,Suspend This bit can be used to suspend" "0,1" bitfld.long 0x0 0. "START,Start This bit can be used to launch the" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "DMA2D_ISR,DMA2D Interrupt Status" bitfld.long 0x0 5. "CEIF,Configuration error interrupt flag This" "0,1" bitfld.long 0x0 4. "CTCIF,CLUT transfer complete interrupt flag" "0,1" newline bitfld.long 0x0 3. "CAEIF,CLUT access error interrupt flag This" "0,1" bitfld.long 0x0 2. "TWIF,Transfer watermark interrupt flag This" "0,1" newline bitfld.long 0x0 1. "TCIF,Transfer complete interrupt flag This" "0,1" bitfld.long 0x0 0. "TEIF,Transfer error interrupt flag This bit" "0,1" group.long 0x8++0x47 line.long 0x0 "DMA2D_IFCR,DMA2D interrupt flag clear" bitfld.long 0x0 5. "CCEIF,Clear configuration error interrupt flag" "0,1" bitfld.long 0x0 4. "CCTCIF,Clear CLUT transfer complete interrupt" "0,1" newline bitfld.long 0x0 3. "CAECIF,Clear CLUT access error interrupt flag" "0,1" bitfld.long 0x0 2. "CTWIF,Clear transfer watermark interrupt flag" "0,1" newline bitfld.long 0x0 1. "CTCIF,Clear transfer complete interrupt flag" "0,1" bitfld.long 0x0 0. "CTEIF,Clear Transfer error interrupt flag" "0,1" line.long 0x4 "DMA2D_FGMAR,DMA2D foreground memory address" hexmask.long 0x4 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x8 "DMA2D_FGOR,DMA2D foreground offset" hexmask.long.word 0x8 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0xC "DMA2D_BGMAR,DMA2D background memory address" hexmask.long 0xC 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x10 "DMA2D_BGOR,DMA2D background offset" hexmask.long.word 0x10 0.--13. 1. "LO,Line offset Line offset used for the" line.long 0x14 "DMA2D_FGPFCCR,DMA2D foreground PFC control" hexmask.long.byte 0x14 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x14 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x14 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x14 18.--19. "CSS,Chroma Sub-Sampling These bits define" "0,1,2,3" newline bitfld.long 0x14 16.--17. "AM,Alpha mode These bits select the alpha" "0,1,2,3" hexmask.long.byte 0x14 8.--15. 1. "CS,CLUT size These bits define the size of" newline bitfld.long 0x14 5. "START,Start This bit can be set to start the" "0,1" bitfld.long 0x14 4. "CCM,CLUT color mode This bit defines the" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "CM,Color mode These bits defines the color" line.long 0x18 "DMA2D_FGCOLR,DMA2D foreground color" hexmask.long.byte 0x18 16.--23. 1. "RED,Red Value These bits defines the red" hexmask.long.byte 0x18 8.--15. 1. "GREEN,Green Value These bits defines the green" newline hexmask.long.byte 0x18 0.--7. 1. "BLUE,Blue Value These bits defines the blue" line.long 0x1C "DMA2D_BGPFCCR,DMA2D background PFC control" hexmask.long.byte 0x1C 24.--31. 1. "ALPHA,Alpha value These bits define a fixed" bitfld.long 0x1C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" newline bitfld.long 0x1C 20. "AI,Alpha Inverted This bit inverts the" "0,1" bitfld.long 0x1C 16.--17. "AM,Alpha mode These bits define which alpha" "0,1,2,3" newline hexmask.long.byte 0x1C 8.--15. 1. "CS,CLUT size These bits define the size of" bitfld.long 0x1C 5. "START,Start This bit is set to start the" "0,1" newline bitfld.long 0x1C 4. "CCM,CLUT Color mode These bits define the" "0,1" hexmask.long.byte 0x1C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x20 "DMA2D_BGCOLR,DMA2D background color" hexmask.long.byte 0x20 16.--23. 1. "RED,Red Value These bits define the red" hexmask.long.byte 0x20 8.--15. 1. "GREEN,Green Value These bits define the green" newline hexmask.long.byte 0x20 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x24 "DMA2D_FGCMAR,DMA2D foreground CLUT memory address" hexmask.long 0x24 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x28 "DMA2D_BGCMAR,DMA2D background CLUT memory address" hexmask.long 0x28 0.--31. 1. "MA,Memory address Address of the data used" line.long 0x2C "DMA2D_OPFCCR,DMA2D output PFC control" bitfld.long 0x2C 21. "RBS,Red Blue Swap This bit allows to swap" "0,1" bitfld.long 0x2C 20. "AI,Alpha Inverted This bit inverts the" "0,1" newline hexmask.long.byte 0x2C 0.--3. 1. "CM,Color mode These bits define the color" line.long 0x30 "DMA2D_OCOLR,DMA2D output color register" hexmask.long.byte 0x30 24.--31. 1. "ALPHA,Alpha Channel Value These bits define" hexmask.long.byte 0x30 16.--23. 1. "RED,Red Value These bits define the red" newline hexmask.long.byte 0x30 8.--15. 1. "GREEN,Green Value These bits define the green" hexmask.long.byte 0x30 0.--7. 1. "BLUE,Blue Value These bits define the blue" line.long 0x34 "DMA2D_OMAR,DMA2D output memory address" hexmask.long 0x34 0.--31. 1. "MA,Memory Address Address of the data used" line.long 0x38 "DMA2D_OOR,DMA2D output offset register" hexmask.long.word 0x38 0.--13. 1. "LO,Line Offset Line offset used for the" line.long 0x3C "DMA2D_NLR,DMA2D number of line register" hexmask.long.word 0x3C 16.--29. 1. "PL,Pixel per lines Number of pixels per" hexmask.long.word 0x3C 0.--15. 1. "NL,Number of lines Number of lines of the" line.long 0x40 "DMA2D_LWR,DMA2D line watermark register" hexmask.long.word 0x40 0.--15. 1. "LW,Line watermark These bits allow to" line.long 0x44 "DMA2D_AMTCR,DMA2D AXI master timer configuration" hexmask.long.byte 0x44 8.--15. 1. "DT,Dead Time Dead time value in the AXI" bitfld.long 0x44 0. "EN,Enable Enables the dead time" "0,1" endif tree.end tree "DMAMUX (DMA Request Multiplexer)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")) tree "DMAMUX1" base ad:0x40020800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) group.long 0x0++0x3F line.long 0x0 "DMAMUX_C0CR," bitfld.long 0x0 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x0 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x4 "DMAMUX_C1CR," bitfld.long 0x4 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x4 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x4 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x4 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x8 "DMAMUX_C2CR," bitfld.long 0x8 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x8 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x8 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x8 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0xC "DMAMUX_C3CR," bitfld.long 0xC 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0xC 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0xC 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0xC 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x10 "DMAMUX_C4CR," bitfld.long 0x10 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x10 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x10 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x10 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x14 "DMAMUX_C5CR," bitfld.long 0x14 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x14 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x14 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x14 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x18 "DMAMUX_C6CR," bitfld.long 0x18 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x18 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x18 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x18 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x1C "DMAMUX_C7CR," bitfld.long 0x1C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x1C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x1C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x1C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x1C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x1C 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x20 "DMAMUX_C8CR," bitfld.long 0x20 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x20 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x20 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x20 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x20 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x20 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x24 "DMAMUX_C9CR," bitfld.long 0x24 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x24 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x24 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x24 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x24 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x24 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x28 "DMAMUX_C10CR," bitfld.long 0x28 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x28 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x28 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x28 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x28 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x28 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x2C "DMAMUX_C11CR," bitfld.long 0x2C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x2C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x2C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x2C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x2C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x2C 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x30 "DMAMUX_C12CR," bitfld.long 0x30 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x30 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x30 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x30 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x30 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x30 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x34 "DMAMUX_C13CR," bitfld.long 0x34 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x34 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x34 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x34 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x34 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x34 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x38 "DMAMUX_C14CR," bitfld.long 0x38 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x38 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x38 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x38 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x38 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x38 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x3C "DMAMUX_C15CR," bitfld.long 0x3C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x3C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x3C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x3C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x3C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x3C 0.--6. 1. "DMAREQ_ID,DMA request identification" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX_CSR," bitfld.long 0x0 15. "SOF15,Synchronization overrun event flag" "?,?" bitfld.long 0x0 14. "SOF14,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 13. "SOF13,Synchronization overrun event flag" "?,?" bitfld.long 0x0 12. "SOF12,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 11. "SOF11,Synchronization overrun event flag" "?,?" bitfld.long 0x0 10. "SOF10,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 9. "SOF9,Synchronization overrun event flag" "?,?" bitfld.long 0x0 8. "SOF8,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 7. "SOF7,Synchronization overrun event flag" "?,?" bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "?,?" bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "?,?" bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "?,?" bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "?,?" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX_CFR," bitfld.long 0x0 15. "CSOF15,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 14. "CSOF14,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 13. "CSOF13,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 12. "CSOF12,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 11. "CSOF11,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 10. "CSOF10,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 9. "CSOF9,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 8. "CSOF8,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 7. "CSOF7,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1" group.long 0x100++0x1F line.long 0x0 "DMAMUX_RG0CR," hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x0 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x4 "DMAMUX_RG1CR," hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x4 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x8 "DMAMUX_RG2CR," hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x8 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0xC "DMAMUX_RG3CR," hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0xC 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x10 "DMAMUX_RG4CR," hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x10 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x10 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x10 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x14 "DMAMUX_RG5CR," hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x14 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x14 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x14 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x18 "DMAMUX_RG6CR," hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x18 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x18 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x18 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x1C "DMAMUX_RG7CR," hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x1C 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x1C 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x1C 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX_RGSR," bitfld.long 0x0 7. "OF7,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 6. "OF6,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 5. "OF5,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 4. "OF4,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 3. "OF3,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 2. "OF2,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 1. "OF1,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 0. "OF0,[:0]: Trigger overrun event flag" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX_RGCFR," bitfld.long 0x0 7. "COF7,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 6. "COF6,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 5. "COF5,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 4. "COF4,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1" endif sif (cpuis("STM32H745??-CM4")) group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" endif sif (cpuis("STM32H745??-CM4")) rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" endif tree.end endif sif (cpuis("STM32H745??-CM7")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H750*")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "DMAMUX_C0CR," bitfld.long 0x0 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x0 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x4 "DMAMUX_C1CR," bitfld.long 0x4 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x4 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x4 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x4 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x8 "DMAMUX_C2CR," bitfld.long 0x8 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x8 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x8 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x8 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0xC "DMAMUX_C3CR," bitfld.long 0xC 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0xC 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0xC 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0xC 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x10 "DMAMUX_C4CR," bitfld.long 0x10 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x10 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x10 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x10 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x14 "DMAMUX_C5CR," bitfld.long 0x14 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x14 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x14 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x14 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x18 "DMAMUX_C6CR," bitfld.long 0x18 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x18 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x18 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x18 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x1C "DMAMUX_C7CR," bitfld.long 0x1C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x1C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x1C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x1C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x1C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x1C 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x20 "DMAMUX_C8CR," bitfld.long 0x20 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x20 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x20 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x20 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x20 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x20 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x24 "DMAMUX_C9CR," bitfld.long 0x24 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x24 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x24 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x24 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x24 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x24 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x28 "DMAMUX_C10CR," bitfld.long 0x28 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x28 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x28 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x28 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x28 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x28 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x2C "DMAMUX_C11CR," bitfld.long 0x2C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x2C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x2C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x2C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x2C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x2C 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x30 "DMAMUX_C12CR," bitfld.long 0x30 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x30 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x30 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x30 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x30 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x30 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x34 "DMAMUX_C13CR," bitfld.long 0x34 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x34 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x34 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x34 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x34 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x34 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x38 "DMAMUX_C14CR," bitfld.long 0x38 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x38 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x38 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x38 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x38 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x38 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x3C "DMAMUX_C15CR," bitfld.long 0x3C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x3C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x3C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x3C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x3C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x3C 0.--6. 1. "DMAREQ_ID,DMA request identification" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX_CSR," bitfld.long 0x0 15. "SOF15,Synchronization overrun event flag" "?,?" bitfld.long 0x0 14. "SOF14,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 13. "SOF13,Synchronization overrun event flag" "?,?" bitfld.long 0x0 12. "SOF12,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 11. "SOF11,Synchronization overrun event flag" "?,?" bitfld.long 0x0 10. "SOF10,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 9. "SOF9,Synchronization overrun event flag" "?,?" bitfld.long 0x0 8. "SOF8,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 7. "SOF7,Synchronization overrun event flag" "?,?" bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "?,?" bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "?,?" bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "?,?" bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "?,?" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX_CFR," bitfld.long 0x0 15. "CSOF15,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 14. "CSOF14,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 13. "CSOF13,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 12. "CSOF12,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 11. "CSOF11,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 10. "CSOF10,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 9. "CSOF9,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 8. "CSOF8,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 7. "CSOF7,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1" group.long 0x100++0x1F line.long 0x0 "DMAMUX_RG0CR," hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x0 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x4 "DMAMUX_RG1CR," hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x4 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x8 "DMAMUX_RG2CR," hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x8 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0xC "DMAMUX_RG3CR," hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0xC 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x10 "DMAMUX_RG4CR," hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x10 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x10 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x10 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x14 "DMAMUX_RG5CR," hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x14 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x14 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x14 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x18 "DMAMUX_RG6CR," hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x18 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x18 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x18 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x1C "DMAMUX_RG7CR," hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x1C 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x1C 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x1C 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX_RGSR," bitfld.long 0x0 7. "OF7,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 6. "OF6,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 5. "OF5,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 4. "OF4,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 3. "OF3,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 2. "OF2,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 1. "OF1,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 0. "OF0,[:0]: Trigger overrun event flag" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX_RGCFR," bitfld.long 0x0 7. "COF7,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 6. "COF6,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 5. "COF5,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 4. "COF4,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "DMAMUX2" base ad:0x58025800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x1F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" endif sif (cpuis("STM32H750*")) group.long 0x0++0x1F line.long 0x0 "DMAMUX2_C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "DMAMUX2_C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "DMAMUX2_C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "DMAMUX2_C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "DMAMUX2_C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "DMAMUX2_C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "DMAMUX2_C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "DMAMUX2_C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" newline bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" newline bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" newline hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "DMAMUX2_RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "DMAMUX2_RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "DMAMUX2_RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "DMAMUX2_RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "DMAMUX2_RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "DMAMUX2_RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "DMAMUX2_RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "DMAMUX2_RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" newline bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" newline hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX2_RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX2_RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" endif sif (cpuis("STM32H750*")) rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX2_CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX2_CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" endif tree.end endif sif (cpuis("STM32H753*")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "DMAMUX_C0CR," bitfld.long 0x0 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x0 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x4 "DMAMUX_C1CR," bitfld.long 0x4 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x4 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x4 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x4 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x8 "DMAMUX_C2CR," bitfld.long 0x8 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x8 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x8 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x8 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0xC "DMAMUX_C3CR," bitfld.long 0xC 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0xC 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0xC 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0xC 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x10 "DMAMUX_C4CR," bitfld.long 0x10 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x10 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x10 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x10 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x14 "DMAMUX_C5CR," bitfld.long 0x14 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x14 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x14 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x14 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x18 "DMAMUX_C6CR," bitfld.long 0x18 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x18 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x18 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x18 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x1C "DMAMUX_C7CR," bitfld.long 0x1C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x1C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x1C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x1C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x1C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x1C 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x20 "DMAMUX_C8CR," bitfld.long 0x20 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x20 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x20 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x20 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x20 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x20 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x24 "DMAMUX_C9CR," bitfld.long 0x24 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x24 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x24 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x24 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x24 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x24 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x28 "DMAMUX_C10CR," bitfld.long 0x28 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x28 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x28 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x28 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x28 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x28 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x2C "DMAMUX_C11CR," bitfld.long 0x2C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x2C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x2C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x2C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x2C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x2C 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x30 "DMAMUX_C12CR," bitfld.long 0x30 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x30 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x30 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x30 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x30 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x30 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x34 "DMAMUX_C13CR," bitfld.long 0x34 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x34 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x34 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x34 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x34 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x34 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x38 "DMAMUX_C14CR," bitfld.long 0x38 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x38 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x38 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x38 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x38 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x38 0.--6. 1. "DMAREQ_ID,DMA request identification" line.long 0x3C "DMAMUX_C15CR," bitfld.long 0x3C 24.--26. "SYNC_ID,Synchronization identification" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward" newline bitfld.long 0x3C 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges" bitfld.long 0x3C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled" newline bitfld.long 0x3C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled" bitfld.long 0x3C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled" newline hexmask.long.byte 0x3C 0.--6. 1. "DMAREQ_ID,DMA request identification" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX_CSR," bitfld.long 0x0 15. "SOF15,Synchronization overrun event flag" "?,?" bitfld.long 0x0 14. "SOF14,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 13. "SOF13,Synchronization overrun event flag" "?,?" bitfld.long 0x0 12. "SOF12,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 11. "SOF11,Synchronization overrun event flag" "?,?" bitfld.long 0x0 10. "SOF10,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 9. "SOF9,Synchronization overrun event flag" "?,?" bitfld.long 0x0 8. "SOF8,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 7. "SOF7,Synchronization overrun event flag" "?,?" bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "?,?" bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "?,?" bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "?,?" newline bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "?,?" bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "?,?" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX_CFR," bitfld.long 0x0 15. "CSOF15,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 14. "CSOF14,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 13. "CSOF13,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 12. "CSOF12,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 11. "CSOF11,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 10. "CSOF10,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 9. "CSOF9,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 8. "CSOF8,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 7. "CSOF7,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1" newline bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1" bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1" group.long 0x100++0x1F line.long 0x0 "DMAMUX_RG0CR," hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x0 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x4 "DMAMUX_RG1CR," hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x4 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x8 "DMAMUX_RG2CR," hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x8 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0xC "DMAMUX_RG3CR," hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0xC 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x10 "DMAMUX_RG4CR," hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x10 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x10 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x10 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x14 "DMAMUX_RG5CR," hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x14 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x14 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x14 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x18 "DMAMUX_RG6CR," hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x18 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x18 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x18 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" line.long 0x1C "DMAMUX_RG7CR," hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges" newline bitfld.long 0x1C 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled" bitfld.long 0x1C 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.." newline bitfld.long 0x1C 0.--2. "SIG_ID,Signal identification" "0,1,2,3,4,5,6,7" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX_RGSR," bitfld.long 0x0 7. "OF7,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 6. "OF6,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 5. "OF5,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 4. "OF4,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 3. "OF3,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 2. "OF2,[:0]: Trigger overrun event flag" "0,1" newline bitfld.long 0x0 1. "OF1,[:0]: Trigger overrun event flag" "0,1" bitfld.long 0x0 0. "OF0,[:0]: Trigger overrun event flag" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX_RGCFR," bitfld.long 0x0 7. "COF7,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 6. "COF6,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 5. "COF5,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 4. "COF4,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1" newline bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1" bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1" tree.end tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H7A3*")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "DMAMUX1_C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "DMAMUX1_C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "DMAMUX1_C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "DMAMUX1_C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "DMAMUX1_C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "DMAMUX1_C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "DMAMUX1_C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "DMAMUX1_C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "DMAMUX1_C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "DMAMUX1_C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "DMAMUX1_C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "DMAMUX1_C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "DMAMUX1_C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "DMAMUX1_C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "DMAMUX1_C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "DMAMUX1_C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "DMAMUX1_RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "DMAMUX1_RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "DMAMUX1_RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "DMAMUX1_RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "DMAMUX1_RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "DMAMUX1_RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "DMAMUX1_RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "DMAMUX1_RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX1_RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX1_RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX1_CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX1_CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H7B0*")) tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "DMAMUX2_C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "DMAMUX2_C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "DMAMUX2_C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "DMAMUX2_C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "DMAMUX2_C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "DMAMUX2_C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "DMAMUX2_C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "DMAMUX2_C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "DMAMUX2_RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "DMAMUX2_RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "DMAMUX2_RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "DMAMUX2_RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "DMAMUX2_RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "DMAMUX2_RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "DMAMUX2_RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "DMAMUX2_RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX2_RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX2_RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX2_CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX2_CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H7B0*")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "DMAMUX1_C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "DMAMUX1_C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "DMAMUX1_C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "DMAMUX1_C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "DMAMUX1_C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "DMAMUX1_C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "DMAMUX1_C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "DMAMUX1_C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "DMAMUX1_C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "DMAMUX1_C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "DMAMUX1_C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "DMAMUX1_C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "DMAMUX1_C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "DMAMUX1_C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "DMAMUX1_C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "DMAMUX1_C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "DMAMUX1_RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "DMAMUX1_RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "DMAMUX1_RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "DMAMUX1_RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "DMAMUX1_RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "DMAMUX1_RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "DMAMUX1_RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "DMAMUX1_RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX1_RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX1_RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX1_CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX1_CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif sif (cpuis("STM32H7B3*")) tree "DMAMUX1" base ad:0x40020800 group.long 0x0++0x3F line.long 0x0 "DMAMUX1_C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "DMAMUX1_C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "DMAMUX1_C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "DMAMUX1_C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "DMAMUX1_C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "DMAMUX1_C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "DMAMUX1_C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "DMAMUX1_C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x20 "DMAMUX1_C8CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x20 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x20 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x20 9. "EGE,Event generation" "0,1" bitfld.long 0x20 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x20 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x24 "DMAMUX1_C9CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x24 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x24 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x24 9. "EGE,Event generation" "0,1" bitfld.long 0x24 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x24 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x28 "DMAMUX1_C10CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x28 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x28 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x28 9. "EGE,Event generation" "0,1" bitfld.long 0x28 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x28 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x2C "DMAMUX1_C11CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x2C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x2C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x2C 9. "EGE,Event generation" "0,1" bitfld.long 0x2C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x2C 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x30 "DMAMUX1_C12CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x30 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x30 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x30 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x30 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x30 9. "EGE,Event generation" "0,1" bitfld.long 0x30 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x30 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x34 "DMAMUX1_C13CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x34 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x34 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x34 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x34 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x34 9. "EGE,Event generation" "0,1" bitfld.long 0x34 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x34 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x38 "DMAMUX1_C14CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x38 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x38 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x38 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x38 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x38 9. "EGE,Event generation" "0,1" bitfld.long 0x38 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x38 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x3C "DMAMUX1_C15CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x3C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x3C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x3C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x3C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x3C 9. "EGE,Event generation" "0,1" bitfld.long 0x3C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x3C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "DMAMUX1_RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "DMAMUX1_RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "DMAMUX1_RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "DMAMUX1_RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "DMAMUX1_RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "DMAMUX1_RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "DMAMUX1_RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "DMAMUX1_RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX1_RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX1_RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX1_CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX1_CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end tree "DMAMUX2" base ad:0x58025800 group.long 0x0++0x1F line.long 0x0 "DMAMUX2_C0CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x0 9. "EGE,Event generation" "0,1" bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x4 "DMAMUX2_C1CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x4 9. "EGE,Event generation" "0,1" bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x8 "DMAMUX2_C2CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x8 9. "EGE,Event generation" "0,1" bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0xC "DMAMUX2_C3CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0xC 9. "EGE,Event generation" "0,1" bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x10 "DMAMUX2_C4CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x10 9. "EGE,Event generation" "0,1" bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x14 "DMAMUX2_C5CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x14 9. "EGE,Event generation" "0,1" bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x18 "DMAMUX2_C6CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x18 9. "EGE,Event generation" "0,1" bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line" line.long 0x1C "DMAMUX2_C7CR,DMAMux - DMA request line multiplexer" hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization input" hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests to forward" bitfld.long 0x1C 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3" bitfld.long 0x1C 16. "SE,Synchronous operating mode" "0,1" bitfld.long 0x1C 9. "EGE,Event generation" "0,1" bitfld.long 0x1C 8. "SOIE,Interrupt enable at synchronization" "0,1" hexmask.long.byte 0x1C 0.--7. 1. "DMAREQ_ID,Input DMA request line" group.long 0x100++0x1F line.long 0x0 "DMAMUX2_RG0CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x4 "DMAMUX2_RG1CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x8 "DMAMUX2_RG2CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0xC "DMAMUX2_RG3CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1" bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x10 "DMAMUX2_RG4CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x10 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x10 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x10 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x10 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x10 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x14 "DMAMUX2_RG5CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x14 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x14 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x14 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x14 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x14 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x18 "DMAMUX2_RG6CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x18 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x18 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x18 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x18 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x18 0.--4. 1. "SIG_ID,DMA request trigger input" line.long 0x1C "DMAMUX2_RG7CR,DMAMux - DMA request generator channel x" hexmask.long.byte 0x1C 19.--23. 1. "GNBREQ,Number of DMA requests to generate" bitfld.long 0x1C 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3" bitfld.long 0x1C 16. "GE,DMA request generator channel" "0,1" bitfld.long 0x1C 8. "OIE,Interrupt enable at trigger event" "0,1" hexmask.long.byte 0x1C 0.--4. 1. "SIG_ID,DMA request trigger input" rgroup.long 0x140++0x3 line.long 0x0 "DMAMUX2_RGSR,DMAMux - DMA request generator status" hexmask.long.byte 0x0 0.--7. 1. "OF,Trigger event overrun flag The flag is" wgroup.long 0x144++0x3 line.long 0x0 "DMAMUX2_RGCFR,DMAMux - DMA request generator clear flag" hexmask.long.byte 0x0 0.--7. 1. "COF,Clear trigger event overrun flag Upon" rgroup.long 0x80++0x3 line.long 0x0 "DMAMUX2_CSR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "SOF,Synchronization overrun event" wgroup.long 0x84++0x3 line.long 0x0 "DMAMUX2_CFR,DMAMUX request line multiplexer interrupt" hexmask.long.word 0x0 0.--15. 1. "CSOF,Clear synchronization overrun event" tree.end endif tree.end sif (cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "DSIHOST (DSI Host)" base ad:0x50000000 rgroup.long 0x0++0x3 line.long 0x0 "DSI_VR,DSI Host version register" hexmask.long 0x0 0.--31. 1. "VERSION,VERSION" group.long 0x4++0x17 line.long 0x0 "DSI_CR,DSI Host control register" bitfld.long 0x0 0. "EN,EN" "0,1" line.long 0x4 "DSI_CCR,DSI Host clock control register" hexmask.long.byte 0x4 8.--15. 1. "TOCKDIV,TOCKDIV" hexmask.long.byte 0x4 0.--7. 1. "TXECKDIV,TXECKDIV" line.long 0x8 "DSI_LVCIDR,DSI Host LTDC VCID register" bitfld.long 0x8 0.--1. "VCID,VCID" "0,1,2,3" line.long 0xC "DSI_LCOLCR,DSI Host LTDC color coding register" bitfld.long 0xC 8. "LPE,LPE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "COLC,COLC" line.long 0x10 "DSI_LPCR,DSI Host LTDC polarity configuration register" bitfld.long 0x10 2. "HSP,HSP" "0,1" bitfld.long 0x10 1. "VSP,VSP" "0,1" bitfld.long 0x10 0. "DEP,DEP" "0,1" line.long 0x14 "DSI_LPMCR,DSI Host low-power mode configuration register" hexmask.long.byte 0x14 16.--23. 1. "LPSIZE,LPSIZE" hexmask.long.byte 0x14 0.--7. 1. "VLPSIZE,VLPSIZE" group.long 0x2C++0x3 line.long 0x0 "DSI_PCR,DSI Host protocol configuration register" bitfld.long 0x0 4. "CRCRXE,CRCRXE" "0,1" bitfld.long 0x0 3. "ECCRXE,ECCRXE" "0,1" bitfld.long 0x0 2. "BTAE,BTAE" "0,1" bitfld.long 0x0 1. "ETRXE,ETRXE" "0,1" bitfld.long 0x0 0. "ETTXE,ETTXE" "0,1" rgroup.long 0x30++0x3 line.long 0x0 "DSI_GVCIDR,DSI Host generic VCID register" bitfld.long 0x0 0.--1. "VCID,VCID" "0,1,2,3" group.long 0x34++0x3F line.long 0x0 "DSI_MCR,DSI Host mode configuration register" bitfld.long 0x0 0. "CMDM,CMDM" "0,1" line.long 0x4 "DSI_VMCR,DSI Host video mode configuration register" bitfld.long 0x4 24. "PGO,PGO" "0,1" bitfld.long 0x4 20. "PGM,PGM" "0,1" bitfld.long 0x4 16. "PGE,PGE" "0,1" bitfld.long 0x4 15. "LPCE,LPCE" "0,1" bitfld.long 0x4 14. "FBTAAE,FBTAAE" "0,1" bitfld.long 0x4 13. "LPHFPE,LPHFPE" "0,1" bitfld.long 0x4 12. "LPHBPE,LPHBPE" "0,1" newline bitfld.long 0x4 11. "LPVAE,LPVAE" "0,1" bitfld.long 0x4 10. "LPVFPE,LPVFPE" "0,1" bitfld.long 0x4 9. "LPVBPE,LPVBPE" "0,1" bitfld.long 0x4 8. "LPVSAE,LPVSAE" "0,1" bitfld.long 0x4 0.--1. "VMT,VMT" "0,1,2,3" line.long 0x8 "DSI_VPCR,DSI Host video packet configuration register" hexmask.long.word 0x8 0.--13. 1. "VPSIZE,VPSIZE" line.long 0xC "DSI_VCCR,DSI Host video chunks configuration register" hexmask.long.word 0xC 0.--12. 1. "NUMC,NUMC" line.long 0x10 "DSI_VNPCR,DSI Host video null packet configuration register" hexmask.long.word 0x10 0.--12. 1. "NPSIZE,NPSIZE" line.long 0x14 "DSI_VHSACR,DSI Host video HSA configuration register" hexmask.long.word 0x14 0.--11. 1. "HSA,HSA" line.long 0x18 "DSI_VHBPCR,DSI Host video HBP configuration register" hexmask.long.word 0x18 0.--11. 1. "HBP,HBP" line.long 0x1C "DSI_VLCR,DSI Host video line configuration register" hexmask.long.word 0x1C 0.--14. 1. "HLINE,HLINE" line.long 0x20 "DSI_VVSACR,DSI Host video VSA configuration register" hexmask.long.word 0x20 0.--9. 1. "VSA,VSA" line.long 0x24 "DSI_VVBPCR,DSI Host video VBP configuration register" hexmask.long.word 0x24 0.--9. 1. "VBP,VBP" line.long 0x28 "DSI_VVFPCR,DSI Host video VFP configuration register" hexmask.long.word 0x28 0.--9. 1. "VFP,VFP" line.long 0x2C "DSI_VVACR,DSI Host video VA configuration register" hexmask.long.word 0x2C 0.--13. 1. "VA,VA" line.long 0x30 "DSI_LCCR,DSI Host LTDC command configuration register" hexmask.long.word 0x30 0.--15. 1. "CMDSIZE,CMDSIZE" line.long 0x34 "DSI_CMCR,DSI Host command mode configuration register" bitfld.long 0x34 24. "MRDPS,MRDPS" "0,1" bitfld.long 0x34 19. "DLWTX,DLWTX" "0,1" bitfld.long 0x34 18. "DSR0TX,DSR0TX" "0,1" bitfld.long 0x34 17. "DSW1TX,DSW1TX" "0,1" bitfld.long 0x34 16. "DSW0TX,DSW0TX" "0,1" bitfld.long 0x34 14. "GLWTX,GLWTX" "0,1" bitfld.long 0x34 13. "GSR2TX,GSR2TX" "0,1" newline bitfld.long 0x34 12. "GSR1TX,GSR1TX" "0,1" bitfld.long 0x34 11. "GSR0TX,GSR0TX" "0,1" bitfld.long 0x34 10. "GSW2TX,GSW2TX" "0,1" bitfld.long 0x34 9. "GSW1TX,GSW1TX" "0,1" bitfld.long 0x34 8. "GSW0TX,GSW0TX" "0,1" bitfld.long 0x34 1. "ARE,ARE" "0,1" bitfld.long 0x34 0. "TEARE,TEARE" "0,1" line.long 0x38 "DSI_GHCR,DSI Host generic header configuration register" hexmask.long.byte 0x38 16.--23. 1. "WCMSB,WCMSB" hexmask.long.byte 0x38 8.--15. 1. "WCLSB,WCLSB" bitfld.long 0x38 6.--7. "VCID,VCID" "0,1,2,3" hexmask.long.byte 0x38 0.--5. 1. "DT,DT" line.long 0x3C "DSI_GPDR,DSI Host generic payload data register" hexmask.long.byte 0x3C 24.--31. 1. "DATA4,DATA4" hexmask.long.byte 0x3C 16.--23. 1. "DATA3,DATA3" hexmask.long.byte 0x3C 8.--15. 1. "DATA2,DATA2" hexmask.long.byte 0x3C 0.--7. 1. "DATA1,DATA1" rgroup.long 0x74++0x3 line.long 0x0 "DSI_GPSR,DSI Host generic packet status register" bitfld.long 0x0 6. "RCB,RCB" "0,1" bitfld.long 0x0 5. "PRDFF,PRDFF" "0,1" bitfld.long 0x0 4. "PRDFE,PRDFE" "0,1" bitfld.long 0x0 3. "PWRFF,PWRFF" "0,1" bitfld.long 0x0 2. "PWRFE,PWRFE" "0,1" bitfld.long 0x0 1. "CMDFF,CMDFF" "0,1" bitfld.long 0x0 0. "CMDFE,CMDFE" "0,1" group.long 0x78++0x17 line.long 0x0 "DSI_TCCR0,DSI Host timeout counter configuration register 0" hexmask.long.word 0x0 16.--31. 1. "HSTX_TOCNT,HSTX_TOCNT" hexmask.long.word 0x0 0.--15. 1. "LPRX_TOCNT,LPRX_TOCNT" line.long 0x4 "DSI_TCCR1,DSI Host timeout counter configuration register 1" hexmask.long.word 0x4 0.--15. 1. "HSRD_TOCNT,HSRD_TOCNT" line.long 0x8 "DSI_TCCR2,DSI Host timeout counter configuration register 2" hexmask.long.word 0x8 0.--15. 1. "LPRD_TOCNT,LPRD_TOCNT" line.long 0xC "DSI_TCCR3,DSI Host timeout counter configuration register 3" bitfld.long 0xC 24. "PM,PM" "0,1" hexmask.long.word 0xC 0.--15. 1. "HSWR_TOCNT,HSWR_TOCNT" line.long 0x10 "DSI_TCCR4,DSI Host timeout counter configuration register 4" hexmask.long.word 0x10 0.--15. 1. "LPWR_TOCNT,LPWR_TOCNT" line.long 0x14 "DSI_TCCR5,DSI Host timeout counter configuration register 5" hexmask.long.word 0x14 0.--15. 1. "BTA_TOCNT,BTA_TOCNT" group.long 0x94++0x1B line.long 0x0 "DSI_CLCR,DSI Host clock lane configuration register" bitfld.long 0x0 1. "ACR,ACR" "0,1" bitfld.long 0x0 0. "DPCC,DPCC" "0,1" line.long 0x4 "DSI_CLTCR,DSI Host clock lane timer configuration register" hexmask.long.word 0x4 16.--25. 1. "HS2LP_TIME,HS2LP_TIME" hexmask.long.word 0x4 0.--9. 1. "LP2HS_TIME,LP2HS_TIME" line.long 0x8 "DSI_DLTCR,DSI Host data lane timer configuration register" hexmask.long.byte 0x8 24.--31. 1. "HS2LP_TIME,HS2LP_TIME" hexmask.long.byte 0x8 16.--23. 1. "LP2HS_TIME,LP2HS_TIME" hexmask.long.word 0x8 0.--14. 1. "MRD_TIME,Maximum read time" line.long 0xC "DSI_PCTLR,DSI Host PHY control register" bitfld.long 0xC 2. "CKE,CKE" "0,1" bitfld.long 0xC 1. "DEN,DEN" "0,1" line.long 0x10 "DSI_PCONFR,DSI Host PHY configuration register" hexmask.long.byte 0x10 8.--15. 1. "SW_TIME,SW_TIME" bitfld.long 0x10 0.--1. "NL,NL" "0,1,2,3" line.long 0x14 "DSI_PUCR,DSI Host PHY ULPS control register" bitfld.long 0x14 3. "UEDL,UEDL" "0,1" bitfld.long 0x14 2. "URDL,URDL" "0,1" bitfld.long 0x14 1. "UECL,UECL" "0,1" bitfld.long 0x14 0. "URCL,URCL" "0,1" line.long 0x18 "DSI_PTTCR,DSI Host PHY TX triggers configuration register" hexmask.long.byte 0x18 0.--3. 1. "TX_TRIG,TX_TRIG" rgroup.long 0xB0++0x3 line.long 0x0 "DSI_PSR,DSI Host PHY status register" bitfld.long 0x0 8. "UAN1,UAN1" "0,1" bitfld.long 0x0 7. "PSS1,PSS1" "0,1" bitfld.long 0x0 6. "RUE0,RUE0" "0,1" bitfld.long 0x0 5. "UAN0,UAN0" "0,1" bitfld.long 0x0 4. "PSS0,PSS0" "0,1" bitfld.long 0x0 3. "UANC,UANC" "0,1" bitfld.long 0x0 2. "PSSC,PSSC" "0,1" newline bitfld.long 0x0 1. "PD,PD" "0,1" rgroup.long 0xBC++0x7 line.long 0x0 "DSI_ISR0,DSI Host interrupt and status register 0" bitfld.long 0x0 20. "PE4,PE4" "0,1" bitfld.long 0x0 19. "PE3,PE3" "0,1" bitfld.long 0x0 18. "PE2,PE2" "0,1" bitfld.long 0x0 17. "PE1,PE1" "0,1" bitfld.long 0x0 16. "PE0,PE0" "0,1" bitfld.long 0x0 15. "AE15,AE15" "0,1" bitfld.long 0x0 14. "AE14,AE14" "0,1" newline bitfld.long 0x0 13. "AE13,AE13" "0,1" bitfld.long 0x0 12. "AE12,AE12" "0,1" bitfld.long 0x0 11. "AE11,AE11" "0,1" bitfld.long 0x0 10. "AE10,AE10" "0,1" bitfld.long 0x0 9. "AE9,AE9" "0,1" bitfld.long 0x0 8. "AE8,AE8" "0,1" bitfld.long 0x0 7. "AE7,AE7" "0,1" newline bitfld.long 0x0 6. "AE6,AE6" "0,1" bitfld.long 0x0 5. "AE5,AE5" "0,1" bitfld.long 0x0 4. "AE4,AE4" "0,1" bitfld.long 0x0 3. "AE3,AE3" "0,1" bitfld.long 0x0 2. "AE2,AE2" "0,1" bitfld.long 0x0 1. "AE1,AE1" "0,1" bitfld.long 0x0 0. "AE0,AE0" "0,1" line.long 0x4 "DSI_ISR1,DSI Host interrupt and status register 1" bitfld.long 0x4 12. "GPRXE,GPRXE" "0,1" bitfld.long 0x4 11. "GPRDE,GPRDE" "0,1" bitfld.long 0x4 10. "GPTXE,GPTXE" "0,1" bitfld.long 0x4 9. "GPWRE,GPWRE" "0,1" bitfld.long 0x4 8. "GCWRE,GCWRE" "0,1" bitfld.long 0x4 7. "LPWRE,LPWRE" "0,1" bitfld.long 0x4 6. "EOTPE,EOTPE" "0,1" newline bitfld.long 0x4 5. "PSE,PSE" "0,1" bitfld.long 0x4 4. "CRCE,CRCE" "0,1" bitfld.long 0x4 3. "ECCME,ECCME" "0,1" bitfld.long 0x4 2. "ECCSE,ECCSE" "0,1" bitfld.long 0x4 1. "TOLPRX,TOLPRX" "0,1" bitfld.long 0x4 0. "TOHSTX,TOHSTX" "0,1" group.long 0xC4++0x7 line.long 0x0 "DSI_IER0,DSI Host interrupt enable register 0" bitfld.long 0x0 20. "PE4IE,PE4IE" "0,1" bitfld.long 0x0 19. "PE3IE,PE3IE" "0,1" bitfld.long 0x0 18. "PE2IE,PE2IE" "0,1" bitfld.long 0x0 17. "PE1IE,PE1IE" "0,1" bitfld.long 0x0 16. "PE0IE,PE0IE" "0,1" bitfld.long 0x0 15. "AE15IE,AE15IE" "0,1" bitfld.long 0x0 14. "AE14IE,AE14IE" "0,1" newline bitfld.long 0x0 13. "AE13IE,AE13IE" "0,1" bitfld.long 0x0 12. "AE12IE,AE12IE" "0,1" bitfld.long 0x0 11. "AE11IE,AE11IE" "0,1" bitfld.long 0x0 10. "AE10IE,AE10IE" "0,1" bitfld.long 0x0 9. "AE9IE,AE9IE" "0,1" bitfld.long 0x0 8. "AE8IE,AE8IE" "0,1" bitfld.long 0x0 7. "AE7IE,AE7IE" "0,1" newline bitfld.long 0x0 6. "AE6IE,AE6IE" "0,1" bitfld.long 0x0 5. "AE5IE,AE5IE" "0,1" bitfld.long 0x0 4. "AE4IE,AE4IE" "0,1" bitfld.long 0x0 3. "AE3IE,AE3IE" "0,1" bitfld.long 0x0 2. "AE2IE,AE2IE" "0,1" bitfld.long 0x0 1. "AE1IE,AE1IE" "0,1" bitfld.long 0x0 0. "AE0IE,AE0IE" "0,1" line.long 0x4 "DSI_IER1,DSI Host interrupt enable register 1" bitfld.long 0x4 12. "GPRXEIE,GPRXEIE" "0,1" bitfld.long 0x4 11. "GPRDEIE,GPRDEIE" "0,1" bitfld.long 0x4 10. "GPTXEIE,GPTXEIE" "0,1" bitfld.long 0x4 9. "GPWREIE,GPWREIE" "0,1" bitfld.long 0x4 8. "GCWREIE,GCWREIE" "0,1" bitfld.long 0x4 7. "LPWREIE,LPWREIE" "0,1" bitfld.long 0x4 6. "EOTPEIE,EOTPEIE" "0,1" newline bitfld.long 0x4 5. "PSEIE,PSEIE" "0,1" bitfld.long 0x4 4. "CRCEIE,CRCEIE" "0,1" bitfld.long 0x4 3. "ECCMEIE,ECCMEIE" "0,1" bitfld.long 0x4 2. "ECCSEIE,ECCSEIE" "0,1" bitfld.long 0x4 1. "TOLPRXIE,TOLPRXIE" "0,1" bitfld.long 0x4 0. "TOHSTXIE,TOHSTXIE" "0,1" wgroup.long 0xD8++0x7 line.long 0x0 "DSI_FIR0,DSI Host force interrupt register 0" bitfld.long 0x0 20. "FPE4,FPE4" "0,1" bitfld.long 0x0 19. "FPE3,FPE3" "0,1" bitfld.long 0x0 18. "FPE2,FPE2" "0,1" bitfld.long 0x0 17. "FPE1,FPE1" "0,1" bitfld.long 0x0 16. "FPE0,FPE0" "0,1" bitfld.long 0x0 15. "FAE15,FAE15" "0,1" bitfld.long 0x0 14. "FAE14,FAE14" "0,1" newline bitfld.long 0x0 13. "FAE13,FAE13" "0,1" bitfld.long 0x0 12. "FAE12,FAE12" "0,1" bitfld.long 0x0 11. "FAE11,FAE11" "0,1" bitfld.long 0x0 10. "FAE10,FAE10" "0,1" bitfld.long 0x0 9. "FAE9,FAE9" "0,1" bitfld.long 0x0 8. "FAE8,FAE8" "0,1" bitfld.long 0x0 7. "FAE7,FAE7" "0,1" newline bitfld.long 0x0 6. "FAE6,FAE6" "0,1" bitfld.long 0x0 5. "FAE5,FAE5" "0,1" bitfld.long 0x0 4. "FAE4,FAE4" "0,1" bitfld.long 0x0 3. "FAE3,FAE3" "0,1" bitfld.long 0x0 2. "FAE2,FAE2" "0,1" bitfld.long 0x0 1. "FAE1,FAE1" "0,1" bitfld.long 0x0 0. "FAE0,FAE0" "0,1" line.long 0x4 "DSI_FIR1,DSI Host force interrupt register 1" bitfld.long 0x4 12. "FGPRXE,FGPRXE" "0,1" bitfld.long 0x4 11. "FGPRDE,FGPRDE" "0,1" bitfld.long 0x4 10. "FGPTXE,FGPTXE" "0,1" bitfld.long 0x4 9. "FGPWRE,FGPWRE" "0,1" bitfld.long 0x4 8. "FGCWRE,FGCWRE" "0,1" bitfld.long 0x4 7. "FLPWRE,FLPWRE" "0,1" bitfld.long 0x4 6. "FEOTPE,FEOTPE" "0,1" newline bitfld.long 0x4 5. "FPSE,FPSE" "0,1" bitfld.long 0x4 4. "FCRCE,FCRCE" "0,1" bitfld.long 0x4 3. "FECCME,FECCME" "0,1" bitfld.long 0x4 2. "FECCSE,FECCSE" "0,1" bitfld.long 0x4 1. "FTOLPRX,FTOLPRX" "0,1" bitfld.long 0x4 0. "FTOHSTX,FTOHSTX" "0,1" group.long 0x100++0x3 line.long 0x0 "DSI_VSCR,DSI Host video shadow control register" bitfld.long 0x0 8. "UR,UR" "0,1" bitfld.long 0x0 0. "EN,EN" "0,1" group.long 0x10C++0x3 line.long 0x0 "DSI_LCVCIDR,DSI Host LTDC current VCID register" bitfld.long 0x0 0.--1. "VCID,VCID" "0,1,2,3" rgroup.long 0x110++0x3 line.long 0x0 "DSI_LCCCR,DSI Host LTDC current color coding register" bitfld.long 0x0 8. "LPE,LPE" "0,1" hexmask.long.byte 0x0 0.--3. 1. "COLC,COLC" rgroup.long 0x118++0x3 line.long 0x0 "DSI_LPMCCR,DSI Host low-power mode current configuration register" hexmask.long.byte 0x0 16.--23. 1. "LPSIZE,LPSIZE" hexmask.long.byte 0x0 0.--7. 1. "VLPSIZE,VLPSIZE" rgroup.long 0x138++0x2B line.long 0x0 "DSI_VMCCR,DSI Host video mode current configuration register" bitfld.long 0x0 9. "LPCE,LPCE" "0,1" bitfld.long 0x0 8. "FBTAAE,FBTAAE" "0,1" bitfld.long 0x0 7. "LPHFE,LPHFE" "0,1" bitfld.long 0x0 6. "LPHBPE,LPHBPE" "0,1" bitfld.long 0x0 5. "LPVAE,LPVAE" "0,1" bitfld.long 0x0 4. "LPVFPE,LPVFPE" "0,1" bitfld.long 0x0 3. "LPVBPE,LPVBPE" "0,1" newline bitfld.long 0x0 2. "LPVSAE,LPVSAE" "0,1" bitfld.long 0x0 0.--1. "VMT,VMT" "0,1,2,3" line.long 0x4 "DSI_VPCCR,DSI Host video packet current configuration register" hexmask.long.word 0x4 0.--13. 1. "VPSIZE,VPSIZE" line.long 0x8 "DSI_VCCCR,DSI Host video chunks current configuration register" hexmask.long.word 0x8 0.--12. 1. "NUMC,NUMC" line.long 0xC "DSI_VNPCCR,DSI Host video null packet current configuration register" hexmask.long.word 0xC 0.--12. 1. "NPSIZE,NPSIZE" line.long 0x10 "DSI_VHSACCR,DSI Host video HSA current configuration register" hexmask.long.word 0x10 0.--11. 1. "HSA,HSA" line.long 0x14 "DSI_VHBPCCR,DSI Host video HBP current configuration register" hexmask.long.word 0x14 0.--11. 1. "HBP,HBP" line.long 0x18 "DSI_VLCCR,DSI Host video line current configuration register" hexmask.long.word 0x18 0.--14. 1. "HLINE,HLINE" line.long 0x1C "DSI_VVSACCR,DSI Host video VSA current configuration register" hexmask.long.word 0x1C 0.--9. 1. "VSA,VSA" line.long 0x20 "DSI_VVBPCCR,DSI Host video VBP current configuration register" hexmask.long.word 0x20 0.--9. 1. "VBP,VBP" line.long 0x24 "DSI_VVFPCCR,DSI Host video VFP current configuration register" hexmask.long.word 0x24 0.--9. 1. "VFP,VFP" line.long 0x28 "DSI_VVACCR,DSI Host video VA current configuration register" hexmask.long.word 0x28 0.--13. 1. "VA,VA" group.long 0x400++0xB line.long 0x0 "DSI_WCFGR,DSI wrapper configuration register" bitfld.long 0x0 7. "VSPOL,VSPOL" "0,1" bitfld.long 0x0 6. "AR,AR" "0,1" bitfld.long 0x0 5. "TEPOL,TEPOL" "0,1" bitfld.long 0x0 4. "TESRC,TESRC" "0,1" bitfld.long 0x0 1.--3. "COLMUX,COLMUX" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "DSIM,DSIM" "0,1" line.long 0x4 "DSI_WCR,DSI wrapper control register" bitfld.long 0x4 3. "DSIEN,DSIEN" "0,1" bitfld.long 0x4 2. "LTDCEN,LTDCEN" "0,1" bitfld.long 0x4 1. "SHTDN,SHTDN" "0,1" bitfld.long 0x4 0. "COLM,COLM" "0,1" line.long 0x8 "DSI_WIER,DSI wrapper interrupt enable register" bitfld.long 0x8 13. "RRIE,RRIE" "0,1" bitfld.long 0x8 10. "PLLUIE,PLLUIE" "0,1" bitfld.long 0x8 9. "PLLLIE,PLLLIE" "0,1" bitfld.long 0x8 1. "ERIE,ERIE" "0,1" bitfld.long 0x8 0. "TEIE,TEIE" "0,1" rgroup.long 0x40C++0x3 line.long 0x0 "DSI_WISR,DSI wrapper interrupt and status register" bitfld.long 0x0 13. "RRIF,RRIF" "0,1" bitfld.long 0x0 12. "RRS,RRS" "0,1" bitfld.long 0x0 10. "PLLUIF,PLLUIF" "0,1" bitfld.long 0x0 9. "PLLLIF,PLLLIF" "0,1" bitfld.long 0x0 8. "PLLLS,PLLLS" "0,1" bitfld.long 0x0 2. "BUSY,BUSY" "0,1" bitfld.long 0x0 1. "ERIF,ERIF" "0,1" newline bitfld.long 0x0 0. "TEIF,TEIF" "0,1" wgroup.long 0x410++0x3 line.long 0x0 "DSI_WIFCR,DSI wrapper interrupt flag clear register" bitfld.long 0x0 13. "CRRIF,CRRIF" "0,1" bitfld.long 0x0 10. "CPLLUIF,CPLLUIF" "0,1" bitfld.long 0x0 9. "CPLLLIF,CPLLLIF" "0,1" bitfld.long 0x0 1. "CERIF,CERIF" "0,1" bitfld.long 0x0 0. "CTEIF,CTEIF" "0,1" group.long 0x418++0x13 line.long 0x0 "DSI_WPCR0,DSI wrapper PHY configuration register 0" bitfld.long 0x0 27. "TCLKPOSTEN,Custom time for tCLK-POST enable" "0,1" bitfld.long 0x0 26. "TLPXCEN,Custom time for tLPX for clock lane enable" "0,1" bitfld.long 0x0 25. "THSEXITEN,Custom time for tHS-EXIT enable" "0,1" bitfld.long 0x0 24. "TLPXDEN,Custom time for tLPX for data lanes enable" "0,1" bitfld.long 0x0 23. "THSZEROEN,Custom time for tHS-ZERO enable" "0,1" bitfld.long 0x0 22. "THSTRAILEN,Custom time for tHS-TRAIL enable" "0,1" bitfld.long 0x0 21. "THSPREPEN,Custom time for tHS-PREPARE enable" "0,1" newline bitfld.long 0x0 20. "TCLKZEROEN,Custom time for tCLK-ZERO enable" "0,1" bitfld.long 0x0 19. "TCLKPREPEN,Custom time for tCLK-PREPARE enable" "0,1" bitfld.long 0x0 18. "PDEN,Pull-down enable" "0,1" bitfld.long 0x0 16. "TDDL,TDDL" "0,1" bitfld.long 0x0 14. "CDOFFDL,CDOFFDL" "0,1" bitfld.long 0x0 13. "FTXSMDL,FTXSMDL" "0,1" bitfld.long 0x0 12. "FTXSMCL,FTXSMCL" "0,1" newline bitfld.long 0x0 11. "HSIDL1,HSIDL1" "0,1" bitfld.long 0x0 10. "HSIDL0,HSIDL0" "0,1" bitfld.long 0x0 9. "HSICL,HSICL" "0,1" bitfld.long 0x0 8. "SWDL1,SWDL1" "0,1" bitfld.long 0x0 7. "SWDL0,SWDL0" "0,1" bitfld.long 0x0 6. "SWCL,SWCL" "0,1" hexmask.long.byte 0x0 0.--5. 1. "UIX4,UIX4" line.long 0x4 "DSI_WPCR1,This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0)." bitfld.long 0x4 25.--26. "LPRXFT,Low-power RX low-pass filtering tuning" "0,1,2,3" bitfld.long 0x4 22. "FLPRXLPM,Forces LP receiver in low-power mode" "0,1" bitfld.long 0x4 18.--19. "HSTXSRCDL,High-speed transmission slew-rate control on data lanes" "0,1,2,3" bitfld.long 0x4 16.--17. "HSTXSRCCL,High-speed transmission slew-rate control on clock lane" "0,1,2,3" bitfld.long 0x4 12. "SDDC,SDD control" "0,1" bitfld.long 0x4 8.--9. "LPSRCDL,Low-power transmission slew-rate compensation on data lanes" "0,1,2,3" bitfld.long 0x4 6.--7. "LPSRCCL,Low-power transmission slew-rate compensation on clock lane" "0,1,2,3" newline bitfld.long 0x4 2.--3. "HSTXDDL,High-speed transmission delay on data lanes" "0,1,2,3" bitfld.long 0x4 0.--1. "HSTXDCL,High-speed transmission delay on clock lane" "0,1,2,3" line.long 0x8 "DSI_WPCR2,DSI wrapper PHY configuration register 2" hexmask.long.byte 0x8 24.--31. 1. "THSTRAIL,THSTRAIL" hexmask.long.byte 0x8 16.--23. 1. "THSPREP,THSPREP" hexmask.long.byte 0x8 8.--15. 1. "TCLKZERO,TCLKZERO" hexmask.long.byte 0x8 0.--7. 1. "TCLKPREP,TCLKPREP" line.long 0xC "DSI_WPCR3,DSI wrapper PHY configuration register 3" hexmask.long.byte 0xC 24.--31. 1. "TLPXC,TLPXC" hexmask.long.byte 0xC 16.--23. 1. "THSEXIT,THSEXIT" hexmask.long.byte 0xC 8.--15. 1. "TLPXD,TLPXD" hexmask.long.byte 0xC 0.--7. 1. "THSZERO,THSZERO" line.long 0x10 "DSI_WPCR4,DSI wrapper PHY configuration register 4" hexmask.long.byte 0x10 0.--7. 1. "TCLKPOST,TCLKPOST" group.long 0x430++0x3 line.long 0x0 "DSI_WRPCR,DSI wrapper regulator and PLL control register" bitfld.long 0x0 24. "REGEN,REGEN" "0,1" bitfld.long 0x0 16.--17. "ODF,ODF" "0,1,2,3" hexmask.long.byte 0x0 11.--14. 1. "IDF,IDF" hexmask.long.byte 0x0 2.--8. 1. "NDIV,NDIV" bitfld.long 0x0 0. "PLLEN,PLLEN" "0,1" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "ETHERNET" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "Ethernet_MAC" base ad:0x40028000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" newline bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" newline bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" newline bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" newline bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" newline bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" newline bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" newline bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" endif group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" endif sif (cpuis("STM32H742*")) hexmask.long 0x4 0.--31. 1. "MACRWKPFR,MACRWKPFR" endif group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" endif bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x0 14.--15. "ADDR64,ADDR64" "0,1,2,3" newline endif bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" newline hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H742*")) tree "Ethernet_DMA" base ad:0x40029000 group.long 0x0++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x8++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x14C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x15C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" tree.end endif sif (cpuis("STM32H742*")) tree "Ethernet_MTL" base ad:0x40028C00 group.long 0x0++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0x100++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0x104++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0x12C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0x134++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" tree.end endif sif (cpuis("STM32H743*")) tree "Ethernet_DMA" base ad:0x40029000 group.long 0x0++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x8++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x14C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x15C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" tree.end endif sif (cpuis("STM32H743*")) tree "Ethernet_MTL" base ad:0x40028C00 group.long 0x0++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0x100++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0x104++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0x12C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0x134++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" tree.end endif sif (cpuis("STM32H743*")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "MACRWKPFR,MACRWKPFR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" bitfld.long 0x0 17. "PLS,PLS" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x7 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" line.long 0x4 "MACDR,Debug register" bitfld.long 0x4 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x4 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x4 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x4 0. "RPESTS,RPESTS" "0,1" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 14.--15. "ADDR64,ADDR64" "0,1,2,3" newline bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" newline hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x7 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA3LR,Address 3 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H750*")) tree "ETH" base ad:0x40028000 group.long 0x0++0x17 line.long 0x0 "ETH_MACCR,Operating mode configuration register" bitfld.long 0x0 31. "ARPEN,ARP Offload Enable" "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control" "?,?,2: the MAC inserts the content of the MAC Address 0..,3: the MAC replaces the content of the MAC Address..,?,?,6: the MAC inserts the content of the MAC Address 1..,7: the MAC replaces the content of the MAC Address.." newline bitfld.long 0x0 27. "IPC,Checksum Offload" "0,1" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,?,?,?,?,7: 40 bit times" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable" "0,1" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets" "0,1" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets" "0,1" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping" "0,1" newline bitfld.long 0x0 19. "WD,Watchdog Disable" "0,1" newline bitfld.long 0x0 17. "JD,Jabber Disable" "0,1" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable" "0,1" newline bitfld.long 0x0 14. "FES,MAC Speed" "0: 10 Mbps,1: 100 Mbps" newline bitfld.long 0x0 13. "DM,Duplex Mode" "0,1" newline bitfld.long 0x0 12. "LM,Loopback Mode" "0,1" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1" newline bitfld.long 0x0 10. "DO,Disable Receive Own" "0,1" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission" "0,1" newline bitfld.long 0x0 8. "DR,Disable Retry" "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit" "0: k= min (n 10),1: k = min (n 8),2: k = min (n 4),3: k = min (n 1)" newline bitfld.long 0x0 4. "DC,Deferral Check" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets" "0: 7 bytes of preamble,1: 5 bytes of preamble,2: 3 bytes of preamble,3: Reserved must not be used" newline bitfld.long 0x0 1. "TE,Transmitter Enable" "0,1" newline bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "ETH_MACECR,Extended operating mode configuration register" hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap" newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable" "0,1" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect" "0,1" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable" "0,1" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit" line.long 0x8 "ETH_MACPFR,Packet filtering control register" bitfld.long 0x8 31. "RA,Receive All" "0,1" newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets" "0,1" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable" "0,1" newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter" "0,1" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable" "0,1" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering" "0,1" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets" "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,2: The MAC forwards all control packets to the..,3: The MAC forwards the control packets that pass.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets" "0,1" newline bitfld.long 0x8 4. "PM,Pass All Multicast" "0,1" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering" "0,1" newline bitfld.long 0x8 2. "HMC,Hash Multicast" "0,1" newline bitfld.long 0x8 1. "HUC,Hash Unicast" "0,1" newline bitfld.long 0x8 0. "PR,Promiscuous Mode" "0,1" line.long 0xC "ETH_MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout" line.long 0x10 "ETH_MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits" line.long 0x14 "ETH_MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits" group.long 0x50++0x3 line.long 0x0 "ETH_MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status" "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag" "0,1" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing" "0,1" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable" "0,1" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status" "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive" "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip" newline bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check" "0,1" newline bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match" "0,1" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN" "0,1" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable" "0,1" newline bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VLAN Tag Identifier for Receive Packets" group.long 0x58++0x3 line.long 0x0 "ETH_MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLAN Hash Table" group.long 0x60++0x3 line.long 0x0 "ETH_MACVIR,VLAN inclusion register" rbitfld.long 0x0 31. "BUSY,Busy" "0,1" newline bitfld.long 0x0 30. "RDWR,Read write control" "0,1" newline bitfld.long 0x0 24. "ADDR,Address" "0: VLAN tag for insertion in the Transmit packets..,1: VLAN tag for insertion in the Transmit packets.." newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion" "0,1" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion. The MAC removes the VLAN type..,2: VLAN tag insertion. The MAC inserts VLT in bytes..,3: VLAN tag replacement. The MAC replaces VLT in.." newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x60++0x7 line.long 0x0 "ETH_MACVIRALTERNATE,VLAN inclusion register" bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" line.long 0x4 "ETH_MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLAN Tag Input" "0,1" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN" "0: C-LAN,1: S-LAN" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control" "0,1" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets" "0: No VLAN tag deletion insertion or replacement,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets" group.long 0x70++0x3 line.long 0x0 "ETH_MACQTXFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time" newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause" "0,1" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold" "0: Pause Time minus 4 Slot Times (PT -4 slot times),1: Pause Time minus 28 Slot Times (PT -28 slot times),2: Pause Time minus 36 Slot Times (PT -36 slot times),3: Pause Time minus 144 Slot Times (PT -144 slot..,4: Pause Time minus 256 Slot Times (PT -256 slot..,5: Pause Time minus 512 Slot Times (PT -512 slot..,6: Reserved must not be used,7: Reserved must not be used" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate" "0,1" group.long 0x90++0x3 line.long 0x0 "ETH_MACRXFCR,Rx flow control register" bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect" "0,1" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable" "0,1" group.long 0xB0++0xB line.long 0x0 "ETH_MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt" "0,1" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt" "0,1" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status" "0,1" newline rbitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status" "0,1" newline rbitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status" "0,1" newline rbitfld.long 0x0 8. "MMCIS,MMC Interrupt Status" "0,1" newline rbitfld.long 0x0 5. "LPIIS,LPI Interrupt Status" "0,1" newline rbitfld.long 0x0 4. "PMTIS,PMT Interrupt Status" "0,1" newline rbitfld.long 0x0 3. "PHYIS,PHY Interrupt" "0,1" line.long 0x4 "ETH_MACIER,Interrupt enable register" bitfld.long 0x4 14. "RXSTSIE,Receive Status Interrupt Enable" "0,1" newline bitfld.long 0x4 13. "TXSTSIE,Transmit Status Interrupt Enable" "0,1" newline bitfld.long 0x4 12. "TSIE,Timestamp Interrupt Enable" "0,1" newline bitfld.long 0x4 5. "LPIIE,LPI Interrupt Enable" "0,1" newline bitfld.long 0x4 4. "PMTIE,PMT Interrupt Enable" "0,1" newline bitfld.long 0x4 3. "PHYIE,PHY Interrupt Enable" "0,1" line.long 0x8 "ETH_MACRXTXSR,Rx Tx status register" bitfld.long 0x8 8. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x8 5. "EXCOL,Excessive Collisions" "0,1" newline bitfld.long 0x8 4. "LCOL,Late Collision" "0,1" newline bitfld.long 0x8 3. "EXDEF,Excessive Deferral" "0,1" newline bitfld.long 0x8 2. "LCARR,Loss of Carrier" "0,1" newline bitfld.long 0x8 1. "NCARR,No Carrier" "0,1" newline bitfld.long 0x8 0. "TJT,Transmit Jabber Timeout" "0,1" group.long 0xC0++0x7 line.long 0x0 "ETH_MACPCSR," bitfld.long 0x0 31. "RWKFILTRST,Remote wakeup Packet Filter Register Pointer Reset" "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote wakeup FIFO Pointer" newline bitfld.long 0x0 10. "RWKPFE,Remote wakeup Packet Forwarding Enable" "0,1" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote wakeup Packet Received" "0,1" newline bitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received" "0,1" newline bitfld.long 0x0 2. "RWKPKTEN,Remote wakeup Packet Enable" "0,1" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable" "0,1" newline bitfld.long 0x0 0. "PWRDWN,Power Down" "0,1" line.long 0x4 "ETH_MACRWKPFR," hexmask.long 0x4 0.--31. 1. "MACRWKPFR,Remote wakeup packet filter" group.long 0xD0++0xF line.long 0x0 "ETH_MACLCSR,LPI control and status register" bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable" "0,1" newline bitfld.long 0x0 20. "LPITE,LPI Timer Enable" "0,1" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate" "0,1" newline bitfld.long 0x0 17. "PLS,PHY Link Status" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPI Enable" "0,1" newline rbitfld.long 0x0 9. "RLPIST,Receive LPI State" "0,1" newline rbitfld.long 0x0 8. "TLPIST,Transmit LPI State" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry" "0,1" newline rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit" "0,1" newline rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry" "0,1" line.long 0x4 "ETH_MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer" newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer" line.long 0x8 "ETH_MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--19. 1. "LPIET,LPI Entry Timer" line.long 0xC "ETH_MAC1USTCR,One-microsecond-tick counter register" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1 us tick Counter" rgroup.long 0x110++0x7 line.long 0x0 "ETH_MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,ST-defined version" newline hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,IP version" line.long 0x4 "ETH_MACDR,Debug register" bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status" "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control..,3: Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC MII Transmit Protocol Engine Status" "0,1" newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status" "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC MII Receive Protocol Engine Status" "0,1" rgroup.long 0x11C++0xF line.long 0x0 "ETH_MACHWF0R,HW feature 0 register" bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected" "0: GMII or MII,1: RGMII,2: SGMII,3: TBI,4: RMII,5: RTBI,6: SMII,?" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable" "0,1" newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source" "0: Reserved must not be used,1: Internal,2: External,3: Both" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected" "0,1" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected" "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled" "0,1" newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled" "0,1" newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled" "0,1" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled" "0,1" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable" "0,1" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable" "0,1" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wakeup Packet Enable" "0,1" newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface" "0,1" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected" "0,1" newline bitfld.long 0x0 3. "PCSSEL,PCS Registers (TBI SGMII or RTBI PHY interface)" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support" "0,1" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support" "0,1" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support" "0,1" line.long 0x4 "ETH_MACHWF1R,HW feature 1 register" hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size" "0: No Hash table,1: 64,2: 128,3: 256" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable" "0,1" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable" "0,1" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable" "0,1" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable" "0,1" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable" "0,1" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable" "0,1" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable" "0,1" newline bitfld.long 0x4 14.--15. "ADDR64,Address width" "0: 32 bits,?,?,?" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable" "0,1" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable" "0,1" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable" "0,1" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size" line.long 0x8 "ETH_MACHWF2R,HW feature 2 register" bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs" "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,5: Reserved must not be used,6: Reserved must not be used,7: Reserved must not be used" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs" "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,5: Reserved must not be used,6: Reserved must not be used,7: Reserved must not be used" newline bitfld.long 0x8 22.--23. "TDCSZ,Tx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels" newline bitfld.long 0x8 16.--17. "RDCSZ,Rx DMA Descriptor Cache Size in terms of 16-byte descriptors" "0: Cache not configured,1: Four 16-byte descriptors,2: Eight 16-byte descriptors,3: Sixteen 16-byte descriptors" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues" line.long 0xC "ETH_MACHWF3R,HW feature 3 register" bitfld.long 0xC 5. "DVLAN,Double VLAN processing enable" "0,1" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx enable" "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,6: Reserved must not be used,7: Reserved must not be used" group.long 0x200++0x7 line.long 0x0 "ETH_MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,Preamble Suppression Enable" "0,1" newline bitfld.long 0x0 26. "BTB,Back to Back transactions" "0,1" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address" newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address" newline bitfld.long 0x0 12.--14. "NTC,Number of Training Clocks" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet" "0,1" newline bitfld.long 0x0 2.--3. "GOC,MII Operation Command" "0: Reserved must not be used,1: Write,2: Post Read Increment Address for Clause 45 PHY,3: Read" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable" "0,1" newline bitfld.long 0x0 0. "MB,MII Busy" "0,1" line.long 0x4 "ETH_MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,Register Address" newline hexmask.long.word 0x4 0.--15. 1. "MD,MII Data" group.long 0x210++0x3 line.long 0x0 "ETH_MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address" group.long 0x230++0x3 line.long 0x0 "ETH_MACCSRSWCR,CSR software control register" bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1" newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1" group.long 0x300++0x1F line.long 0x0 "ETH_MACA0HR,MAC Address 0 high register" rbitfld.long 0x0 31. "AE,Address Enable" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]" line.long 0x4 "ETH_MACA0LR,MAC Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x8 "ETH_MACA1HR,MAC Address 1 high register" bitfld.long 0x8 31. "AE,Address Enable" "0,1" newline bitfld.long 0x8 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0xC "ETH_MACA1LR,MAC Address 1 low register" hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x10 "ETH_MACA2HR,MAC Address 2 high register" bitfld.long 0x10 31. "AE,Address Enable" "0,1" newline bitfld.long 0x10 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x14 "ETH_MACA2LR,MAC Address 2 low register" hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" line.long 0x18 "ETH_MACA3HR,MAC Address 3 high register" bitfld.long 0x18 31. "AE,Address Enable" "0,1" newline bitfld.long 0x18 30. "SA,Source Address" "0: DA,1: SA" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control" newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32]" line.long 0x1C "ETH_MACA3LR,MAC Address 3 low register" hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address x [31:0] (x = 0 to 3)" group.long 0x700++0x13 line.long 0x0 "ETH_MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets" "0,1" newline bitfld.long 0x0 5. "CNTPRSTLVL,Full-Half Preset" "0,1" newline bitfld.long 0x0 4. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 3. "CNTFREEZ,MMC Counter Freeze" "0,1" newline bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1" newline bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1" newline bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1" line.long 0x4 "ETH_MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x4 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status" "0,1" newline bitfld.long 0x4 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x4 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x4 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status" "0,1" line.long 0x8 "ETH_MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x8 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status" "0,1" newline bitfld.long 0x8 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status" "0,1" newline bitfld.long 0x8 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x8 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1" newline bitfld.long 0x8 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1" line.long 0xC "ETH_MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" bitfld.long 0xC 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0xC 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0xC 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0xC 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0xC 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask" "0,1" line.long 0x10 "ETH_MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" bitfld.long 0x10 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask" "0,1" newline bitfld.long 0x10 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask" "0,1" newline bitfld.long 0x10 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x10 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask" "0,1" newline bitfld.long 0x10 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "ETH_TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets register" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets" line.long 0x4 "ETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets register" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets" rgroup.long 0x768++0x3 line.long 0x0 "ETH_TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,Tx Packet Count Good" rgroup.long 0x794++0x7 line.long 0x0 "ETH_RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,Rx CRC Error Packets" line.long 0x4 "ETH_RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets register" hexmask.long 0x4 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets" rgroup.long 0x7C4++0x3 line.long 0x0 "ETH_RX_UNICAST_PACKETS_GOOD,Rx unicast packets good register" hexmask.long 0x0 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good" rgroup.long 0x7EC++0xF line.long 0x0 "ETH_TX_LPI_USEC_CNTR,Tx LPI microsecond timer register" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter" line.long 0x4 "ETH_TX_LPI_TRAN_CNTR,Tx LPI transition counter register" hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter" line.long 0x8 "ETH_RX_LPI_USEC_CNTR,Rx LPI microsecond counter register" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter" line.long 0xC "ETH_RX_LPI_TRAN_CNTR,Rx LPI transition counter register" hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter" group.long 0x900++0x7 line.long 0x0 "ETH_MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA higher bits match" newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A0R," hexmask.long.word 0x4 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field" group.long 0x910++0xF line.long 0x0 "ETH_MACL3A00R,Layer3 Address 0 filter 0 register" hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A10R,Layer3 Address 1 filter 0 register" hexmask.long 0x4 0.--31. 1. "L3A10,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A20R,Layer3 Address 2 filter 0 register" hexmask.long 0x8 0.--31. 1. "L3A20,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A30R,Layer3 Address 3 filter 0 register" hexmask.long 0xC 0.--31. 1. "L3A30,Layer 3 Address 3 Field" group.long 0x930++0x7 line.long 0x0 "ETH_MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable" "0,1" newline bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable" "0,1" newline bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable" "0,1" newline bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA higher bits match" newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match" newline bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable" "0,1" newline bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable" "0,1" newline bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable" "0,1" newline bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable" "0,1" newline bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable" "0,1" line.long 0x4 "ETH_MACL4A1R," hexmask.long.word 0x4 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field" newline hexmask.long.word 0x4 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field" group.long 0x940++0xF line.long 0x0 "ETH_MACL3A01R,Layer3 address 0 filter 1 Register" hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field" line.long 0x4 "ETH_MACL3A11R,Layer3 address 1 filter 1 register" hexmask.long 0x4 0.--31. 1. "L3A11,Layer 3 Address 1 Field" line.long 0x8 "ETH_MACL3A21R,Layer3 address 2 filter 1 Register" hexmask.long 0x8 0.--31. 1. "L3A21,Layer 3 Address 2 Field" line.long 0xC "ETH_MACL3A31R,Layer3 address 3 filter 1 register" hexmask.long 0xC 0.--31. 1. "L3A31,Layer 3 Address 3 Field" group.long 0xB00++0x7 line.long 0x0 "ETH_MACTSCR,Timestamp control Register" bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable" "0,1" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode" "0,1" newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering" "0,1" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master" "0,1" newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages" "0,1" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP" "0,1" newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP" "0,1" newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets" "0,1" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format" "0,1" newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control" "0,1" newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets" "0,1" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register" "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp" "0,1" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp" "0,1" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update" "0,1" newline bitfld.long 0x0 0. "TSENA,Enable Timestamp" "0,1" line.long 0x4 "ETH_MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value" rgroup.long 0xB08++0x7 line.long 0x0 "ETH_MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second" line.long 0x4 "ETH_MACSTNR,System time nanoseconds register" hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub-seconds" group.long 0xB10++0xB line.long 0x0 "ETH_MACSTSUR,System time seconds update register" hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds" line.long 0x4 "ETH_MACSTNUR," bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time" "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub-seconds" line.long 0x8 "ETH_MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register" group.long 0xB20++0x3 line.long 0x0 "ETH_MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots" newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier" newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error" "0,1" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot" "0,1" newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached" "0,1" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow" "0,1" group.long 0xB30++0x3 line.long 0x0 "ETH_MACTXTSSNR,Tx timestamp status nanoseconds register" rbitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed" "0,1" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low" rgroup.long 0xB34++0x3 line.long 0x0 "ETH_MACTXTSSSR,Tx timestamp status seconds register" hexmask.long 0x0 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High" group.long 0xB40++0x3 line.long 0x0 "ETH_MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable" "0,1" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable" "0,1" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable" "0,1" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "ETH_MACATSNR,Auxiliary timestamp nanoseconds register" hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp" line.long 0x4 "ETH_MACATSSR,Auxiliary timestamp seconds register" hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp" group.long 0xB50++0xF line.long 0x0 "ETH_MACTSIACR,Timestamp Ingress asymmetric correction register" hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction" line.long 0x4 "ETH_MACTSEACR,Timestamp Egress asymmetric correction register" hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction" line.long 0x8 "ETH_MACTSICNR,Timestamp Ingress correction nanosecond register" hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction" line.long 0xC "ETH_MACTSECNR,Timestamp Egress correction nanosecond register" hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCR,ETH_MACPPSCR" bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPS Output Frequency Control" group.long 0xB70++0x3 line.long 0x0 "ETH_MACPPSCRALTERNATE,ETH_MACPPSCRALTERNATE" bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS Output" "0: Target Time registers are programmed only for..,1: Reserved must not be used,2: Target Time registers are programmed for..,3: Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCMD,Flexible PPS Output (eth_ptp_pps_out) Control" group.long 0xB80++0xF line.long 0x0 "ETH_MACPPSTTSR,PPS target time seconds register" hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register" line.long 0x4 "ETH_MACPPSTTNR,PPS target time nanoseconds register" bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy" "0,1" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register" line.long 0x8 "ETH_MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval" line.long 0xC "ETH_MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width" group.long 0xBC0++0x13 line.long 0x0 "ETH_MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number" newline bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation" "0,1" newline bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger" "0,1" newline bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger" "0,1" newline bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable" "0,1" newline bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable" "0,1" newline bitfld.long 0x0 0. "PTOEN,PTP Offload Enable" "0,1" line.long 0x4 "ETH_MACSPI0R,PTP Source Port Identity 0 Register" hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0" line.long 0x8 "ETH_MACSPI1R,PTP Source port identity 1 register" hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1" line.long 0xC "ETH_MACSPI2R,PTP Source port identity 2 register" hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2" line.long 0x10 "ETH_MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval" newline bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio" "0: DelayReq generated for every received SYNC,1: DelayReq generated every alternate reception of..,2: for every 4 SYNC messages,3: for every 8 SYNC messages,4: for every 16 SYNC messages,5: for every 32 SYNC messages,?,?" newline hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval" group.long 0xC00++0x3 line.long 0x0 "ETH_MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,Counters Reset" "0,1" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset" "0,1" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "ETH_MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x7 line.long 0x0 "ETH_MTLTXQOMR,Tx queue operating mode Register" bitfld.long 0x0 16.--18. "TQS,Transmit queue size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0: 32,1: 64,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512" newline rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0: Not enabled,?,2: Enabled,?" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" line.long 0x4 "ETH_MTLTXQUR,Tx queue underflow register" bitfld.long 0x4 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter" "0,1" newline hexmask.long.word 0x4 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" rgroup.long 0xD08++0x3 line.long 0x0 "ETH_MTLTXQDR,Tx queue debug Register" bitfld.long 0x0 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "PTXQ,Number of Packets in the Transmit Queue" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status" "0,1" newline bitfld.long 0x0 4. "TXQSTS,MTL Tx Queue Not Empty Status" "0,1" newline bitfld.long 0x0 3. "TWCSTS,MTL Tx Queue Write Controller Status" "0,1" newline bitfld.long 0x0 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status" "0: Idle state,1: Read state (transferring data to the MAC..,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.." newline bitfld.long 0x0 0. "TXQPAUSED,Transmit Queue in Pause" "0,1" group.long 0xD2C++0xB line.long 0x0 "ETH_MTLQICSR,Queue interrupt control status Register" bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable" "0,1" newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status" "0,1" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status" "0,1" line.long 0x4 "ETH_MTLRXQOMR,Rx queue operating mode register" rbitfld.long 0x4 20.--22. "RQS,Receive Queue Size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets" "0,1" newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward" "0,1" newline bitfld.long 0x4 4. "FEP,Forward Error Packets" "0,1" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets" "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control" "0: 64,1: 32,2: 96,3: 128" line.long 0x8 "ETH_MTLRXQMPOCR,Rx queue missed packet and overflow counter register" bitfld.long 0x8 27. "MISCNTOVF,Missed Packet Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 16.--26. 1. "MISPKTCNT,Missed Packet Counter" newline bitfld.long 0x8 11. "OVFCNTOVF,Overflow Counter Overflow Bit" "0,1" newline hexmask.long.word 0x8 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter" rgroup.long 0xD38++0x3 line.long 0x0 "ETH_MTLRXQDR,Rx queue debug register" hexmask.long.word 0x0 16.--29. 1. "PRXQ,Number of Packets in Receive Queue" newline bitfld.long 0x0 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status" "0: Rx queue empty,1: Rx queue fill-level below flow-control..,2: Rx queue fill-level above flow-control activate..,3: Rx queue full" newline bitfld.long 0x0 1.--2. "RRCSTS,MTL Rx Queue Read Controller State" "0: Idle state,1: Reading packet data,2: Reading packet status (or timestamp),3: Flushing the packet data and status" newline bitfld.long 0x0 0. "RWCSTS,MTL Rx Queue Write Controller Active Status" "0,1" group.long 0x1000++0x7 line.long 0x0 "ETH_DMAMR,DMA mode register" bitfld.long 0x0 16.--17. "INTM,Interrupt Mode" "0,1,2,3" newline bitfld.long 0x0 12.--14. "PR,Priority ratio" "0: The priority ratio is 1:1,1: The priority ratio is 2:1,2: The priority ratio is 3:1,3: The priority ratio is 4:1,4: The priority ratio is 5:1,5: The priority ratio is 6:1,6: The priority ratio is 7:1,7: The priority ratio is 8:1" newline bitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" newline bitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration Scheme" "0: Weighted Round-Robin with Rx:Tx or Tx:Rx,1: Fixed priority" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "ETH_DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" newline rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" newline bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "ETH_DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" newline bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt Status" "0,1" line.long 0x4 "ETH_DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process State" newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process State" newline bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "ETH_DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" newline hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "ETH_DMACTXCR,Channel transmit control register" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length" newline bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" newline bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command" "0,1" line.long 0x8 "ETH_DMACRXCR,Channel receive control register" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet Flush" "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length" newline hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" newline bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "ETH_DMACTXDLAR,Channel Tx descriptor list address register" hexmask.long 0x0 0.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "ETH_DMACRXDLAR,Channel Rx descriptor list address register" hexmask.long 0x0 0.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "ETH_DMACTXDTPR,Channel Tx descriptor tail pointer register" hexmask.long 0x4 0.--31. 1. "TDT,Transmit Descriptor Tail Pointer" group.long 0x1128++0x13 line.long 0x0 "ETH_DMACRXDTPR,Channel Rx descriptor tail pointer register" hexmask.long 0x0 0.--31. 1. "RDT,Receive Descriptor Tail Pointer" line.long 0x4 "ETH_DMACTXRLR,Channel Tx descriptor ring length register" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length" line.long 0x8 "ETH_DMACRXRLR,Channel Rx descriptor ring length register" hexmask.long.byte 0x8 16.--23. 1. "ARBS,Alternate Receive Buffer Size" newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length" line.long 0xC "ETH_DMACIER,Channel interrupt enable register" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable" "0: Transmit Interrupt,?" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable" "?,1: Transmit Process Stopped" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable" "0,1" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable" "0,1" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable" "0,1" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "ETH_DMACRXIWTR,Channel Rx interrupt watchdog timer register" bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units" "0: 256,1: 512,2: 1024,3: 2048" newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count" rgroup.long 0x1144++0x3 line.long 0x0 "ETH_DMACCATXDR,Channel current application transmit descriptor register" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer" rgroup.long 0x114C++0x3 line.long 0x0 "ETH_DMACCARXDR,Channel current application receive descriptor register" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer" rgroup.long 0x1154++0x3 line.long 0x0 "ETH_DMACCATXBR,Channel current application transmit buffer register" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer" rgroup.long 0x115C++0x3 line.long 0x0 "ETH_DMACCARXBR,Channel current application receive buffer register" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer" group.long 0x1160++0x3 line.long 0x0 "ETH_DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0: Transmit Interrupt,?" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "?,1: Transmit Process Stopped" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" group.long 0x116C++0x3 line.long 0x0 "ETH_DMACMFCR,Channel missed frame count register" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" tree.end endif sif (cpuis("STM32H753*")) tree "Ethernet_DMA" base ad:0x40029000 group.long 0x0++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x8++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x11C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x14C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x15C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" newline bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" newline bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" tree.end endif sif (cpuis("STM32H753*")) tree "Ethernet_MTL" base ad:0x40028C00 group.long 0x0++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0x100++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" bitfld.long 0x0 16.--18. "TQS,Transmit Queue Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0x104++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0x12C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0x134++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" tree.end endif sif (cpuis("STM32H753*")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "MACRWKPFR,MACRWKPFR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" bitfld.long 0x0 17. "PLS,PLS" "0,1" newline bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" newline rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x7 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" line.long 0x4 "MACDR,Debug register" bitfld.long 0x4 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x4 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x4 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x4 0. "RPESTS,RPESTS" "0,1" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 14.--15. "ADDR64,ADDR64" "0,1,2,3" newline bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" newline hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x7 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA3LR,Address 3 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "Ethernet_MAC" base ad:0x40028000 group.long 0x1000++0x7 line.long 0x0 "DMAMR,DMA mode register" bitfld.long 0x0 16. "INTM,Interrupt Mode" "0,1" rbitfld.long 0x0 12.--14. "PR,Priority ratio" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 11. "TXPR,Transmit priority" "0,1" rbitfld.long 0x0 1. "DA,DMA Tx or Rx Arbitration" "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset" "0,1" line.long 0x4 "DMASBMR,System bus mode register" rbitfld.long 0x4 15. "RB,Rebuild INCRx Burst" "0,1" rbitfld.long 0x4 14. "MB,Mixed Burst" "0,1" bitfld.long 0x4 12. "AAL,Address-Aligned Beats" "0,1" bitfld.long 0x4 0. "FB,Fixed Burst Length" "0,1" rgroup.long 0x1008++0x7 line.long 0x0 "DMAISR,Interrupt status register" bitfld.long 0x0 17. "MACIS,MAC Interrupt Status" "0,1" bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status" "0,1" bitfld.long 0x0 0. "DC0IS,DMA Channel Interrupt" "0,1" line.long 0x4 "DMADSR,Debug status register" hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel Transmit Process" hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel Receive Process" bitfld.long 0x4 0. "AXWHSTS,AHB Master Write Channel" "0,1" group.long 0x1100++0xB line.long 0x0 "DMACCR,Channel control register" bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PBLX8,8xPBL mode" "0,1" hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size" line.long 0x4 "DMACTxCR,Channel transmit control" hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst" bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled" "0,1" bitfld.long 0x4 4. "OSF,Operate on Second Packet" "0,1" bitfld.long 0x4 0. "ST,Start or Stop Transmission" "0,1" line.long 0x8 "DMACRxCR,Channel receive control" bitfld.long 0x8 31. "RPF,DMA Rx Channel Packet" "0,1" hexmask.long.byte 0x8 16.--21. 1. "RXPBL,RXPBL" hexmask.long.word 0x8 1.--14. 1. "RBSZ,Receive Buffer size" bitfld.long 0x8 0. "SR,Start or Stop Receive" "0,1" group.long 0x1114++0x3 line.long 0x0 "DMACTxDLAR,Channel Tx descriptor list address" hexmask.long 0x0 2.--31. 1. "TDESLA,Start of Transmit List" group.long 0x111C++0x7 line.long 0x0 "DMACRxDLAR,Channel Rx descriptor list address" hexmask.long 0x0 2.--31. 1. "RDESLA,Start of Receive List" line.long 0x4 "DMACTxDTPR,Channel Tx descriptor tail pointer" hexmask.long 0x4 2.--31. 1. "TDT,Transmit Descriptor Tail" group.long 0x1128++0x13 line.long 0x0 "DMACRxDTPR,Channel Rx descriptor tail pointer" hexmask.long 0x0 2.--31. 1. "RDT,Receive Descriptor Tail" line.long 0x4 "DMACTxRLR,Channel Tx descriptor ring length" hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring" line.long 0x8 "DMACRxRLR,Channel Rx descriptor ring length" hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring" line.long 0xC "DMACIER,Channel interrupt enable" bitfld.long 0xC 15. "NIE,Normal Interrupt Summary" "0,1" bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary" "0,1" bitfld.long 0xC 13. "CDEE,Context Descriptor Error" "0,1" bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable" "0,1" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt" "0,1" bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt" "0,1" bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout" "0,1" bitfld.long 0xC 8. "RSE,Receive Stopped Enable" "0,1" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable" "0,1" bitfld.long 0xC 6. "RIE,Receive Interrupt Enable" "0,1" bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable" "0,1" bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable" "0,1" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable" "0,1" line.long 0x10 "DMACRxIWTR,Channel Rx interrupt watchdog timer" hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer" rgroup.long 0x1144++0x3 line.long 0x0 "DMACCATxDR,Channel current application transmit" hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address" rgroup.long 0x114C++0x3 line.long 0x0 "DMACCARxDR,Channel current application receive" hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address" rgroup.long 0x1154++0x3 line.long 0x0 "DMACCATxBR,Channel current application transmit buffer" hexmask.long 0x0 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address" rgroup.long 0x115C++0x3 line.long 0x0 "DMACCARxBR,Channel current application receive buffer" hexmask.long 0x0 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address" group.long 0x1160++0x3 line.long 0x0 "DMACSR,Channel status register" rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. "NIS,Normal Interrupt Summary" "0,1" bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error" "0,1" bitfld.long 0x0 12. "FBE,Fatal Bus Error" "0,1" bitfld.long 0x0 11. "ER,Early Receive Interrupt" "0,1" bitfld.long 0x0 10. "ET,Early Transmit Interrupt" "0,1" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout" "0,1" bitfld.long 0x0 8. "RPS,Receive Process Stopped" "0,1" bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable" "0,1" bitfld.long 0x0 6. "RI,Receive Interrupt" "0,1" newline bitfld.long 0x0 2. "TBU,Transmit Buffer" "0,1" bitfld.long 0x0 1. "TPS,Transmit Process Stopped" "0,1" bitfld.long 0x0 0. "TI,Transmit Interrupt" "0,1" rgroup.long 0x116C++0x3 line.long 0x0 "DMACMFCR,Channel missed frame count" bitfld.long 0x0 15. "MFCO,Overflow status of the MFC" "0,1" hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters" group.long 0xC00++0x3 line.long 0x0 "MTLOMR,Operating mode Register" bitfld.long 0x0 9. "CNTCLR,CNTCLR" "0,1" bitfld.long 0x0 8. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 1. "DTXSTS,DTXSTS" "0,1" rgroup.long 0xC20++0x3 line.long 0x0 "MTLISR,Interrupt status Register" bitfld.long 0x0 0. "Q0IS,Queue interrupt status" "0,1" group.long 0xD00++0x3 line.long 0x0 "MTLTxQOMR,Tx queue operating mode" hexmask.long.word 0x0 16.--24. 1. "TQS,Transmit Queue Size" bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable" "0,1,2,3" bitfld.long 0x0 1. "TSF,Transmit Store and Forward" "0,1" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue" "0,1" rgroup.long 0xD04++0x7 line.long 0x0 "MTLTxQUR,Tx queue underflow register" bitfld.long 0x0 11. "UFCNTOVF,UFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter" line.long 0x4 "MTLTxQDR,Tx queue debug Register" bitfld.long 0x4 20.--22. "STXSTSF,STXSTSF" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "PTXQ,PTXQ" "0,1,2,3,4,5,6,7" bitfld.long 0x4 5. "TXSTSFSTS,TXSTSFSTS" "0,1" bitfld.long 0x4 4. "TXQSTS,TXQSTS" "0,1" newline bitfld.long 0x4 3. "TWCSTS,TWCSTS" "0,1" bitfld.long 0x4 1.--2. "TRCSTS,TRCSTS" "0,1,2,3" bitfld.long 0x4 0. "TXQPAUSED,TXQPAUSED" "0,1" group.long 0xD2C++0x7 line.long 0x0 "MTLQICSR,Queue interrupt control status" bitfld.long 0x0 24. "RXOIE,RXOIE" "0,1" bitfld.long 0x0 16. "RXOVFIS,RXOVFIS" "0,1" bitfld.long 0x0 8. "TXUIE,TXUIE" "0,1" bitfld.long 0x0 0. "TXUNFIS,TXUNFIS" "0,1" line.long 0x4 "MTLRxQOMR,Rx queue operating mode" rbitfld.long 0x4 20.--22. "RQS,RQS" "0,1,2,3,4,5,6,7" bitfld.long 0x4 14.--16. "RFD,RFD" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "RFA,RFA" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "EHFC,EHFC" "0,1" newline bitfld.long 0x4 6. "DIS_TCP_EF,DIS_TCP_EF" "0,1" bitfld.long 0x4 5. "RSF,RSF" "0,1" bitfld.long 0x4 4. "FEP,FEP" "0,1" bitfld.long 0x4 3. "FUP,FUP" "0,1" newline bitfld.long 0x4 0.--1. "RTC,RTC" "0,1,2,3" rgroup.long 0xD34++0x7 line.long 0x0 "MTLRxQMPOCR,Rx queue missed packet and overflow counter" bitfld.long 0x0 27. "MISCNTOVF,MISCNTOVF" "0,1" hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,MISPKTCNT" bitfld.long 0x0 11. "OVFCNTOVF,OVFCNTOVF" "0,1" hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,OVFPKTCNT" line.long 0x4 "MTLRxQDR,Rx queue debug register" hexmask.long.word 0x4 16.--29. 1. "PRXQ,PRXQ" bitfld.long 0x4 4.--5. "RXQSTS,RXQSTS" "0,1,2,3" bitfld.long 0x4 1.--2. "RRCSTS,RRCSTS" "0,1,2,3" bitfld.long 0x4 0. "RWCSTS,RWCSTS" "0,1" group.long 0x0++0x17 line.long 0x0 "MACCR,Operating mode configuration" bitfld.long 0x0 31. "ARPEN,ARPEN" "0,1" bitfld.long 0x0 28.--30. "SARC,SARC" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "IPC,IPC" "0,1" bitfld.long 0x0 24.--26. "IPG,IPG" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,GPSLCE" "0,1" bitfld.long 0x0 22. "S2KP,S2KP" "0,1" bitfld.long 0x0 21. "CST,CST" "0,1" bitfld.long 0x0 20. "ACS,ACS" "0,1" newline bitfld.long 0x0 19. "WD,WD" "0,1" bitfld.long 0x0 17. "JD,JD" "0,1" bitfld.long 0x0 16. "JE,JE" "0,1" bitfld.long 0x0 14. "FES,FES" "0,1" newline bitfld.long 0x0 13. "DM,DM" "0,1" bitfld.long 0x0 12. "LM,LM" "0,1" bitfld.long 0x0 11. "ECRSFD,ECRSFD" "0,1" bitfld.long 0x0 10. "DO,DO" "0,1" newline bitfld.long 0x0 9. "DCRS,DCRS" "0,1" bitfld.long 0x0 8. "DR,DR" "0,1" bitfld.long 0x0 5.--6. "BL,BL" "0,1,2,3" bitfld.long 0x0 4. "DC,DC" "0,1" newline bitfld.long 0x0 2.--3. "PRELEN,PRELEN" "0,1,2,3" bitfld.long 0x0 1. "TE,TE" "0,1" bitfld.long 0x0 0. "RE,Receiver Enable" "0,1" line.long 0x4 "MACECR,Extended operating mode configuration" hexmask.long.byte 0x4 25.--29. 1. "EIPG,EIPG" bitfld.long 0x4 24. "EIPGEN,EIPGEN" "0,1" bitfld.long 0x4 18. "USP,USP" "0,1" bitfld.long 0x4 17. "SPEN,SPEN" "0,1" newline bitfld.long 0x4 16. "DCRCC,DCRCC" "0,1" hexmask.long.word 0x4 0.--13. 1. "GPSL,GPSL" line.long 0x8 "MACPFR,Packet filtering control" bitfld.long 0x8 31. "RA,RA" "0,1" bitfld.long 0x8 21. "DNTU,DNTU" "0,1" bitfld.long 0x8 20. "IPFE,IPFE" "0,1" bitfld.long 0x8 16. "VTFE,VTFE" "0,1" newline bitfld.long 0x8 10. "HPF,HPF" "0,1" bitfld.long 0x8 9. "SAF,SAF" "0,1" bitfld.long 0x8 8. "SAIF,SAIF" "0,1" bitfld.long 0x8 6.--7. "PCF,PCF" "0,1,2,3" newline bitfld.long 0x8 5. "DBF,DBF" "0,1" bitfld.long 0x8 4. "PM,PM" "0,1" bitfld.long 0x8 3. "DAIF,DAIF" "0,1" bitfld.long 0x8 2. "HMC,HMC" "0,1" newline bitfld.long 0x8 1. "HUC,HUC" "0,1" bitfld.long 0x8 0. "PR,PR" "0,1" line.long 0xC "MACWTR,Watchdog timeout register" bitfld.long 0xC 8. "PWE,PWE" "0,1" hexmask.long.byte 0xC 0.--3. 1. "WTO,WTO" line.long 0x10 "MACHT0R,Hash Table 0 register" hexmask.long 0x10 0.--31. 1. "HT31T0,HT31T0" line.long 0x14 "MACHT1R,Hash Table 1 register" hexmask.long 0x14 0.--31. 1. "HT63T32,HT63T32" group.long 0x50++0x3 line.long 0x0 "MACVTR,VLAN tag register" bitfld.long 0x0 31. "EIVLRXS,EIVLRXS" "0,1" bitfld.long 0x0 28.--29. "EIVLS,EIVLS" "0,1,2,3" bitfld.long 0x0 27. "ERIVLT,ERIVLT" "0,1" bitfld.long 0x0 26. "EDVLP,EDVLP" "0,1" newline bitfld.long 0x0 25. "VTHM,VTHM" "0,1" bitfld.long 0x0 24. "EVLRXS,EVLRXS" "0,1" bitfld.long 0x0 21.--22. "EVLS,EVLS" "0,1,2,3" bitfld.long 0x0 20. "DOVLTC,DOVLTC" "0,1" newline bitfld.long 0x0 19. "ERSVLM,ERSVLM" "0,1" bitfld.long 0x0 18. "ESVL,ESVL" "0,1" bitfld.long 0x0 17. "VTIM,VTIM" "0,1" bitfld.long 0x0 16. "ETV,ETV" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "VL,VL" group.long 0x58++0x3 line.long 0x0 "MACVHTR,VLAN Hash table register" hexmask.long.word 0x0 0.--15. 1. "VLHT,VLHT" group.long 0x60++0x7 line.long 0x0 "MACVIR,VLAN inclusion register" bitfld.long 0x0 20. "VLTI,VLTI" "0,1" bitfld.long 0x0 19. "CSVL,CSVL" "0,1" bitfld.long 0x0 18. "VLP,VLP" "0,1" bitfld.long 0x0 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLT" line.long 0x4 "MACIVIR,Inner VLAN inclusion register" bitfld.long 0x4 20. "VLTI,VLTI" "0,1" bitfld.long 0x4 19. "CSVL,CSVL" "0,1" bitfld.long 0x4 18. "VLP,VLP" "0,1" bitfld.long 0x4 16.--17. "VLC,VLC" "0,1,2,3" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLT" group.long 0x70++0x3 line.long 0x0 "MACQTxFCR,Tx Queue flow control register" hexmask.long.word 0x0 16.--31. 1. "PT,PT" bitfld.long 0x0 7. "DZPQ,DZPQ" "0,1" bitfld.long 0x0 4.--6. "PLT,PLT" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1. "TFE,TFE" "0,1" newline bitfld.long 0x0 0. "FCB_BPA,FCB_BPA" "0,1" group.long 0x90++0x3 line.long 0x0 "MACRxFCR,Rx flow control register" bitfld.long 0x0 1. "UP,UP" "0,1" bitfld.long 0x0 0. "RFE,RFE" "0,1" rgroup.long 0xB0++0x3 line.long 0x0 "MACISR,Interrupt status register" bitfld.long 0x0 14. "RXSTSIS,RXSTSIS" "0,1" bitfld.long 0x0 13. "TXSTSIS,TXSTSIS" "0,1" bitfld.long 0x0 12. "TSIS,TSIS" "0,1" bitfld.long 0x0 10. "MMCTXIS,MMCTXIS" "0,1" newline bitfld.long 0x0 9. "MMCRXIS,MMCRXIS" "0,1" bitfld.long 0x0 8. "MMCIS,MMCIS" "0,1" bitfld.long 0x0 5. "LPIIS,LPIIS" "0,1" bitfld.long 0x0 4. "PMTIS,PMTIS" "0,1" newline bitfld.long 0x0 3. "PHYIS,PHYIS" "0,1" group.long 0xB4++0x3 line.long 0x0 "MACIER,Interrupt enable register" bitfld.long 0x0 14. "RXSTSIE,RXSTSIE" "0,1" bitfld.long 0x0 13. "TXSTSIE,TXSTSIE" "0,1" bitfld.long 0x0 12. "TSIE,TSIE" "0,1" bitfld.long 0x0 5. "LPIIE,LPIIE" "0,1" newline bitfld.long 0x0 4. "PMTIE,PMTIE" "0,1" bitfld.long 0x0 3. "PHYIE,PHYIE" "0,1" rgroup.long 0xB8++0x3 line.long 0x0 "MACRxTxSR,Rx Tx status register" bitfld.long 0x0 8. "RWT,RWT" "0,1" bitfld.long 0x0 5. "EXCOL,LCOL" "0,1" bitfld.long 0x0 4. "LCOL,LCOL" "0,1" bitfld.long 0x0 3. "EXDEF,EXDEF" "0,1" newline bitfld.long 0x0 2. "LCARR,LCARR" "0,1" bitfld.long 0x0 1. "NCARR,NCARR" "0,1" bitfld.long 0x0 0. "TJT,TJT" "0,1" group.long 0xC0++0x7 line.long 0x0 "MACPCSR,PMT control status register" bitfld.long 0x0 31. "RWKFILTRST,RWKFILTRST" "0,1" hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,RWKPTR" bitfld.long 0x0 10. "RWKPFE,RWKPFE" "0,1" bitfld.long 0x0 9. "GLBLUCAST,GLBLUCAST" "0,1" newline rbitfld.long 0x0 6. "RWKPRCVD,RWKPRCVD" "0,1" rbitfld.long 0x0 5. "MGKPRCVD,MGKPRCVD" "0,1" bitfld.long 0x0 2. "RWKPKTEN,RWKPKTEN" "0,1" bitfld.long 0x0 1. "MGKPKTEN,MGKPKTEN" "0,1" newline bitfld.long 0x0 0. "PWRDWN,PWRDWN" "0,1" line.long 0x4 "MACRWKPFR,Remove wakeup packet filter" hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,WKUPFRMFTR" group.long 0xD0++0xF line.long 0x0 "MACLCSR,LPI control status register" bitfld.long 0x0 21. "LPITCSE,LPITCSE" "0,1" bitfld.long 0x0 20. "LPITE,LPITE" "0,1" bitfld.long 0x0 19. "LPITXA,LPITXA" "0,1" bitfld.long 0x0 18. "PLSEN,PLSEN" "0,1" newline bitfld.long 0x0 17. "PLS,PLS" "0,1" bitfld.long 0x0 16. "LPIEN,LPIEN" "0,1" rbitfld.long 0x0 9. "RLPIST,RLPIST" "0,1" rbitfld.long 0x0 8. "TLPIST,TLPIST" "0,1" newline rbitfld.long 0x0 3. "RLPIEX,RLPIEX" "0,1" rbitfld.long 0x0 2. "RLPIEN,RLPIEN" "0,1" rbitfld.long 0x0 1. "TLPIEX,TLPIEX" "0,1" rbitfld.long 0x0 0. "TLPIEN,TLPIEN" "0,1" line.long 0x4 "MACLTCR,LPI timers control register" hexmask.long.word 0x4 16.--25. 1. "LST,LST" hexmask.long.word 0x4 0.--15. 1. "TWT,TWT" line.long 0x8 "MACLETR,LPI entry timer register" hexmask.long.tbyte 0x8 0.--16. 1. "LPIET,LPIET" line.long 0xC "MAC1USTCR,1-microsecond-tick counter" hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,TIC_1US_CNTR" rgroup.long 0x110++0x3 line.long 0x0 "MACVR,Version register" hexmask.long.byte 0x0 8.--15. 1. "USERVER,USERVER" hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,SNPSVER" rgroup.long 0x120++0x7 line.long 0x0 "MACHWF1R,HW feature 1 register" hexmask.long.byte 0x0 27.--30. 1. "L3L4FNUM,L3L4FNUM" bitfld.long 0x0 24.--25. "HASHTBLSZ,HASHTBLSZ" "0,1,2,3" bitfld.long 0x0 20. "AVSEL,AVSEL" "0,1" bitfld.long 0x0 19. "DBGMEMA,DBGMEMA" "0,1" newline bitfld.long 0x0 18. "TSOEN,TSOEN" "0,1" bitfld.long 0x0 17. "SPHEN,SPHEN" "0,1" bitfld.long 0x0 16. "DCBEN,DCBEN" "0,1" bitfld.long 0x0 13. "ADVTHWORD,ADVTHWORD" "0,1" newline bitfld.long 0x0 12. "PTOEN,PTOEN" "0,1" bitfld.long 0x0 11. "OSTEN,OSTEN" "0,1" hexmask.long.byte 0x0 6.--10. 1. "TXFIFOSIZE,TXFIFOSIZE" hexmask.long.byte 0x0 0.--4. 1. "RXFIFOSIZE,RXFIFOSIZE" line.long 0x4 "MACHWF2R,HW feature 2 register" bitfld.long 0x4 28.--30. "AUXSNAPNUM,AUXSNAPNUM" "0,1,2,3,4,5,6,7" bitfld.long 0x4 24.--26. "PPSOUTNUM,PPSOUTNUM" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 18.--21. 1. "TXCHCNT,TXCHCNT" hexmask.long.byte 0x4 12.--15. 1. "RXCHCNT,RXCHCNT" newline hexmask.long.byte 0x4 6.--9. 1. "TXQCNT,TXQCNT" hexmask.long.byte 0x4 0.--3. 1. "RXQCNT,RXQCNT" group.long 0x200++0x7 line.long 0x0 "MACMDIOAR,MDIO address register" bitfld.long 0x0 27. "PSE,PSE" "0,1" bitfld.long 0x0 26. "BTB,BTB" "0,1" hexmask.long.byte 0x0 21.--25. 1. "PA,PA" hexmask.long.byte 0x0 16.--20. 1. "RDA,RDA" newline bitfld.long 0x0 12.--14. "NTC,NTC" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "CR,CR" bitfld.long 0x0 4. "SKAP,SKAP" "0,1" bitfld.long 0x0 2.--3. "GOC,GOC" "0,1,2,3" newline bitfld.long 0x0 1. "C45E,C45E" "0,1" bitfld.long 0x0 0. "MB,MB" "0,1" line.long 0x4 "MACMDIODR,MDIO data register" hexmask.long.word 0x4 16.--31. 1. "RA,RA" hexmask.long.word 0x4 0.--15. 1. "MD,MD" group.long 0xAE0++0x3 line.long 0x0 "MACARPAR,ARP address register" hexmask.long 0x0 0.--31. 1. "ARPPA,ARPPA" group.long 0x300++0x7 line.long 0x0 "MACA0HR,Address 0 high register" rbitfld.long 0x0 31. "AE,AE" "0,1" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" line.long 0x4 "MACA0LR,Address 0 low register" hexmask.long 0x4 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x30C++0x3 line.long 0x0 "MACA1LR,Address 1 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x314++0x3 line.long 0x0 "MACA2LR,Address 2 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x31C++0x3 line.long 0x0 "MACA3LR,Address 3 low register" hexmask.long 0x0 0.--31. 1. "ADDRLO,ADDRLO" group.long 0x308++0x3 line.long 0x0 "MACA1HR,Address 1 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x310++0x3 line.long 0x0 "MACA2HR,Address 2 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x318++0x3 line.long 0x0 "MACA3HR,Address 3 high register" bitfld.long 0x0 31. "AE,AE" "0,1" bitfld.long 0x0 30. "SA,SA" "0,1" hexmask.long.byte 0x0 24.--29. 1. "MBC,MBC" hexmask.long.word 0x0 0.--15. 1. "ADDRHI,ADDRHI" group.long 0x700++0x3 line.long 0x0 "MMC_CONTROL,MMC control register" bitfld.long 0x0 8. "UCDBC,UCDBC" "0,1" bitfld.long 0x0 5. "CNTPRSTLVL,CNTPRSTLVL" "0,1" bitfld.long 0x0 4. "CNTPRST,CNTPRST" "0,1" bitfld.long 0x0 3. "CNTFREEZ,CNTFREEZ" "0,1" newline bitfld.long 0x0 2. "RSTONRD,RSTONRD" "0,1" bitfld.long 0x0 1. "CNTSTOPRO,CNTSTOPRO" "0,1" bitfld.long 0x0 0. "CNTRST,CNTRST" "0,1" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,MMC Rx interrupt register" bitfld.long 0x0 27. "RXLPITRCIS,RXLPITRCIS" "0,1" bitfld.long 0x0 26. "RXLPIUSCIS,RXLPIUSCIS" "0,1" bitfld.long 0x0 17. "RXUCGPIS,RXUCGPIS" "0,1" bitfld.long 0x0 6. "RXALGNERPIS,RXALGNERPIS" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIS,RXCRCERPIS" "0,1" line.long 0x4 "MMC_TX_INTERRUPT,MMC Tx interrupt register" bitfld.long 0x4 27. "TXLPITRCIS,TXLPITRCIS" "0,1" bitfld.long 0x4 26. "TXLPIUSCIS,TXLPIUSCIS" "0,1" bitfld.long 0x4 21. "TXGPKTIS,TXGPKTIS" "0,1" bitfld.long 0x4 15. "TXMCOLGPIS,TXMCOLGPIS" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIS,TXSCOLGPIS" "0,1" group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,MMC Rx interrupt mask register" rbitfld.long 0x0 27. "RXLPITRCIM,RXLPITRCIM" "0,1" bitfld.long 0x0 26. "RXLPIUSCIM,RXLPIUSCIM" "0,1" bitfld.long 0x0 17. "RXUCGPIM,RXUCGPIM" "0,1" bitfld.long 0x0 6. "RXALGNERPIM,RXALGNERPIM" "0,1" newline bitfld.long 0x0 5. "RXCRCERPIM,RXCRCERPIM" "0,1" line.long 0x4 "MMC_TX_INTERRUPT_MASK,MMC Tx interrupt mask register" rbitfld.long 0x4 27. "TXLPITRCIM,TXLPITRCIM" "0,1" bitfld.long 0x4 26. "TXLPIUSCIM,TXLPIUSCIM" "0,1" bitfld.long 0x4 21. "TXGPKTIM,TXGPKTIM" "0,1" bitfld.long 0x4 15. "TXMCOLGPIM,TXMCOLGPIM" "0,1" newline bitfld.long 0x4 14. "TXSCOLGPIM,TXSCOLGPIM" "0,1" rgroup.long 0x74C++0x7 line.long 0x0 "TX_SINGLE_COLLISION_GOOD_PACKETS,Tx single collision good packets" hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,TXSNGLCOLG" line.long 0x4 "TX_MULTIPLE_COLLISION_GOOD_PACKETS,Tx multiple collision good packets" hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,TXMULTCOLG" rgroup.long 0x768++0x3 line.long 0x0 "TX_PACKET_COUNT_GOOD,Tx packet count good register" hexmask.long 0x0 0.--31. 1. "TXPKTG,TXPKTG" rgroup.long 0x794++0x7 line.long 0x0 "RX_CRC_ERROR_PACKETS,Rx CRC error packets register" hexmask.long 0x0 0.--31. 1. "RXCRCERR,RXCRCERR" line.long 0x4 "RX_ALIGNMENT_ERROR_PACKETS,Rx alignment error packets" hexmask.long 0x4 0.--31. 1. "RXALGNERR,RXALGNERR" rgroup.long 0x7C4++0x3 line.long 0x0 "RX_UNICAST_PACKETS_GOOD,Rx unicast packets good" hexmask.long 0x0 0.--31. 1. "RXUCASTG,RXUCASTG" rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,Tx LPI microsecond timer" hexmask.long 0x0 0.--31. 1. "TXLPIUSC,TXLPIUSC" line.long 0x4 "TX_LPI_TRAN_CNTR,Tx LPI transition counter" hexmask.long 0x4 0.--31. 1. "TXLPITRC,TXLPITRC" line.long 0x8 "RX_LPI_USEC_CNTR,Rx LPI microsecond counter" hexmask.long 0x8 0.--31. 1. "RXLPIUSC,RXLPIUSC" line.long 0xC "RX_LPI_TRAN_CNTR,Rx LPI transition counter" hexmask.long 0xC 0.--31. 1. "RXLPITRC,RXLPITRC" group.long 0x900++0x7 line.long 0x0 "MACL3L4C0R,L3 and L4 control 0 register" bitfld.long 0x0 21. "L4DPIM0,L4DPIM0" "0,1" bitfld.long 0x0 20. "L4DPM0,L4DPM0" "0,1" bitfld.long 0x0 19. "L4SPIM0,L4SPIM0" "0,1" bitfld.long 0x0 18. "L4SPM0,L4SPM0" "0,1" newline bitfld.long 0x0 16. "L4PEN0,L4PEN0" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,L3HDBM0" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,L3HSBM0" bitfld.long 0x0 5. "L3DAIM0,L3DAIM0" "0,1" newline bitfld.long 0x0 4. "L3DAM0,L3DAM0" "0,1" bitfld.long 0x0 3. "L3SAIM0,L3SAIM0" "0,1" bitfld.long 0x0 2. "L3SAM0,L3SAM0" "0,1" bitfld.long 0x0 0. "L3PEN0,L3PEN0" "0,1" line.long 0x4 "MACL4A0R,Layer4 address filter 0" hexmask.long.word 0x4 16.--31. 1. "L4DP0,L4DP0" hexmask.long.word 0x4 0.--15. 1. "L4SP0,L4SP0" rgroup.long 0x114++0x3 line.long 0x0 "MACDR,Debug register" bitfld.long 0x0 17.--18. "TFCSTS,TFCSTS" "0,1,2,3" bitfld.long 0x0 16. "TPESTS,TPESTS" "0,1" bitfld.long 0x0 1.--2. "RFCFCSTS,RFCFCSTS" "0,1,2,3" bitfld.long 0x0 0. "RPESTS,RPESTS" "0,1" group.long 0x910++0xF line.long 0x0 "MACL3A00R,MACL3A00R" hexmask.long 0x0 0.--31. 1. "L3A00,L3A00" line.long 0x4 "MACL3A10R,Layer3 address 1 filter 0" hexmask.long 0x4 0.--31. 1. "L3A10,L3A10" line.long 0x8 "MACL3A20,Layer3 Address 2 filter 0" hexmask.long 0x8 0.--31. 1. "L3A20,L3A20" line.long 0xC "MACL3A30,Layer3 Address 3 filter 0" hexmask.long 0xC 0.--31. 1. "L3A30,L3A30" group.long 0x930++0x7 line.long 0x0 "MACL3L4C1R,L3 and L4 control 1 register" bitfld.long 0x0 21. "L4DPIM1,L4DPIM1" "0,1" bitfld.long 0x0 20. "L4DPM1,L4DPM1" "0,1" bitfld.long 0x0 19. "L4SPIM1,L4SPIM1" "0,1" bitfld.long 0x0 18. "L4SPM1,L4SPM1" "0,1" newline bitfld.long 0x0 16. "L4PEN1,L4PEN1" "0,1" hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,L3HDBM1" hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,L3HSBM1" bitfld.long 0x0 5. "L3DAIM1,L3DAIM1" "0,1" newline bitfld.long 0x0 4. "L3DAM1,L3DAM1" "0,1" bitfld.long 0x0 3. "L3SAIM1,L3SAIM1" "0,1" bitfld.long 0x0 2. "L3SAM1,L3SAM1" "0,1" bitfld.long 0x0 0. "L3PEN1,L3PEN1" "0,1" line.long 0x4 "MACL4A1R,Layer 4 address filter 1" hexmask.long.word 0x4 16.--31. 1. "L4DP1,L4DP1" hexmask.long.word 0x4 0.--15. 1. "L4SP1,L4SP1" group.long 0x940++0xF line.long 0x0 "MACL3A01R,Layer3 address 0 filter 1" hexmask.long 0x0 0.--31. 1. "L3A01,L3A01" line.long 0x4 "MACL3A11R,Layer3 address 1 filter 1" hexmask.long 0x4 0.--31. 1. "L3A11,L3A11" line.long 0x8 "MACL3A21R,Layer3 address 2 filter 1" hexmask.long 0x8 0.--31. 1. "L3A21,L3A21" line.long 0xC "MACL3A31R,Layer3 address 3 filter 1" hexmask.long 0xC 0.--31. 1. "L3A31,L3A31" group.long 0xB00++0x7 line.long 0x0 "MACTSCR,Timestamp control Register" bitfld.long 0x0 24. "TXTSSTSM,TXTSSTSM" "0,1" rbitfld.long 0x0 19. "CSC,CSC" "0,1" bitfld.long 0x0 18. "TSENMACADDR,TSENMACADDR" "0,1" bitfld.long 0x0 16.--17. "SNAPTYPSEL,SNAPTYPSEL" "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,TSMSTRENA" "0,1" bitfld.long 0x0 14. "TSEVNTENA,TSEVNTENA" "0,1" bitfld.long 0x0 13. "TSIPV4ENA,TSIPV4ENA" "0,1" bitfld.long 0x0 12. "TSIPV6ENA,TSIPV6ENA" "0,1" newline bitfld.long 0x0 11. "TSIPENA,TSIPENA" "0,1" bitfld.long 0x0 10. "TSVER2ENA,TSVER2ENA" "0,1" bitfld.long 0x0 9. "TSCTRLSSR,TSCTRLSSR" "0,1" bitfld.long 0x0 8. "TSENALL,TSENALL" "0,1" newline bitfld.long 0x0 5. "TSADDREG,TSADDREG" "0,1" bitfld.long 0x0 3. "TSUPDT,TSUPDT" "0,1" bitfld.long 0x0 2. "TSINIT,TSINIT" "0,1" bitfld.long 0x0 1. "TSCFUPDT,TSCFUPDT" "0,1" newline bitfld.long 0x0 0. "TSENA,TSENA" "0,1" line.long 0x4 "MACSSIR,Sub-second increment register" hexmask.long.byte 0x4 16.--23. 1. "SSINC,SSINC" hexmask.long.byte 0x4 8.--15. 1. "SNSINC,SNSINC" rgroup.long 0xB08++0x7 line.long 0x0 "MACSTSR,System time seconds register" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNR,System time nanoseconds" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" group.long 0xB10++0xB line.long 0x0 "MACSTSUR,System time seconds update" hexmask.long 0x0 0.--31. 1. "TSS,TSS" line.long 0x4 "MACSTNUR,System time nanoseconds update" bitfld.long 0x4 31. "ADDSUB,ADDSUB" "0,1" hexmask.long 0x4 0.--30. 1. "TSSS,TSSS" line.long 0x8 "MACTSAR,Timestamp addend register" hexmask.long 0x8 0.--31. 1. "TSAR,TSAR" rgroup.long 0xB20++0x3 line.long 0x0 "MACTSSR,Timestamp status register" hexmask.long.byte 0x0 25.--29. 1. "ATSNS,ATSNS" bitfld.long 0x0 24. "ATSSTM,ATSSTM" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,ATSSTN" bitfld.long 0x0 15. "TXTSSIS,TXTSSIS" "0,1" newline bitfld.long 0x0 3. "TSTRGTERR0,TSTRGTERR0" "0,1" bitfld.long 0x0 2. "AUXTSTRIG,AUXTSTRIG" "0,1" bitfld.long 0x0 1. "TSTARGT0,TSTARGT0" "0,1" bitfld.long 0x0 0. "TSSOVF,TSSOVF" "0,1" rgroup.long 0xB30++0x7 line.long 0x0 "MACTxTSSNR,Tx timestamp status nanoseconds" bitfld.long 0x0 31. "TXTSSMIS,TXTSSMIS" "0,1" hexmask.long 0x0 0.--30. 1. "TXTSSLO,TXTSSLO" line.long 0x4 "MACTxTSSSR,Tx timestamp status seconds" hexmask.long 0x4 0.--31. 1. "TXTSSHI,TXTSSHI" group.long 0xB40++0x3 line.long 0x0 "MACACR,Auxiliary control register" bitfld.long 0x0 7. "ATSEN3,ATSEN3" "0,1" bitfld.long 0x0 6. "ATSEN2,ATSEN2" "0,1" bitfld.long 0x0 5. "ATSEN1,ATSEN1" "0,1" bitfld.long 0x0 4. "ATSEN0,ATSEN0" "0,1" newline bitfld.long 0x0 0. "ATSFC,ATSFC" "0,1" rgroup.long 0xB48++0x7 line.long 0x0 "MACATSNR,Auxiliary timestamp nanoseconds" hexmask.long 0x0 0.--30. 1. "AUXTSLO,AUXTSLO" line.long 0x4 "MACATSSR,Auxiliary timestamp seconds" hexmask.long 0x4 0.--31. 1. "AUXTSHI,AUXTSHI" group.long 0xB50++0xF line.long 0x0 "MACTSIACR,Timestamp Ingress asymmetric correction" hexmask.long 0x0 0.--31. 1. "OSTIAC,OSTIAC" line.long 0x4 "MACTSEACR,Timestamp Egress asymmetric correction" hexmask.long 0x4 0.--31. 1. "OSTEAC,OSTEAC" line.long 0x8 "MACTSICNR,Timestamp Ingress correction nanosecond" hexmask.long 0x8 0.--31. 1. "TSIC,TSIC" line.long 0xC "MACTSECNR,Timestamp Egress correction nanosecond" hexmask.long 0xC 0.--31. 1. "TSEC,TSEC" group.long 0xB70++0x3 line.long 0x0 "MACPPSCR,PPS control register" bitfld.long 0x0 5.--6. "TRGTMODSEL0,TRGTMODSEL0" "0,1,2,3" bitfld.long 0x0 4. "PPSEN0,PPSEN0" "0,1" hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL,PPSCTRL" group.long 0xB80++0xF line.long 0x0 "MACPPSTTSR,PPS target time seconds" hexmask.long 0x0 0.--30. 1. "TSTRH0,TSTRH0" line.long 0x4 "MACPPSTTNR,PPS target time nanoseconds" bitfld.long 0x4 31. "TRGTBUSY0,TRGTBUSY0" "0,1" hexmask.long 0x4 0.--30. 1. "TTSL0,TTSL0" line.long 0x8 "MACPPSIR,PPS interval register" hexmask.long 0x8 0.--31. 1. "PPSINT0,PPSINT0" line.long 0xC "MACPPSWR,PPS width register" hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPSWIDTH0" group.long 0xBC0++0x13 line.long 0x0 "MACPOCR,PTP Offload control register" hexmask.long.byte 0x0 8.--15. 1. "DN,DN" bitfld.long 0x0 6. "DRRDIS,DRRDIS" "0,1" bitfld.long 0x0 5. "APDREQTRIG,APDREQTRIG" "0,1" bitfld.long 0x0 4. "ASYNCTRIG,ASYNCTRIG" "0,1" newline bitfld.long 0x0 2. "APDREQEN,APDREQEN" "0,1" bitfld.long 0x0 1. "ASYNCEN,ASYNCEN" "0,1" bitfld.long 0x0 0. "PTOEN,PTOEN" "0,1" line.long 0x4 "MACSPI0R,PTP Source Port Identity 0" hexmask.long 0x4 0.--31. 1. "SPI0,SPI0" line.long 0x8 "MACSPI1R,PTP Source port identity 1" hexmask.long 0x8 0.--31. 1. "SPI1,SPI1" line.long 0xC "MACSPI2R,PTP Source port identity 2" hexmask.long.word 0xC 0.--15. 1. "SPI2,SPI2" line.long 0x10 "MACLMIR,Log message interval register" hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,LMPDRI" bitfld.long 0x10 8.--10. "DRSYNCR,DRSYNCR" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 0.--7. 1. "LSI,LSI" tree.end endif tree.end endif tree "EXTI (External Interrupt/Event Controller)" base ad:0x58000000 group.long 0x0++0x17 line.long 0x0 "RTSR1,EXTI rising trigger selection" bitfld.long 0x0 21. "TR21,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 20. "TR20,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 19. "TR19,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 18. "TR18,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 17. "TR17,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit" "0,1" newline bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit" "0,1" line.long 0x4 "FTSR1,EXTI falling trigger selection" bitfld.long 0x4 21. "TR21,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 20. "TR20,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 19. "TR19,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 18. "TR18,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 17. "TR17,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 16. "TR16,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 15. "TR15,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 14. "TR14,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 13. "TR13,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 12. "TR12,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 11. "TR11,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 10. "TR10,Rising trigger event configuration bit" "0,1" newline bitfld.long 0x4 9. "TR9,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 8. "TR8,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 7. "TR7,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 6. "TR6,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 5. "TR5,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 4. "TR4,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 3. "TR3,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 2. "TR2,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 1. "TR1,Rising trigger event configuration bit" "0,1" bitfld.long 0x4 0. "TR0,Rising trigger event configuration bit" "0,1" line.long 0x8 "SWIER1,EXTI software interrupt event" bitfld.long 0x8 21. "SWIER21,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 20. "SWIER20,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 19. "SWIER19,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 18. "SWIER18,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 17. "SWIER17,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 16. "SWIER16,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 15. "SWIER15,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 14. "SWIER14,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 13. "SWIER13,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 12. "SWIER12,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 11. "SWIER11,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 10. "SWIER10,Rising trigger event configuration bit" "0,1" newline bitfld.long 0x8 9. "SWIER9,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 8. "SWIER8,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 7. "SWIER7,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 6. "SWIER6,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 5. "SWIER5,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 4. "SWIER4,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 3. "SWIER3,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 2. "SWIER2,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 1. "SWIER1,Rising trigger event configuration bit" "0,1" bitfld.long 0x8 0. "SWIER0,Rising trigger event configuration bit" "0,1" line.long 0xC "D3PMR1,EXTI D3 pending mask register" bitfld.long 0xC 25. "MR25,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 21. "MR21,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 20. "MR20,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 19. "MR19,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 15. "MR15,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 14. "MR14,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 13. "MR13,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 12. "MR12,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 11. "MR11,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 10. "MR10,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 9. "MR9,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 8. "MR8,Rising trigger event configuration bit" "0,1" newline bitfld.long 0xC 7. "MR7,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 6. "MR6,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 5. "MR5,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 4. "MR4,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 3. "MR3,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 2. "MR2,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 1. "MR1,Rising trigger event configuration bit" "0,1" bitfld.long 0xC 0. "MR0,Rising trigger event configuration bit" "0,1" line.long 0x10 "D3PCR1L,EXTI D3 pending clear selection register" bitfld.long 0x10 30.--31. "PCS15,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 28.--29. "PCS14,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 26.--27. "PCS13,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 24.--25. "PCS12,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 22.--23. "PCS11,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 20.--21. "PCS10,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 18.--19. "PCS9,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 16.--17. "PCS8,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 14.--15. "PCS7,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 12.--13. "PCS6,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 10.--11. "PCS5,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 8.--9. "PCS4,D3 Pending request clear input signal" "0,1,2,3" newline bitfld.long 0x10 6.--7. "PCS3,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 4.--5. "PCS2,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 2.--3. "PCS1,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 0.--1. "PCS0,D3 Pending request clear input signal" "0,1,2,3" line.long 0x14 "D3PCR1H,EXTI D3 pending clear selection register" bitfld.long 0x14 18.--19. "PCS25,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 10.--11. "PCS21,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 8.--9. "PCS20,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 6.--7. "PCS19,D3 Pending request clear input signal" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "RTSR2,EXTI rising trigger selection" bitfld.long 0x0 19. "TR51,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 17. "TR49,Rising trigger event configuration bit" "0,1" line.long 0x4 "FTSR2,EXTI falling trigger selection" bitfld.long 0x4 19. "TR51,Falling trigger event configuration bit" "0,1" bitfld.long 0x4 17. "TR49,Falling trigger event configuration bit" "0,1" line.long 0x8 "SWIER2,EXTI software interrupt event" bitfld.long 0x8 19. "SWIER51,Software interrupt on line" "0,1" bitfld.long 0x8 17. "SWIER49,Software interrupt on line" "0,1" line.long 0xC "D3PMR2,EXTI D3 pending mask register" bitfld.long 0xC 21. "MR53,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 20. "MR52,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 19. "MR51,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 18. "MR50,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 17. "MR49,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 16. "MR48,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 9. "MR41,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 3. "MR35,D3 Pending Mask on Event input" "0,1" bitfld.long 0xC 2. "MR34,D3 Pending Mask on Event input" "0,1" line.long 0x10 "D3PCR2L,EXTI D3 pending clear selection register" bitfld.long 0x10 18.--19. "PCS41,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 6.--7. "PCS35,D3 Pending request clear input signal" "0,1,2,3" bitfld.long 0x10 4.--5. "PCS34,D3 Pending request clear input signal" "0,1,2,3" line.long 0x14 "D3PCR2H,EXTI D3 pending clear selection register" bitfld.long 0x14 10.--11. "PCS53,Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 8.--9. "PCS52,Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 6.--7. "PCS51,Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 4.--5. "PCS50,Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 2.--3. "PCS49,Pending request clear input signal" "0,1,2,3" bitfld.long 0x14 0.--1. "PCS48,Pending request clear input signal" "0,1,2,3" group.long 0x40++0xF line.long 0x0 "RTSR3,EXTI rising trigger selection" bitfld.long 0x0 22. "TR86,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 21. "TR85,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 20. "TR84,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 18. "TR82,Rising trigger event configuration bit" "0,1" line.long 0x4 "FTSR3,EXTI falling trigger selection" bitfld.long 0x4 22. "TR86,Falling trigger event configuration bit" "0,1" bitfld.long 0x4 21. "TR85,Falling trigger event configuration bit" "0,1" bitfld.long 0x4 20. "TR84,Falling trigger event configuration bit" "0,1" bitfld.long 0x4 18. "TR82,Falling trigger event configuration bit" "0,1" line.long 0x8 "SWIER3,EXTI software interrupt event" bitfld.long 0x8 22. "SWIER86,Software interrupt on line" "0,1" bitfld.long 0x8 21. "SWIER85,Software interrupt on line" "0,1" bitfld.long 0x8 20. "SWIER84,Software interrupt on line" "0,1" bitfld.long 0x8 18. "SWIER82,Software interrupt on line" "0,1" line.long 0xC "D3PMR3,EXTI D3 pending mask register" bitfld.long 0xC 24. "MR88,D3 Pending Mask on Event input" "0,1" group.long 0x54++0x3 line.long 0x0 "D3PCR3H,EXTI D3 pending clear selection register" bitfld.long 0x0 18.--19. "PCS88,D3 Pending request clear input signal" "0,1,2,3" group.long 0x80++0xB line.long 0x0 "CPUIMR1,EXTI interrupt mask register" bitfld.long 0x0 31. "MR31,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 30. "MR30,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 29. "MR29,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 28. "MR28,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 27. "MR27,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 26. "MR26,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 25. "MR25,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 24. "MR24,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 23. "MR23,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 22. "MR22,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 21. "MR21,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 20. "MR20,Rising trigger event configuration bit" "0,1" newline bitfld.long 0x0 19. "MR19,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 18. "MR18,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 17. "MR17,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 16. "MR16,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 15. "MR15,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 14. "MR14,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 13. "MR13,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 12. "MR12,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 11. "MR11,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 10. "MR10,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 9. "MR9,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 8. "MR8,Rising trigger event configuration bit" "0,1" newline bitfld.long 0x0 7. "MR7,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 6. "MR6,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 5. "MR5,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 4. "MR4,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 3. "MR3,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 2. "MR2,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 1. "MR1,Rising trigger event configuration bit" "0,1" bitfld.long 0x0 0. "MR0,Rising trigger event configuration bit" "0,1" line.long 0x4 "CPUEMR1,EXTI event mask register" bitfld.long 0x4 31. "MR31,CPU Event mask on Event input" "0,1" bitfld.long 0x4 30. "MR30,CPU Event mask on Event input" "0,1" bitfld.long 0x4 29. "MR29,CPU Event mask on Event input" "0,1" bitfld.long 0x4 28. "MR28,CPU Event mask on Event input" "0,1" bitfld.long 0x4 27. "MR27,CPU Event mask on Event input" "0,1" bitfld.long 0x4 26. "MR26,CPU Event mask on Event input" "0,1" bitfld.long 0x4 25. "MR25,CPU Event mask on Event input" "0,1" bitfld.long 0x4 24. "MR24,CPU Event mask on Event input" "0,1" bitfld.long 0x4 23. "MR23,CPU Event mask on Event input" "0,1" bitfld.long 0x4 22. "MR22,CPU Event mask on Event input" "0,1" bitfld.long 0x4 21. "MR21,CPU Event mask on Event input" "0,1" bitfld.long 0x4 20. "MR20,CPU Event mask on Event input" "0,1" newline bitfld.long 0x4 19. "MR19,CPU Event mask on Event input" "0,1" bitfld.long 0x4 18. "MR18,CPU Event mask on Event input" "0,1" bitfld.long 0x4 17. "MR17,CPU Event mask on Event input" "0,1" bitfld.long 0x4 16. "MR16,CPU Event mask on Event input" "0,1" bitfld.long 0x4 15. "MR15,CPU Event mask on Event input" "0,1" bitfld.long 0x4 14. "MR14,CPU Event mask on Event input" "0,1" bitfld.long 0x4 13. "MR13,CPU Event mask on Event input" "0,1" bitfld.long 0x4 12. "MR12,CPU Event mask on Event input" "0,1" bitfld.long 0x4 11. "MR11,CPU Event mask on Event input" "0,1" bitfld.long 0x4 10. "MR10,CPU Event mask on Event input" "0,1" bitfld.long 0x4 9. "MR9,CPU Event mask on Event input" "0,1" bitfld.long 0x4 8. "MR8,CPU Event mask on Event input" "0,1" newline bitfld.long 0x4 7. "MR7,CPU Event mask on Event input" "0,1" bitfld.long 0x4 6. "MR6,CPU Event mask on Event input" "0,1" bitfld.long 0x4 5. "MR5,CPU Event mask on Event input" "0,1" bitfld.long 0x4 4. "MR4,CPU Event mask on Event input" "0,1" bitfld.long 0x4 3. "MR3,CPU Event mask on Event input" "0,1" bitfld.long 0x4 2. "MR2,CPU Event mask on Event input" "0,1" bitfld.long 0x4 1. "MR1,CPU Event mask on Event input" "0,1" bitfld.long 0x4 0. "MR0,CPU Event mask on Event input" "0,1" line.long 0x8 "CPUPR1,EXTI pending register" bitfld.long 0x8 21. "PR21,CPU Event mask on Event input" "0,1" bitfld.long 0x8 20. "PR20,CPU Event mask on Event input" "0,1" bitfld.long 0x8 19. "PR19,CPU Event mask on Event input" "0,1" bitfld.long 0x8 18. "PR18,CPU Event mask on Event input" "0,1" bitfld.long 0x8 17. "PR17,CPU Event mask on Event input" "0,1" bitfld.long 0x8 16. "PR16,CPU Event mask on Event input" "0,1" bitfld.long 0x8 15. "PR15,CPU Event mask on Event input" "0,1" bitfld.long 0x8 14. "PR14,CPU Event mask on Event input" "0,1" bitfld.long 0x8 13. "PR13,CPU Event mask on Event input" "0,1" bitfld.long 0x8 12. "PR12,CPU Event mask on Event input" "0,1" bitfld.long 0x8 11. "PR11,CPU Event mask on Event input" "0,1" bitfld.long 0x8 10. "PR10,CPU Event mask on Event input" "0,1" newline bitfld.long 0x8 9. "PR9,CPU Event mask on Event input" "0,1" bitfld.long 0x8 8. "PR8,CPU Event mask on Event input" "0,1" bitfld.long 0x8 7. "PR7,CPU Event mask on Event input" "0,1" bitfld.long 0x8 6. "PR6,CPU Event mask on Event input" "0,1" bitfld.long 0x8 5. "PR5,CPU Event mask on Event input" "0,1" bitfld.long 0x8 4. "PR4,CPU Event mask on Event input" "0,1" bitfld.long 0x8 3. "PR3,CPU Event mask on Event input" "0,1" bitfld.long 0x8 2. "PR2,CPU Event mask on Event input" "0,1" bitfld.long 0x8 1. "PR1,CPU Event mask on Event input" "0,1" bitfld.long 0x8 0. "PR0,CPU Event mask on Event input" "0,1" group.long 0x90++0x7 line.long 0x0 "CPUIMR2,EXTI interrupt mask register" bitfld.long 0x0 31. "MR31,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 30. "MR30,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 29. "MR29,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 28. "MR28,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 27. "MR27,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 26. "MR26,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 25. "MR25,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 24. "MR24,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 23. "MR23,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 22. "MR22,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 21. "MR21,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 20. "MR20,CPU Interrupt Mask on Direct Event input" "0,1" newline bitfld.long 0x0 19. "MR19,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 18. "MR18,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 17. "MR17,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 16. "MR16,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 15. "MR15,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 14. "MR14,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 12. "MR12,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 11. "MR11,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 10. "MR10,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 9. "MR9,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 8. "MR8,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 7. "MR7,CPU Interrupt Mask on Direct Event input" "0,1" newline bitfld.long 0x0 6. "MR6,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 5. "MR5,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 4. "MR4,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 3. "MR3,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 2. "MR2,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 1. "MR1,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 0. "MR0,CPU Interrupt Mask on Direct Event input" "0,1" line.long 0x4 "CPUEMR2,EXTI event mask register" bitfld.long 0x4 31. "MR63,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 30. "MR62,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 29. "MR61,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 28. "MR60,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 27. "MR59,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 26. "MR58,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 25. "MR57,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 24. "MR56,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 23. "MR55,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 22. "MR54,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 21. "MR53,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 20. "MR52,CPU Interrupt Mask on Direct Event input" "0,1" newline bitfld.long 0x4 19. "MR51,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 18. "MR50,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 17. "MR49,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 16. "MR48,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 15. "MR47,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 14. "MR46,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 12. "MR44,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 11. "MR43,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 10. "MR42,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 9. "MR41,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 8. "MR40,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 7. "MR39,CPU Interrupt Mask on Direct Event input" "0,1" newline bitfld.long 0x4 6. "MR38,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 5. "MR37,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 4. "MR36,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 3. "MR35,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 2. "MR34,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 1. "MR33,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x4 0. "MR32,CPU Interrupt Mask on Direct Event input" "0,1" rgroup.long 0x98++0x3 line.long 0x0 "CPUPR2,EXTI pending register" bitfld.long 0x0 19. "PR51,Configurable event inputs x+32 Pending" "0,1" bitfld.long 0x0 17. "PR49,Configurable event inputs x+32 Pending" "0,1" rgroup.long 0xA0++0xB line.long 0x0 "CPUIMR3,EXTI interrupt mask register" bitfld.long 0x0 24. "MR88,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 23. "MR87,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 22. "MR86,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 21. "MR85,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 20. "MR84,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 18. "MR82,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 16. "MR80,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 15. "MR79,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 14. "MR78,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 13. "MR77,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 12. "MR76,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 11. "MR75,CPU Interrupt Mask on Direct Event input" "0,1" newline bitfld.long 0x0 10. "MR74,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 9. "MR73,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 8. "MR72,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 7. "MR71,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 6. "MR70,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 5. "MR69,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 4. "MR68,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 3. "MR67,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 2. "MR66,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 1. "MR65,CPU Interrupt Mask on Direct Event input" "0,1" bitfld.long 0x0 0. "MR64,CPU Interrupt Mask on Direct Event input" "0,1" line.long 0x4 "CPUEMR3,EXTI event mask register" bitfld.long 0x4 24. "MR88,CPU Event mask on Event input" "0,1" bitfld.long 0x4 23. "MR87,CPU Event mask on Event input" "0,1" bitfld.long 0x4 22. "MR86,CPU Event mask on Event input" "0,1" bitfld.long 0x4 21. "MR85,CPU Event mask on Event input" "0,1" bitfld.long 0x4 20. "MR84,CPU Event mask on Event input" "0,1" bitfld.long 0x4 18. "MR82,CPU Event mask on Event input" "0,1" bitfld.long 0x4 16. "MR80,CPU Event mask on Event input" "0,1" bitfld.long 0x4 15. "MR79,CPU Event mask on Event input" "0,1" bitfld.long 0x4 14. "MR78,CPU Event mask on Event input" "0,1" bitfld.long 0x4 13. "MR77,CPU Event mask on Event input" "0,1" bitfld.long 0x4 12. "MR76,CPU Event mask on Event input" "0,1" bitfld.long 0x4 11. "MR75,CPU Event mask on Event input" "0,1" newline bitfld.long 0x4 10. "MR74,CPU Event mask on Event input" "0,1" bitfld.long 0x4 9. "MR73,CPU Event mask on Event input" "0,1" bitfld.long 0x4 8. "MR72,CPU Event mask on Event input" "0,1" bitfld.long 0x4 7. "MR71,CPU Event mask on Event input" "0,1" bitfld.long 0x4 6. "MR70,CPU Event mask on Event input" "0,1" bitfld.long 0x4 5. "MR69,CPU Event mask on Event input" "0,1" bitfld.long 0x4 4. "MR68,CPU Event mask on Event input" "0,1" bitfld.long 0x4 3. "MR67,CPU Event mask on Event input" "0,1" bitfld.long 0x4 2. "MR66,CPU Event mask on Event input" "0,1" bitfld.long 0x4 1. "MR65,CPU Event mask on Event input" "0,1" bitfld.long 0x4 0. "MR64,CPU Event mask on Event input" "0,1" line.long 0x8 "CPUPR3,EXTI pending register" bitfld.long 0x8 22. "PR86,Configurable event inputs x+64 Pending" "0,1" bitfld.long 0x8 21. "PR85,Configurable event inputs x+64 Pending" "0,1" bitfld.long 0x8 20. "PR84,Configurable event inputs x+64 Pending" "0,1" bitfld.long 0x8 18. "PR82,Configurable event inputs x+64 Pending" "0,1" tree.end tree "FDCAN (Controller Area Network)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) tree "CAN_CCU (CCU registers)" base ad:0x4000A800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) group.long 0x0++0x17 line.long 0x0 "CREL,Clock Calibration Unit Core Release" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CCFG,Calibration Configuration" bitfld.long 0x4 31. "SWR,Software Reset" "0,1" hexmask.long.byte 0x4 16.--19. 1. "CDIV,Clock Divider" newline hexmask.long.byte 0x4 8.--15. 1. "OCPM,Oscillator Clock Periods" bitfld.long 0x4 7. "CFL,Calibration Field Length" "0,1" newline bitfld.long 0x4 6. "BCC,Bypass Clock Calibration" "0,1" hexmask.long.byte 0x4 0.--4. 1. "TQBT,Time Quanta per Bit Time" line.long 0x8 "CSTAT,Calibration Status Register" bitfld.long 0x8 30.--31. "CALS,Calibration State" "0,1,2,3" hexmask.long.word 0x8 18.--28. 1. "TQC,Time Quanta Counter" newline hexmask.long.tbyte 0x8 0.--17. 1. "OCPC,Oscillator Clock Period" line.long 0xC "CWD,Calibration Watchdog Register" hexmask.long.word 0xC 16.--31. 1. "WDV,WDV" hexmask.long.word 0xC 0.--15. 1. "WDC,WDC" line.long 0x10 "IR,Clock Calibration Unit Interrupt" bitfld.long 0x10 1. "CSC,Calibration State Changed" "0,1" bitfld.long 0x10 0. "CWE,Calibration Watchdog Event" "0,1" line.long 0x14 "IE,Clock Calibration Unit Interrupt Enable" bitfld.long 0x14 1. "CSCE,Calibration State Changed" "0,1" bitfld.long 0x14 0. "CWEE,Calibration Watchdog Event" "0,1" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" newline hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" newline hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" newline hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" newline hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" newline bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" newline bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" newline bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" newline bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" newline bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" newline bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" newline hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" newline bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" newline bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" newline bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" newline bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0x3 line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" newline bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" newline bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" newline bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" newline bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" newline bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" newline bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" newline bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" group.long 0x54++0x3 line.long 0x0 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x0 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDE,Protocol Error in Data Phase" "0,1" newline bitfld.long 0x0 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIE,Watchdog Interrupt Enable" "0,1" newline bitfld.long 0x0 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x0 24. "EWE,Warning Status Enable" "0,1" newline bitfld.long 0x0 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x0 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECE,Bit Error Corrected Interrupt" "0,1" newline bitfld.long 0x0 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOE,Timeout Occurred Enable" "0,1" newline bitfld.long 0x0 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSWE,Timestamp Wraparound" "0,1" newline bitfld.long 0x0 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x0 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNE,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x0 10. "TCFE,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPME,High Priority Message" "0,1" newline bitfld.long 0x0 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x0 4. "RF1NE,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" newline bitfld.long 0x0 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 0. "RF0NE,Rx FIFO 0 New Message" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x0 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDL,Protocol Error in Data Phase" "0,1" newline bitfld.long 0x0 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIL,Watchdog Interrupt Line" "0,1" newline bitfld.long 0x0 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EWL,Warning Status Interrupt" "0,1" newline bitfld.long 0x0 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x0 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x0 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECL,Bit Error Corrected Interrupt" "0,1" newline bitfld.long 0x0 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOL,Timeout Occurred Interrupt" "0,1" newline bitfld.long 0x0 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x0 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" newline bitfld.long 0x0 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x0 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x0 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" newline bitfld.long 0x0 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x0 10. "TCFL,Transmission Cancellation Finished" "0,1" newline bitfld.long 0x0 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x0 8. "HPML,High Priority Message Interrupt" "0,1" newline bitfld.long 0x0 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x0 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x0 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" newline bitfld.long 0x0 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x0 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" newline bitfld.long 0x0 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" newline bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" newline bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" newline bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" newline bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" newline bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" newline bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" newline bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" newline bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" newline bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" newline bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" newline bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" newline bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" newline bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" newline bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" newline bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" newline bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" newline bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" newline bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" newline bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" newline bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" newline bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" newline bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" newline bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" newline bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" newline bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" newline bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" newline hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" newline hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" newline bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" newline hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 0 Data Field Size:" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 1 Data Field Size:" "0,1,2,3,4,5,6,7" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" newline hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" newline hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" newline hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." newline hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" newline hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" newline bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" newline bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" newline bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" newline bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." newline hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" newline bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" newline bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" newline bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" newline bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" newline bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" newline hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" newline bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" newline bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" newline bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" newline bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" newline bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" newline bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" newline bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" newline bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" newline bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" newline bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" newline bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" newline bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" newline bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" newline bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" newline bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" newline bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" newline bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" newline bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" newline bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" newline bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" newline bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" newline bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" newline bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" newline bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "FDCAN1" base ad:0x4000A000 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0xB line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x8 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x8 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 0 Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 1 Data Field Size:" "0,1,2,3,4,5,6,7" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2F line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" line.long 0x2C "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x2C 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x2C 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x2C 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x2C 28. "WFE,Wait for Event" "0,1" bitfld.long 0x2C 27. "GSI,Gap Started Indicator." "0,1" bitfld.long 0x2C 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x2C 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x2C 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x2C 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x2C 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x2C 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x2C 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x2C 0.--1. "EL,Error Level" "0,1,2,3" rgroup.long 0x130++0x13 line.long 0x0 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x0 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x4 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x4 16.--31. 1. "GT,Global Time" hexmask.long.word 0x4 0.--15. 1. "LT,Local Time" line.long 0x8 "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0x8 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0x8 0.--15. 1. "CT,Cycle Time" line.long 0xC "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0xC 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0xC 0.--5. 1. "CT,Cycle Count Value" line.long 0x10 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x10 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end tree "FDCAN2" base ad:0x4000A400 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0xB line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x8 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x8 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 0 Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 1 Data Field Size:" "0,1,2,3,4,5,6,7" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2F line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" line.long 0x2C "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x2C 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x2C 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x2C 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x2C 28. "WFE,Wait for Event" "0,1" bitfld.long 0x2C 27. "GSI,Gap Started Indicator." "0,1" bitfld.long 0x2C 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x2C 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x2C 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x2C 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x2C 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x2C 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x2C 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x2C 0.--1. "EL,Error Level" "0,1,2,3" rgroup.long 0x130++0x13 line.long 0x0 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x0 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x4 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x4 16.--31. 1. "GT,Global Time" hexmask.long.word 0x4 0.--15. 1. "LT,Local Time" line.long 0x8 "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0x8 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0x8 0.--15. 1. "CT,Cycle Time" line.long 0xC "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0xC 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0xC 0.--5. 1. "CT,Cycle Count Value" line.long 0x10 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x10 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "FDCAN3" base ad:0x4000D400 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0xB line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x8 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x8 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 0 Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 1 Data Field Size:" "0,1,2,3,4,5,6,7" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2F line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" line.long 0x2C "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x2C 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x2C 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x2C 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x2C 28. "WFE,Wait for Event" "0,1" bitfld.long 0x2C 27. "GSI,Gap Started Indicator." "0,1" bitfld.long 0x2C 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x2C 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x2C 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x2C 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x2C 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x2C 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x2C 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x2C 0.--1. "EL,Error Level" "0,1,2,3" rgroup.long 0x130++0x13 line.long 0x0 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x0 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x4 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x4 16.--31. 1. "GT,Global Time" hexmask.long.word 0x4 0.--15. 1. "LT,Local Time" line.long 0x8 "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0x8 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0x8 0.--15. 1. "CT,Cycle Time" line.long 0xC "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0xC 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0xC 0.--5. 1. "CT,Cycle Count Value" line.long 0x10 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x10 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif sif (cpuis("STM32H7A3*")) tree "FDCAN" base ad:0x4000A400 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0x3 line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" group.long 0x54++0x3 line.long 0x0 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x0 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x0 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x0 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x0 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x0 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x0 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x0 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x0 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x0 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPME,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x0 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x0 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 0. "RF0NE,Rx FIFO 0 New Message" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x0 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x0 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x0 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x0 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x0 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x0 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x0 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x0 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x0 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x0 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x0 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x0 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x0 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x0 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x0 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x0 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x0 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x0 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x0 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 0 Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 1 Data Field Size:" "0,1,2,3,4,5,6,7" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif sif (cpuis("STM32H7A3*")) tree "TT_FDCAN" base ad:0x4000A000 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Last Error Code" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0x3 line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" group.long 0x54++0x3 line.long 0x0 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x0 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x0 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x0 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x0 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x0 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x0 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x0 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x0 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x0 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPME,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x0 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x0 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 0. "RF0NE,Rx FIFO 0 New Message" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x0 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x0 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x0 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x0 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x0 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x0 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x0 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x0 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x0 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x0 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x0 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x0 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x0 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x0 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x0 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x0 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x0 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x0 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x0 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 0 Data Field Size:" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 1 Data Field Size:" "0,1,2,3,4,5,6,7" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size:" "0,1,2,3,4,5,6,7" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif sif (cpuis("STM32H7B0*")) tree "FDCAN" base ad:0x4000A400 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" hexmask.long.byte 0x4 8.--11. 1. "DLEC,Data Last Error Code" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "LEC,Last Error Code" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0xB line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x8 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x8 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" hexmask.long.byte 0x1C 8.--11. 1. "RBDS,Rx Buffer Data Field Size:" hexmask.long.byte 0x1C 4.--7. 1. "F1DS,Rx FIFO 0 Data Field Size:" hexmask.long.byte 0x1C 0.--3. 1. "F0DS,Rx FIFO 1 Data Field Size:" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" hexmask.long.byte 0x0 0.--3. 1. "TBDS,Tx Buffer Data Field Size:" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" hexmask.long.byte 0x8 5.--8. 1. "LDSDL,LD of Synchronization Deviation" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" hexmask.long.byte 0x0 24.--27. 1. "TMP,Time Master Priority" bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif sif (cpuis("STM32H7B0*")) tree "TT_FDCAN" base ad:0x4000A000 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" hexmask.long.byte 0x4 8.--11. 1. "DLEC,Data Last Error Code" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "LEC,Last Error Code" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0xB line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0x4 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x4 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x4 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x4 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x4 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x4 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x4 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x4 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x4 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x4 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x4 8. "HPME,High Priority Message" "0,1" bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message" "0,1" line.long 0x8 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x8 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x8 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x8 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x8 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x8 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" hexmask.long.byte 0x1C 8.--11. 1. "RBDS,Rx Buffer Data Field Size:" hexmask.long.byte 0x1C 4.--7. 1. "F1DS,Rx FIFO 0 Data Field Size:" hexmask.long.byte 0x1C 0.--3. 1. "F0DS,Rx FIFO 1 Data Field Size:" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" hexmask.long.byte 0x0 0.--3. 1. "TBDS,Tx Buffer Data Field Size:" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" hexmask.long.byte 0x8 5.--8. 1. "LDSDL,LD of Synchronization Deviation" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" hexmask.long.byte 0x0 24.--27. 1. "TMP,Time Master Priority" bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x100++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end tree "CAN_CCU (CCU registers)" base ad:0x4000A800 group.long 0x0++0x17 line.long 0x0 "CREL,Clock Calibration Unit Core Release" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "CCFG,Calibration Configuration" bitfld.long 0x4 31. "SWR,Software Reset" "0,1" hexmask.long.byte 0x4 16.--19. 1. "CDIV,Clock Divider" hexmask.long.byte 0x4 8.--15. 1. "OCPM,Oscillator Clock Periods" bitfld.long 0x4 7. "CFL,Calibration Field Length" "0,1" bitfld.long 0x4 6. "BCC,Bypass Clock Calibration" "0,1" hexmask.long.byte 0x4 0.--4. 1. "TQBT,Time Quanta per Bit Time" line.long 0x8 "CSTAT,Calibration Status Register" bitfld.long 0x8 30.--31. "CALS,Calibration State" "0,1,2,3" hexmask.long.word 0x8 18.--28. 1. "TQC,Time Quanta Counter" hexmask.long.tbyte 0x8 0.--17. 1. "OCPC,Oscillator Clock Period" line.long 0xC "CWD,Calibration Watchdog Register" hexmask.long.word 0xC 16.--31. 1. "WDV,WDV" hexmask.long.word 0xC 0.--15. 1. "WDC,WDC" line.long 0x10 "IR,Clock Calibration Unit Interrupt" bitfld.long 0x10 1. "CSC,Calibration State Changed" "0,1" bitfld.long 0x10 0. "CWE,Calibration Watchdog Event" "0,1" line.long 0x14 "IE,Clock Calibration Unit Interrupt Enable" bitfld.long 0x14 1. "CSCE,Calibration State Changed" "0,1" bitfld.long 0x14 0. "CWEE,Calibration Watchdog Event" "0,1" tree.end endif sif (cpuis("STM32H7B3*")) tree "CAN_CCU (FDCAN1)" base ad:0x4000A800 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" hexmask.long.byte 0x4 8.--11. 1. "DLEC,Data Last Error Code" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "LEC,Last Error Code" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0x3 line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" group.long 0x54++0x3 line.long 0x0 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x0 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x0 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x0 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x0 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x0 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x0 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x0 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x0 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x0 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPME,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x0 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x0 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 0. "RF0NE,Rx FIFO 0 New Message" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x0 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x0 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x0 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x0 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x0 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x0 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x0 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x0 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x0 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x0 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x0 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x0 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x0 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x0 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x0 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x0 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x0 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x0 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x0 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" hexmask.long.byte 0x1C 8.--11. 1. "RBDS,Rx Buffer Data Field Size:" hexmask.long.byte 0x1C 4.--7. 1. "F1DS,Rx FIFO 0 Data Field Size:" hexmask.long.byte 0x1C 0.--3. 1. "F0DS,Rx FIFO 1 Data Field Size:" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" hexmask.long.byte 0x0 0.--3. 1. "TBDS,Tx Buffer Data Field Size:" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" hexmask.long.byte 0x8 5.--8. 1. "LDSDL,LD of Synchronization Deviation" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" hexmask.long.byte 0x0 24.--27. 1. "TMP,Time Master Priority" bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif sif (cpuis("STM32H7B3*")) tree "FDCAN" base ad:0x4000A400 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" hexmask.long.byte 0x4 8.--11. 1. "DLEC,Data Last Error Code" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "LEC,Last Error Code" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0x3 line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" group.long 0x54++0x3 line.long 0x0 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x0 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x0 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x0 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x0 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x0 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x0 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x0 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x0 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x0 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPME,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x0 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x0 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 0. "RF0NE,Rx FIFO 0 New Message" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x0 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x0 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x0 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x0 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x0 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x0 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x0 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x0 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x0 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x0 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x0 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x0 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x0 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x0 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x0 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x0 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x0 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x0 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x0 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" hexmask.long.byte 0x1C 8.--11. 1. "RBDS,Rx Buffer Data Field Size:" hexmask.long.byte 0x1C 4.--7. 1. "F1DS,Rx FIFO 0 Data Field Size:" hexmask.long.byte 0x1C 0.--3. 1. "F0DS,Rx FIFO 1 Data Field Size:" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" hexmask.long.byte 0x0 0.--3. 1. "TBDS,Tx Buffer Data Field Size:" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" hexmask.long.byte 0x8 5.--8. 1. "LDSDL,LD of Synchronization Deviation" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" hexmask.long.byte 0x0 24.--27. 1. "TMP,Time Master Priority" bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif sif (cpuis("STM32H7B3*")) tree "TT_FDCAN" base ad:0x4000A000 rgroup.long 0x0++0x7 line.long 0x0 "FDCAN_CREL,FDCAN Core Release Register" hexmask.long.byte 0x0 28.--31. 1. "REL,Core release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core release" hexmask.long.byte 0x0 16.--19. 1. "YEAR,Timestamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Timestamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Timestamp Day" line.long 0x4 "FDCAN_ENDN,FDCAN Core Release Register" hexmask.long 0x4 0.--31. 1. "ETV,Endiannes Test Value" rgroup.long 0xC++0xB line.long 0x0 "FDCAN_DBTP,FDCAN Data Bit Timing and Prescaler" bitfld.long 0x0 23. "TDC,Transceiver Delay" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data BIt Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment after sample" hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization Jump Width" line.long 0x4 "FDCAN_TEST,FDCAN Test Register" bitfld.long 0x4 7. "RX,Control of Transmit Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Loop Back mode" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back mode" "0,1" line.long 0x8 "FDCAN_RWD,FDCAN RAM Watchdog Register" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration" group.long 0x18++0x17 line.long 0x0 "FDCAN_CCCR,FDCAN CC Control Register" bitfld.long 0x0 15. "NISO,Non ISO Operation" "0,1" bitfld.long 0x0 14. "TXP,TXP" "0,1" bitfld.long 0x0 13. "EFBI,Edge Filtering during Bus" "0,1" bitfld.long 0x0 12. "PXHD,Protocol Exception Handling" "0,1" bitfld.long 0x0 9. "BSE,FDCAN Bit Rate Switching" "0,1" bitfld.long 0x0 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0x0 7. "TEST,Test Mode Enable" "0,1" bitfld.long 0x0 6. "DAR,Disable Automatic" "0,1" newline bitfld.long 0x0 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0x0 4. "CSR,Clock Stop Request" "0,1" bitfld.long 0x0 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0x0 2. "ASM,ASM Restricted Operation" "0,1" bitfld.long 0x0 1. "CCE,Configuration Change" "0,1" bitfld.long 0x0 0. "INIT,Initialization" "0,1" line.long 0x4 "FDCAN_NBTP,FDCAN Nominal Bit Timing and Prescaler" hexmask.long.byte 0x4 25.--31. 1. "NSJW,NSJW: Nominal (Re)Synchronization Jump" hexmask.long.word 0x4 16.--24. 1. "NBRP,Bit Rate Prescaler" hexmask.long.byte 0x4 8.--15. 1. "NTSEG1,Nominal Time segment before sample" hexmask.long.byte 0x4 0.--6. 1. "TSEG2,Nominal Time segment after sample" line.long 0x8 "FDCAN_TSCC,FDCAN Timestamp Counter Configuration" hexmask.long.byte 0x8 16.--19. 1. "TCP,Timestamp Counter" bitfld.long 0x8 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0xC "FDCAN_TSCV,FDCAN Timestamp Counter Value" hexmask.long.word 0xC 0.--15. 1. "TSC,Timestamp Counter" line.long 0x10 "FDCAN_TOCC,FDCAN Timeout Counter Configuration" hexmask.long.word 0x10 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x10 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x10 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x14 "FDCAN_TOCV,FDCAN Timeout Counter Value" hexmask.long.word 0x14 0.--15. 1. "TOC,Timeout Counter" group.long 0x40++0x7 line.long 0x0 "FDCAN_ECR,FDCAN Error Counter Register" hexmask.long.byte 0x0 16.--23. 1. "CEL,AN Error Logging" bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "TREC,Receive Error Counter" hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "FDCAN_PSR,FDCAN Protocol Status Register" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "REDL,Received FDCAN Message" "0,1" bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN" "0,1" hexmask.long.byte 0x4 8.--11. 1. "DLEC,Data Last Error Code" bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" newline bitfld.long 0x4 5. "EP,Error Passive" "0,1" bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "LEC,Last Error Code" rgroup.long 0x48++0x3 line.long 0x0 "FDCAN_TDCR,FDCAN Transmitter Delay Compensation" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter" rgroup.long 0x50++0x3 line.long 0x0 "FDCAN_IR,FDCAN Interrupt Register" bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit" "0,1" bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EW,Warning Status" "0,1" bitfld.long 0x0 23. "EP,Error Passive" "0,1" bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1" newline bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx" "0,1" bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1" bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark" "0,1" bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x0 11. "TEF,Tx FIFO Empty" "0,1" bitfld.long 0x0 10. "TCF,Transmission Cancellation" "0,1" bitfld.long 0x0 9. "TC,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPM,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark" "0,1" bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1" newline bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Full" "0,1" bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1" group.long 0x54++0x3 line.long 0x0 "FDCAN_IE,FDCAN Interrupt Enable" bitfld.long 0x0 29. "ARAE,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDE,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAE,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0x0 25. "BOE,Bus_Off Status Enable" "0,1" bitfld.long 0x0 24. "EWE,Warning Status Enable" "0,1" bitfld.long 0x0 23. "EPE,Error Passive Enable" "0,1" bitfld.long 0x0 22. "ELOE,Error Logging Overflow" "0,1" newline bitfld.long 0x0 21. "BEUE,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECE,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXE,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOE,Timeout Occurred Enable" "0,1" bitfld.long 0x0 17. "MRAFE,Message RAM Access Failure" "0,1" bitfld.long 0x0 16. "TSWE,Timestamp Wraparound" "0,1" bitfld.long 0x0 15. "TEFLE,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 14. "TEFFE,Tx Event FIFO Full Enable" "0,1" newline bitfld.long 0x0 13. "TEFWE,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNE,Tx Event FIFO New Entry" "0,1" bitfld.long 0x0 11. "TEFE,Tx FIFO Empty Enable" "0,1" bitfld.long 0x0 10. "TCFE,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCE,Transmission Completed" "0,1" bitfld.long 0x0 8. "HPME,High Priority Message" "0,1" bitfld.long 0x0 7. "RF1LE,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x0 6. "RF1FE,Rx FIFO 1 Watermark Reached" "0,1" newline bitfld.long 0x0 5. "RF1WE,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x0 4. "RF1NE,Rx FIFO 1 New Message" "0,1" bitfld.long 0x0 3. "RF0LE,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 2. "RF0FE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 1. "RF0WE,Rx FIFO 0 Full Enable" "0,1" bitfld.long 0x0 0. "RF0NE,Rx FIFO 0 New Message" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "FDCAN_ILS,FDCAN Interrupt Line Select" bitfld.long 0x0 29. "ARAL,Access to Reserved Address" "0,1" bitfld.long 0x0 28. "PEDL,Protocol Error in Data Phase" "0,1" bitfld.long 0x0 27. "PEAL,Protocol Error in Arbitration Phase" "0,1" bitfld.long 0x0 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x0 25. "BOL,Bus_Off Status" "0,1" bitfld.long 0x0 24. "EWL,Warning Status Interrupt" "0,1" bitfld.long 0x0 23. "EPL,Error Passive Interrupt" "0,1" bitfld.long 0x0 22. "ELOL,Error Logging Overflow Interrupt" "0,1" newline bitfld.long 0x0 21. "BEUL,Bit Error Uncorrected Interrupt" "0,1" bitfld.long 0x0 20. "BECL,Bit Error Corrected Interrupt" "0,1" bitfld.long 0x0 19. "DRXL,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x0 18. "TOOL,Timeout Occurred Interrupt" "0,1" bitfld.long 0x0 17. "MRAFL,Message RAM Access Failure Interrupt" "0,1" bitfld.long 0x0 16. "TSWL,Timestamp Wraparound Interrupt" "0,1" bitfld.long 0x0 15. "TEFLL,Tx Event FIFO Element Lost Interrupt" "0,1" bitfld.long 0x0 14. "TEFFL,Tx Event FIFO Full Interrupt" "0,1" newline bitfld.long 0x0 13. "TEFWL,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x0 12. "TEFNL,Tx Event FIFO New Entry Interrupt" "0,1" bitfld.long 0x0 11. "TEFL,Tx FIFO Empty Interrupt" "0,1" bitfld.long 0x0 10. "TCFL,Transmission Cancellation Finished" "0,1" bitfld.long 0x0 9. "TCL,Transmission Completed Interrupt" "0,1" bitfld.long 0x0 8. "HPML,High Priority Message Interrupt" "0,1" bitfld.long 0x0 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt" "0,1" bitfld.long 0x0 6. "RF1FL,Rx FIFO 1 Full Interrupt" "0,1" newline bitfld.long 0x0 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 4. "RF1NL,Rx FIFO 1 New Message Interrupt" "0,1" bitfld.long 0x0 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt" "0,1" bitfld.long 0x0 2. "RF0FL,Rx FIFO 0 Full Interrupt" "0,1" bitfld.long 0x0 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt" "0,1" bitfld.long 0x0 0. "RF0NL,Rx FIFO 0 New Message Interrupt" "0,1" group.long 0x5C++0x3 line.long 0x0 "FDCAN_ILE,FDCAN Interrupt Line Enable" bitfld.long 0x0 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x0 0. "EINT0,Enable Interrupt Line 0" "0,1" group.long 0x80++0xB line.long 0x0 "FDCAN_GFC,FDCAN Global Filter Configuration" bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames" "0,1,2,3" bitfld.long 0x0 1. "RRFS,Reject Remote Frames" "0,1" bitfld.long 0x0 0. "RRFE,Reject Remote Frames" "0,1" line.long 0x4 "FDCAN_SIDFC,FDCAN Standard ID Filter Configuration" hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard" hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start" line.long 0x8 "FDCAN_XIDFC,FDCAN Extended ID Filter Configuration" hexmask.long.byte 0x8 16.--23. 1. "LSE,List Size Extended" hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Standard Start" group.long 0x90++0x3 line.long 0x0 "FDCAN_XIDAM,FDCAN Extended ID and Mask" hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x94++0xB line.long 0x0 "FDCAN_HPMS,FDCAN High Priority Message Status" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" line.long 0x4 "FDCAN_NDAT1,FDCAN New Data 1 Register" bitfld.long 0x4 31. "ND31,New data" "0,1" bitfld.long 0x4 30. "ND30,New data" "0,1" bitfld.long 0x4 29. "ND29,New data" "0,1" bitfld.long 0x4 28. "ND28,New data" "0,1" bitfld.long 0x4 27. "ND27,New data" "0,1" bitfld.long 0x4 26. "ND26,New data" "0,1" bitfld.long 0x4 25. "ND25,New data" "0,1" bitfld.long 0x4 24. "ND24,New data" "0,1" newline bitfld.long 0x4 23. "ND23,New data" "0,1" bitfld.long 0x4 22. "ND22,New data" "0,1" bitfld.long 0x4 21. "ND21,New data" "0,1" bitfld.long 0x4 20. "ND20,New data" "0,1" bitfld.long 0x4 19. "ND19,New data" "0,1" bitfld.long 0x4 18. "ND18,New data" "0,1" bitfld.long 0x4 17. "ND17,New data" "0,1" bitfld.long 0x4 16. "ND16,New data" "0,1" newline bitfld.long 0x4 15. "ND15,New data" "0,1" bitfld.long 0x4 14. "ND14,New data" "0,1" bitfld.long 0x4 13. "ND13,New data" "0,1" bitfld.long 0x4 12. "ND12,New data" "0,1" bitfld.long 0x4 11. "ND11,New data" "0,1" bitfld.long 0x4 10. "ND10,New data" "0,1" bitfld.long 0x4 9. "ND9,New data" "0,1" bitfld.long 0x4 8. "ND8,New data" "0,1" newline bitfld.long 0x4 7. "ND7,New data" "0,1" bitfld.long 0x4 6. "ND6,New data" "0,1" bitfld.long 0x4 5. "ND5,New data" "0,1" bitfld.long 0x4 4. "ND4,New data" "0,1" bitfld.long 0x4 3. "ND3,New data" "0,1" bitfld.long 0x4 2. "ND2,New data" "0,1" bitfld.long 0x4 1. "ND1,New data" "0,1" bitfld.long 0x4 0. "ND0,New data" "0,1" line.long 0x8 "FDCAN_NDAT2,FDCAN New Data 2 Register" bitfld.long 0x8 31. "ND63,New data" "0,1" bitfld.long 0x8 30. "ND62,New data" "0,1" bitfld.long 0x8 29. "ND61,New data" "0,1" bitfld.long 0x8 28. "ND60,New data" "0,1" bitfld.long 0x8 27. "ND59,New data" "0,1" bitfld.long 0x8 26. "ND58,New data" "0,1" bitfld.long 0x8 25. "ND57,New data" "0,1" bitfld.long 0x8 24. "ND56,New data" "0,1" newline bitfld.long 0x8 23. "ND55,New data" "0,1" bitfld.long 0x8 22. "ND54,New data" "0,1" bitfld.long 0x8 21. "ND53,New data" "0,1" bitfld.long 0x8 20. "ND52,New data" "0,1" bitfld.long 0x8 19. "ND51,New data" "0,1" bitfld.long 0x8 18. "ND50,New data" "0,1" bitfld.long 0x8 17. "ND49,New data" "0,1" bitfld.long 0x8 16. "ND48,New data" "0,1" newline bitfld.long 0x8 15. "ND47,New data" "0,1" bitfld.long 0x8 14. "ND46,New data" "0,1" bitfld.long 0x8 13. "ND45,New data" "0,1" bitfld.long 0x8 12. "ND44,New data" "0,1" bitfld.long 0x8 11. "ND43,New data" "0,1" bitfld.long 0x8 10. "ND42,New data" "0,1" bitfld.long 0x8 9. "ND41,New data" "0,1" bitfld.long 0x8 8. "ND40,New data" "0,1" newline bitfld.long 0x8 7. "ND39,New data" "0,1" bitfld.long 0x8 6. "ND38,New data" "0,1" bitfld.long 0x8 5. "ND37,New data" "0,1" bitfld.long 0x8 4. "ND36,New data" "0,1" bitfld.long 0x8 3. "ND35,New data" "0,1" bitfld.long 0x8 2. "ND34,New data" "0,1" bitfld.long 0x8 1. "ND33,New data" "0,1" bitfld.long 0x8 0. "ND32,New data" "0,1" group.long 0xA0++0x23 line.long 0x0 "FDCAN_RXF0C,FDCAN Rx FIFO 0 Configuration" hexmask.long.byte 0x0 24.--31. 1. "F0WM,FIFO 0 Watermark" hexmask.long.byte 0x0 16.--23. 1. "F0S,Rx FIFO 0 Size" hexmask.long.word 0x0 2.--15. 1. "F0SA,Rx FIFO 0 Start Address" line.long 0x4 "FDCAN_RXF0S,FDCAN Rx FIFO 0 Status" bitfld.long 0x4 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x4 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x4 16.--21. 1. "F0P,Rx FIFO 0 Put Index" hexmask.long.byte 0x4 8.--13. 1. "F0G,Rx FIFO 0 Get Index" hexmask.long.byte 0x4 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" line.long 0x8 "FDCAN_RXF0A,CAN Rx FIFO 0 Acknowledge" hexmask.long.byte 0x8 0.--5. 1. "FA01,Rx FIFO 0 Acknowledge" line.long 0xC "FDCAN_RXBC,FDCAN Rx Buffer Configuration" hexmask.long.word 0xC 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x10 "FDCAN_RXF1C,FDCAN Rx FIFO 1 Configuration" hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark" hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size" hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address" line.long 0x14 "FDCAN_RXF1S,FDCAN Rx FIFO 1 Status" bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3" bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1" hexmask.long.byte 0x14 16.--22. 1. "F1PI,Rx FIFO 1 Put Index" hexmask.long.byte 0x14 8.--14. 1. "F1GI,Rx FIFO 1 Get Index" hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level" line.long 0x18 "FDCAN_RXF1A,FDCAN Rx FIFO 1 Acknowledge" hexmask.long.byte 0x18 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge" line.long 0x1C "FDCAN_RXESC,FDCAN Rx Buffer Element Size Configuration" hexmask.long.byte 0x1C 8.--11. 1. "RBDS,Rx Buffer Data Field Size:" hexmask.long.byte 0x1C 4.--7. 1. "F1DS,Rx FIFO 0 Data Field Size:" hexmask.long.byte 0x1C 0.--3. 1. "F0DS,Rx FIFO 1 Data Field Size:" line.long 0x20 "FDCAN_TXBC,FDCAN Tx Buffer Configuration" bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x20 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x20 16.--21. 1. "NDTB,Number of Dedicated Transmit" hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address" rgroup.long 0xC4++0x3 line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/Queue Status" bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x0 8.--12. 1. "TFGI,TFGI" hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0xC8++0x3 line.long 0x0 "FDCAN_TXESC,FDCAN Tx Buffer Element Size Configuration" hexmask.long.byte 0x0 0.--3. 1. "TBDS,Tx Buffer Data Field Size:" rgroup.long 0xCC++0x3 line.long 0x0 "FDCAN_TXBRP,FDCAN Tx Buffer Request Pending" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request" group.long 0xD0++0xB line.long 0x0 "FDCAN_TXBAR,FDCAN Tx Buffer Add Request" hexmask.long 0x0 0.--31. 1. "AR,Add Request" line.long 0x4 "FDCAN_TXBCR,FDCAN Tx Buffer Cancellation Request" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" line.long 0x8 "FDCAN_TXBTO,FDCAN Tx Buffer Transmission Occurred" hexmask.long 0x8 0.--31. 1. "TO,Transmission Occurred." rgroup.long 0xDC++0x3 line.long 0x0 "FDCAN_TXBCF,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x0 0.--31. 1. "CF,Cancellation Finished" group.long 0xE0++0x7 line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx Buffer Transmission Interrupt" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt" line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx Buffer Cancellation Finished" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished Interrupt" group.long 0xF0++0xB line.long 0x0 "FDCAN_TXEFC,FDCAN Tx Event FIFO Configuration" hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address" line.long 0x4 "FDCAN_TXEFS,FDCAN Tx Event FIFO Status" bitfld.long 0x4 25. "TEFL,Tx Event FIFO Element" "0,1" bitfld.long 0x4 24. "EFF,Event FIFO Full." "0,1" hexmask.long.byte 0x4 16.--20. 1. "EFPI,Event FIFO put index." hexmask.long.byte 0x4 8.--12. 1. "EFGI,Event FIFO Get Index." hexmask.long.byte 0x4 0.--5. 1. "EFFL,Event FIFO Fill Level" line.long 0x8 "FDCAN_TXEFA,FDCAN Tx Event FIFO Acknowledge" hexmask.long.byte 0x8 0.--4. 1. "EFAI,Event FIFO Acknowledge" group.long 0x100++0x2B line.long 0x0 "FDCAN_TTTMC,FDCAN TT Trigger Memory Configuration" hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements" hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start" line.long 0x4 "FDCAN_TTRMC,FDCAN TT Reference Message Configuration" bitfld.long 0x4 31. "RMPS,Reference Message Payload" "0,1" bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1" hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier." line.long 0x8 "FDCAN_TTOCF,FDCAN TT Operation Configuration" bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0,1" bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0,1" bitfld.long 0x8 24. "EGTF,Enable Global Time" "0,1" hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit" bitfld.long 0x8 15. "EECS,Enable External Clock" "0,1" hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger" hexmask.long.byte 0x8 5.--8. 1. "LDSDL,LD of Synchronization Deviation" bitfld.long 0x8 4. "TM,Time Master" "0,1" newline bitfld.long 0x8 3. "GEN,Gap Enable" "0,1" bitfld.long 0x8 0.--1. "OM,Operation Mode" "0,1,2,3" line.long 0xC "FDCAN_TTMLM,FDCAN TT Matrix Limits" hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx" hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window" bitfld.long 0xC 6.--7. "CSS,Cycle Start" "0,1,2,3" hexmask.long.byte 0xC 0.--5. 1. "CCM,Cycle Count Max" line.long 0x10 "FDCAN_TURCF,FDCAN TUR Configuration" bitfld.long 0x10 31. "ELT,Enable Local Time" "0,1" hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration." hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration" line.long 0x14 "FDCAN_TTOCN,FDCAN TT Operation Control" bitfld.long 0x14 15. "LCKC,TT Operation Control Register" "0,1" bitfld.long 0x14 13. "ESCN,External Synchronization" "0,1" bitfld.long 0x14 12. "NIG,Next is Gap" "0,1" bitfld.long 0x14 11. "TMG,Time Mark Gap" "0,1" bitfld.long 0x14 10. "FGP,Finish Gap." "0,1" bitfld.long 0x14 9. "GCS,Gap Control Select" "0,1" bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0,1,2,3" newline bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse" "0,1" bitfld.long 0x14 3.--4. "SWS,Stop Watch Source." "0,1,2,3" bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0,1" bitfld.long 0x14 1. "ECS,External Clock" "0,1" bitfld.long 0x14 0. "SGT,Set Global time" "0,1" line.long 0x18 "CAN_TTGTP,FDCAN TT Global Time Preset" hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase" hexmask.long.word 0x18 0.--15. 1. "NCL,Time Preset" line.long 0x1C "FDCAN_TTTMK,FDCAN TT Time Mark Register" bitfld.long 0x1C 31. "LCKM,TT Time Mark Register" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code" hexmask.long.word 0x1C 0.--15. 1. "TM,Time Mark" line.long 0x20 "FDCAN_TTIR,FDCAN TT Interrupt Register" bitfld.long 0x20 18. "CER,Configuration Error" "0,1" bitfld.long 0x20 17. "AW,Application Watchdog" "0,1" bitfld.long 0x20 16. "WT,Watch Trigger" "0,1" bitfld.long 0x20 15. "IWTG,Initialization Watch" "0,1" bitfld.long 0x20 14. "ELC,Error Level Changed." "0,1" bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0,1" bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0,1" bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0,1" newline bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0,1" bitfld.long 0x20 9. "GTE,Global Time Error" "0,1" bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0,1" bitfld.long 0x20 7. "GTW,Global Time Wrap" "0,1" bitfld.long 0x20 6. "SWE,Stop Watch Event" "0,1" bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event" "0,1" bitfld.long 0x20 4. "RTMI,Register Time Mark" "0,1" bitfld.long 0x20 3. "SOG,Start of Gap" "0,1" newline bitfld.long 0x20 2. "CSM,Change of Synchronization" "0,1" bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0,1" bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0,1" line.long 0x24 "FDCAN_TTIE,FDCAN TT Interrupt Enable" bitfld.long 0x24 18. "CERE,Configuration Error Interrupt" "0,1" bitfld.long 0x24 17. "AWE,Application Watchdog Interrupt" "0,1" bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt" "0,1" bitfld.long 0x24 15. "IWTGE,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt" "0,1" bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt" "0,1" bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt" "0,1" bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt" "0,1" bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt" "0,1" bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt" "0,1" newline bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt" "0,1" line.long 0x28 "FDCAN_TTILS,FDCAN TT Interrupt Line Select" bitfld.long 0x28 18. "CERL,Configuration Error Interrupt" "0,1" bitfld.long 0x28 17. "AWL,Application Watchdog Interrupt" "0,1" bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt" "0,1" bitfld.long 0x28 15. "IWTGL,Initialization Watch Trigger Interrupt" "0,1" bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt" "0,1" bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt" "0,1" bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt" "0,1" bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt" "0,1" newline bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt" "0,1" bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt" "0,1" bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt" "0,1" bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt" "0,1" bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt" "0,1" bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal" "0,1" bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt" "0,1" bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt" "0,1" newline bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt" "0,1" bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt" "0,1" bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt" "0,1" rgroup.long 0x12C++0x17 line.long 0x0 "FDCAN_TTOST,FDCAN TT Operation Status" bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0,1" bitfld.long 0x0 30. "WECS,Wait for External Clock" "0,1" bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0,1" bitfld.long 0x0 28. "WFE,Wait for Event" "0,1" bitfld.long 0x0 27. "GSI,Gap Started Indicator." "0,1" hexmask.long.byte 0x0 24.--27. 1. "TMP,Time Master Priority" bitfld.long 0x0 23. "GFI,Gap Finished Indicator." "0,1" bitfld.long 0x0 22. "WGTD,Wait for Global Time" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset" bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0,1" bitfld.long 0x0 6. "GTP,Quality of Global Time" "0,1" bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0,1,2,3" bitfld.long 0x0 2.--3. "MS,Master State." "0,1,2,3" bitfld.long 0x0 0.--1. "EL,Error Level" "0,1,2,3" line.long 0x4 "FDCAN_TURNA,FDCAN TUR Numerator Actual" hexmask.long.tbyte 0x4 0.--17. 1. "NAV,Numerator Actual Value" line.long 0x8 "FDCAN_TTLGT,FDCAN TT Local and Global Time" hexmask.long.word 0x8 16.--31. 1. "GT,Global Time" hexmask.long.word 0x8 0.--15. 1. "LT,Local Time" line.long 0xC "FDCAN_TTCTC,FDCAN TT Cycle Time and Count" hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count" hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time" line.long 0x10 "FDCAN_TTCPT,FDCAN TT Capture Time Register" hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value" hexmask.long.byte 0x10 0.--5. 1. "CT,Cycle Count Value" line.long 0x14 "FDCAN_TTCSM,FDCAN TT Cycle Sync Mark" hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark" group.long 0x300++0x3 line.long 0x0 "FDCAN_TTTS,FDCAN TT Trigger Select" bitfld.long 0x0 4.--5. "EVTSEL,Event trigger input" "0,1,2,3" bitfld.long 0x0 0.--1. "SWTDEL,Stop watch trigger input" "0,1,2,3" tree.end endif tree.end tree "FLASH (Embedded Flash Memory)" base ad:0x52002000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) group.long 0x0++0x3 line.long 0x0 "ACR,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" newline endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" endif group.long 0x8++0x3 line.long 0x0 "OPTKEYR,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x18++0xB line.long 0x0 "OPTCR,FLASH option control register" sif (cpuis("STM32H742*")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" newline endif bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" endif bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR,FLASH option status register" sif (cpuis("STM32H742*")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" newline endif bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" newline sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" newline endif bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" bitfld.long 0x4 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" newline bitfld.long 0x4 7. "NRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "NRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_SW,IWDG1 control option status" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" endif hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 7. "NRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "NRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 7. "NRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "NRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 4. "IWDG1_SW,IWDG1 control option status" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x4 4. "IWDG1_SW,IWDG1 control option status" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" newline endif bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG,FLASH option status register" sif (cpuis("STM32H742*")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" newline endif bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" newline bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" endif bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" newline bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" newline bitfld.long 0x8 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" bitfld.long 0x8 7. "NRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "NRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_SW,IWDG1 option configuration" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline endif hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 7. "NRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "NRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x8 7. "NRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "NRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 4. "IWDG1_SW,IWDG1 option configuration" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 4. "IWDG1_SW,IWDG1 option configuration" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" endif bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x24++0x3 line.long 0x0 "OPTCCR,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" group.long 0x5C++0x3 line.long 0x0 "CRCDATAR,FLASH CRC data register" hexmask.long 0x0 0.--31. 1. "CRC_DATA,CRC result" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x4++0x3 line.long 0x0 "KEYR,FLASH key register" hexmask.long 0x0 0.--31. 1. "KEYKEYRR,access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR,FLASH control register" bitfld.long 0x0 28. "CRCRDERRIE,CRC read error interrupt enable bit" "0,1" bitfld.long 0x0 27. "CRCENDIE,end of CRC calculation interrupt" "0,1" newline bitfld.long 0x0 26. "DBECCERRIE,ECC double detection error" "0,1" bitfld.long 0x0 25. "SNECCERRIE,ECC single correction error" "0,1" newline bitfld.long 0x0 24. "RDSERRIE,secure error interrupt enable" "0,1" bitfld.long 0x0 23. "RDPERRIE,read protection error interrupt" "0,1" newline bitfld.long 0x0 22. "OPERRIE,write/erase error interrupt" "0,1" bitfld.long 0x0 21. "INCERRIE,inconsistency error interrupt" "0,1" newline bitfld.long 0x0 19. "STRBERRIE,strobe error interrupt enable" "0,1" bitfld.long 0x0 18. "PGSERRIE,programming sequence error" "0,1" newline bitfld.long 0x0 17. "WRPERRIE,write protection error interrupt" "0,1" bitfld.long 0x0 16. "EOPIE,end-of-program interrupt control" "0,1" newline bitfld.long 0x0 15. "CRC_EN,CRC control bit" "0,1" bitfld.long 0x0 8.--10. "SNB,sector erase selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "START,bank or sector erase start" "0,1" bitfld.long 0x0 6. "FW,write forcing control" "0,1" newline bitfld.long 0x0 4.--5. "PSIZE,program size" "0,1,2,3" bitfld.long 0x0 3. "BER,erase request" "0,1" newline bitfld.long 0x0 2. "SER,sector erase request" "0,1" bitfld.long 0x0 1. "PG,program enable bit" "0,1" newline bitfld.long 0x0 0. "LOCK,configuration lock bit" "0,1" line.long 0x4 "SR,FLASH status register for bank" rbitfld.long 0x4 28. "CRCRDERR,CRC read error flag" "0,1" bitfld.long 0x4 27. "CRCEND,CRC-complete flag" "0,1" newline bitfld.long 0x4 26. "DBECCERR,ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERR,single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERR,secure error flag" "0,1" bitfld.long 0x4 23. "RDPERR,read protection error" "0,1" newline bitfld.long 0x4 22. "OPERR,write/erase error" "0,1" bitfld.long 0x4 21. "INCERR,inconsistency error" "0,1" newline bitfld.long 0x4 19. "STRBERR,strobe error flag" "0,1" bitfld.long 0x4 18. "PGSERR,programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERR,write protection error" "0,1" bitfld.long 0x4 16. "EOP,end-of-program flag" "0,1" newline bitfld.long 0x4 3. "CRC_BUSY,CRC busy flag" "0,1" bitfld.long 0x4 2. "QW,wait queue flag" "0,1" newline bitfld.long 0x4 1. "WBNE,write buffer not empty" "0,1" bitfld.long 0x4 0. "BSY,ongoing program" "0,1" line.long 0x8 "CCR,FLASH clear control register for bank" bitfld.long 0x8 28. "CLR_CRCRDERR,CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x8 27. "CLR_CRCEND,CRCEND flag clear" "0,1" newline bitfld.long 0x8 26. "CLR_DBECCERR,DBECCERR flag clear" "0,1" bitfld.long 0x8 25. "CLR_SNECCERR,SNECCERR flag clear" "0,1" newline bitfld.long 0x8 24. "CLR_RDSERR,RDSERR flag clear" "0,1" bitfld.long 0x8 23. "CLR_RDPERR,RDPERR flag clear" "0,1" newline bitfld.long 0x8 22. "CLR_OPERR,OPERR flag clear" "0,1" bitfld.long 0x8 21. "CLR_INCERR,INCERR flag clear" "0,1" newline bitfld.long 0x8 19. "CLR_STRBERR,STRBERR flag clear" "0,1" bitfld.long 0x8 18. "CLR_PGSERR,PGSERR flag clear" "0,1" newline bitfld.long 0x8 17. "CLR_WRPERR,WRPERR1 flag clear" "0,1" bitfld.long 0x8 16. "CLR_EOP,EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP,PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END,highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START,lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP,PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END,highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START,lowest PCROP protected address" line.long 0x4 "SCAR_CUR,FLASH secure address for bank" bitfld.long 0x4 31. "DMES,secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END,highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START,lowest secure protected" line.long 0x8 "SCAR_PRG,FLASH secure address for bank" bitfld.long 0x8 31. "DMES,secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END,highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START,lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn,sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn,sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CUR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_CM_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_CM_ADD0,Boot address 0" line.long 0x4 "BOOT_PRG,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_CM_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_CM_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR,FLASH CRC control register for bank" bitfld.long 0x0 22. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 20.--21. "CRC_BURST,CRC burst size" "0,1,2,3" newline bitfld.long 0x0 17. "CLEAN_CRC,CRC clear bit" "0,1" bitfld.long 0x0 16. "START_CRC,CRC start bit" "0,1" newline bitfld.long 0x0 10. "CLEAN_SECT,CRC sector list clear" "0,1" bitfld.long 0x0 9. "ADD_SECT,CRC sector select" "0,1" newline bitfld.long 0x0 8. "CRC_BY_SECT,CRC sector mode select" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADDR,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "CRCEADDR,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FAR,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR,ECC error address" rgroup.long 0x70++0x3 line.long 0x0 "OPTSR2_CUR,FLASH ECC fail address for bank" bitfld.long 0x0 2. "CPUFREQ_BOOST,CPU frequency boost status bit" "0,1" bitfld.long 0x0 0.--1. "TCM_AXI_SHARED,TCM RAM sharing status bit" "0,1,2,3" group.long 0x74++0x3 line.long 0x0 "OPTSR2_PRG,FLASH ECC fail address for bank" bitfld.long 0x0 2. "CPUFREQ_BOOST,CPU frequency boost status bit" "0,1" bitfld.long 0x0 0.--1. "TCM_AXI_SHARED,TCM RAM sharing status bit" "0,1,2,3" endif sif (cpuis("STM32H742*")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEY1R,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 28. "CRCRDERRIE1,Bank 1 CRC read error interrupt enable bit" "0,1" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x0 25. "SNECCERR1,Bank 1 ECC single correction error" "0,1" newline bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" newline bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" newline bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" newline bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" newline bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" newline bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" newline bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" rbitfld.long 0x4 28. "CRCRDERR1,Bank 1 CRC read error flag" "0,1" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" newline bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERR,Bank 1 single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" newline bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" newline bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" newline bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" newline bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 28. "CLR_CRCRDERR1,Bank 1 CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" newline bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" newline bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" newline bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" newline bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" newline bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" endif sif (cpuis("STM32H743*")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEY1R,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 28. "CRCRDERRIE1,Bank 1 CRC read error interrupt enable bit" "0,1" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x0 25. "SNECCERR1,Bank 1 ECC single correction error" "0,1" newline bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" newline bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" newline bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" newline bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" newline bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" newline bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" newline bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" rbitfld.long 0x4 28. "CRCRDERR1,Bank 1 CRC read error flag" "0,1" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" newline bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERR,Bank 1 single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" newline bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" newline bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" newline bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" newline bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 28. "CLR_CRCRDERR1,Bank 1 CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" newline bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" newline bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" newline bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" newline bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" newline bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x108++0x1B line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" line.long 0x4 "CR2,FLASH control register for bank" bitfld.long 0x4 28. "CRCRDERRIE2,Bank 2 CRC read error interrupt enable bit" "0,1" bitfld.long 0x4 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x4 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" bitfld.long 0x4 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" newline bitfld.long 0x4 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" bitfld.long 0x4 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" newline bitfld.long 0x4 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" bitfld.long 0x4 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" bitfld.long 0x4 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" newline bitfld.long 0x4 15. "CRC_EN,Bank 2 CRC control bit" "0,1" bitfld.long 0x4 14. "SPSS2,Bank 2 special sector selection bit" "0,1" newline bitfld.long 0x4 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x4 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x4 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x4 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x4 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x4 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x4 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x8 "SR2,FLASH status register for bank" bitfld.long 0x8 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x8 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x8 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x8 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x8 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x8 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x8 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x8 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x8 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x8 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x8 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x8 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x8 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x8 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x8 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0xC "CCR2,FLASH clear control register for bank" bitfld.long 0xC 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0xC 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0xC 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0xC 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0xC 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0xC 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0xC 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0xC 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0xC 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0xC 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0xC 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" line.long 0x10 "OPTCR_,FLASH option control register" bitfld.long 0x10 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x10 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x10 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x10 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x10 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x14 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x14 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x14 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x14 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x14 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x14 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x14 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x14 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x14 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x14 7. "NRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x14 6. "NRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x14 4. "IWDG1_SW,IWDG1 control option status" "0,1" bitfld.long 0x14 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x14 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x18 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x18 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x18 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x18 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x18 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x18 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x18 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x18 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x18 7. "nRST_STDY,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x18 6. "nRST_STOP,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x18 4. "IWDG1_SW,IWDG1 option configuration" "0,1" newline bitfld.long 0x18 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x12C++0xB line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" line.long 0x4 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x8 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x8 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" rgroup.long 0x140++0x7 line.long 0x0 "BOOT_CURR_,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR_,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x150++0xF line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 2" line.long 0xC "CRCDATAR_,FLASH CRC data register" hexmask.long 0xC 0.--31. 1. "CRC_DATA,CRC result" endif sif (cpuis("STM32H745??-CM4")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H745??-CM7")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H747??-CM4")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H747??-CM7")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H750*")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEY1R,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 28. "CRCRDERRIE1,Bank 1 CRC read error interrupt enable bit" "0,1" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x0 25. "SNECCERR1,Bank 1 ECC single correction error" "0,1" newline bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" newline bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" newline bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" newline bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" newline bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" newline bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" newline bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" rbitfld.long 0x4 28. "CRCRDERR1,Bank 1 CRC read error flag" "0,1" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" newline bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERR,Bank 1 single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" newline bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" newline bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" newline bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" newline bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 28. "CLR_CRCRDERR1,Bank 1 CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" newline bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" newline bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" newline bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" newline bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" newline bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x108++0x1B line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" line.long 0x4 "CR2,FLASH control register for bank" bitfld.long 0x4 28. "CRCRDERRIE2,Bank 2 CRC read error interrupt enable bit" "0,1" bitfld.long 0x4 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x4 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" bitfld.long 0x4 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" newline bitfld.long 0x4 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" bitfld.long 0x4 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" newline bitfld.long 0x4 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" bitfld.long 0x4 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" bitfld.long 0x4 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" newline bitfld.long 0x4 15. "CRC_EN,Bank 2 CRC control bit" "0,1" bitfld.long 0x4 14. "SPSS2,Bank 2 special sector selection bit" "0,1" newline bitfld.long 0x4 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x4 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x4 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x4 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x4 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x4 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x4 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x8 "SR2,FLASH status register for bank" bitfld.long 0x8 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x8 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x8 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x8 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x8 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x8 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x8 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x8 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x8 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x8 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x8 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x8 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x8 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x8 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x8 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0xC "CCR2,FLASH clear control register for bank" bitfld.long 0xC 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0xC 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0xC 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0xC 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0xC 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0xC 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0xC 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0xC 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0xC 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0xC 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0xC 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" line.long 0x10 "OPTCR_,FLASH option control register" bitfld.long 0x10 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x10 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x10 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x10 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x10 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x14 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x14 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x14 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x14 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x14 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x14 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x14 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x14 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x14 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x14 7. "NRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x14 6. "NRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x14 4. "IWDG1_SW,IWDG1 control option status" "0,1" bitfld.long 0x14 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x14 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x18 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x18 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x18 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x18 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x18 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x18 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x18 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x18 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x18 7. "nRST_STDY,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x18 6. "nRST_STOP,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x18 4. "IWDG1_SW,IWDG1 option configuration" "0,1" newline bitfld.long 0x18 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x12C++0xB line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" line.long 0x4 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x8 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x8 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" rgroup.long 0x140++0x7 line.long 0x0 "BOOT_CURR_,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR_,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x150++0xF line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 2" line.long 0xC "CRCDATAR_,FLASH CRC data register" hexmask.long 0xC 0.--31. 1. "CRC_DATA,CRC result" endif sif (cpuis("STM32H753*")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEY1R,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 28. "CRCRDERRIE1,Bank 1 CRC read error interrupt enable bit" "0,1" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x0 25. "SNECCERR1,Bank 1 ECC single correction error" "0,1" newline bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" newline bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" newline bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" newline bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" newline bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" newline bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" newline bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" rbitfld.long 0x4 28. "CRCRDERR1,Bank 1 CRC read error flag" "0,1" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" newline bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERR,Bank 1 single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" newline bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" newline bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" newline bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" newline bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 28. "CLR_CRCRDERR1,Bank 1 CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" newline bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" newline bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" newline bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" newline bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" newline bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x108++0x1B line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" line.long 0x4 "CR2,FLASH control register for bank" bitfld.long 0x4 28. "CRCRDERRIE2,Bank 2 CRC read error interrupt enable bit" "0,1" bitfld.long 0x4 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x4 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" bitfld.long 0x4 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" newline bitfld.long 0x4 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" bitfld.long 0x4 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" newline bitfld.long 0x4 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" bitfld.long 0x4 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" bitfld.long 0x4 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" newline bitfld.long 0x4 15. "CRC_EN,Bank 2 CRC control bit" "0,1" bitfld.long 0x4 14. "SPSS2,Bank 2 special sector selection bit" "0,1" newline bitfld.long 0x4 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x4 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x4 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x4 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x4 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x4 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x4 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x8 "SR2,FLASH status register for bank" bitfld.long 0x8 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x8 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x8 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x8 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x8 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x8 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x8 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x8 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x8 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x8 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x8 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x8 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x8 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x8 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x8 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0xC "CCR2,FLASH clear control register for bank" bitfld.long 0xC 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0xC 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0xC 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0xC 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0xC 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0xC 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0xC 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0xC 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0xC 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0xC 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0xC 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" line.long 0x10 "OPTCR_,FLASH option control register" bitfld.long 0x10 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x10 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x10 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x10 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x10 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x14 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x14 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x14 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x14 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x14 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x14 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x14 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x14 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x14 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x14 7. "NRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x14 6. "NRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x14 4. "IWDG1_SW,IWDG1 control option status" "0,1" bitfld.long 0x14 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x14 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x18 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x18 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x18 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x18 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x18 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x18 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x18 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x18 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x18 7. "nRST_STDY,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x18 6. "nRST_STOP,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x18 4. "IWDG1_SW,IWDG1 option configuration" "0,1" newline bitfld.long 0x18 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x12C++0xB line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" line.long 0x4 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x8 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x8 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" rgroup.long 0x140++0x7 line.long 0x0 "BOOT_CURR_,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR_,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x150++0xF line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 2" line.long 0xC "CRCDATAR_,FLASH CRC data register" hexmask.long 0xC 0.--31. 1. "CRC_DATA,CRC result" endif sif (cpuis("STM32H755??-CM4")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x4++0x3 line.long 0x0 "KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEYR1,Bank 1 access configuration unlock" group.long 0xC++0xB line.long 0x0 "CR1,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE1,Bank 1 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE1,Bank 1 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB1,Bank 1 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START1,Bank 1 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW1,Bank 1 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE1,Bank 1 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0,1" bitfld.long 0x0 2. "SER1,Bank 1 sector erase" "0,1" newline bitfld.long 0x0 1. "PG1,Bank 1 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock" "0,1" line.long 0x4 "SR1,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND1,Bank 1 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR1,Bank 1 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR11,Bank 1 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR1,Bank 1 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR1,Bank 1 read protection error" "0,1" bitfld.long 0x4 22. "OPERR1,Bank 1 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR1,Bank 1 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR1,Bank 1 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR1,Bank 1 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR1,Bank 1 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP1,Bank 1 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW1,Bank 1 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE1,Bank 1 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY1,Bank 1 ongoing program" "0,1" line.long 0x8 "CCR1,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR1,Bank 1 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "PRAR_CUR1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected" group.long 0x2C++0xB line.long 0x0 "PRAR_PRG1,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 lowest PCROP protected address" line.long 0x4 "SCAR_CUR1,FLASH secure address for bank" bitfld.long 0x4 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected" line.long 0x8 "SCAR_PRG1,FLASH secure address for bank" bitfld.long 0x8 31. "DMES1,Bank 1 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END1,Bank 1 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START1,Bank 1 lowest secure protected address" rgroup.long 0x38++0x3 line.long 0x0 "WPSN_CUR1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection option" group.long 0x3C++0x3 line.long 0x0 "WPSN_PRG1R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn1,Bank 1 sector write protection" rgroup.long 0x40++0x7 line.long 0x0 "BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xB line.long 0x0 "CRCCR1,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 1 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD1R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD1R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 1" rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x10C++0xB line.long 0x0 "CR2,FLASH control register for bank" bitfld.long 0x0 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" bitfld.long 0x0 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x0 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" bitfld.long 0x0 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" newline bitfld.long 0x0 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" bitfld.long 0x0 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" newline bitfld.long 0x0 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" bitfld.long 0x0 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" newline bitfld.long 0x0 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" bitfld.long 0x0 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" newline bitfld.long 0x0 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" bitfld.long 0x0 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline bitfld.long 0x0 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x0 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x0 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x0 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x0 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x0 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x0 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x4 "SR2,FLASH status register for bank" bitfld.long 0x4 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x4 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x4 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x4 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x4 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x4 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x4 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x4 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x4 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x4 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x4 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x4 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x4 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x4 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x4 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0x8 "CCR2,FLASH clear control register for bank" bitfld.long 0x8 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0x8 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0x8 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0x8 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0x8 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0x8 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0x8 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0x8 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0x8 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0x8 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0x8 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" wgroup.long 0x4++0x7 line.long 0x0 "FLASH_KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEY1R,Non-volatile memory bank 1 configuration access unlock key" line.long 0x4 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x4 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0xC++0x3 line.long 0x0 "FLASH_CR1," bitfld.long 0x0 28. "CRCRDERRIE1,Bank 1 CRC read error interrupt enable bit" "0: no interrupt generated when a CRC read error..,1: interrupt generated when a CRC read error occurs.." bitfld.long 0x0 27. "CRCENDIE1,Bank 1 CRC end of calculation interrupt enable bit" "0: no interrupt generated when CRC computation..,1: interrupt generated when CRC computation.." newline bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error interrupt enable bit" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.." bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error interrupt enable bit" "0: no interrupt generated when an ECC single..,1: interrupt generated when an ECC single.." newline bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable bit" "0: no interrupt generated when a secure error..,1: an interrupt is generated when a secure error.." bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt enable bit" "0: no interrupt generated when a read protection..,1: an interrupt is generated when a read protection.." newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt enable bit" "0: no interrupt generated when a inconsistency..,1: interrupt generated when a inconsistency error.." bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable bit" "0: no interrupt generated when a strobe error..,1: interrupt generated when strobe error occurs on.." newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error interrupt enable bit" "0: no interrupt generated when a sequence error..,1: interrupt generated when sequence error occurs.." bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt enable bit" "0: no interrupt generated when a protection error..,1: interrupt generated when a protection error.." newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control bit" "0: no interrupt generated at the end of a program..,1: interrupt enabled when at the end of a program.." bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline hexmask.long.byte 0x0 6.--12. 1. "SSN1,Bank 1 sector erase selection number" bitfld.long 0x0 5. "START1,Bank 1 erase start control bit" "0,1" newline bitfld.long 0x0 4. "FW1,Bank 1 write forcing control bit" "0,1" bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0: bank erase not requested on bank 1,1: bank erase requested on bank 1" newline bitfld.long 0x0 2. "SER1,Bank 1 sector erase request" "0: sector erase not requested on bank 1,1: sector erase requested on bank 1" bitfld.long 0x0 1. "PG1,Bank 1 internal buffer control bit" "0: Internal buffer disabled for write operations to..,1: Internal buffer enabled for write operations to.." newline bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock bit" "0: FLASH_CR1 register unlocked,1: FLASH_CR1 register locked" rgroup.long 0x10++0x3 line.long 0x0 "FLASH_SR1," bitfld.long 0x0 28. "CRCRDERR1,Bank 1 CRC read error flag" "0: no protected area detected inside address read..,1: a protected area has been detected inside.." bitfld.long 0x0 27. "CRCEND1,Bank 1 CRC end of calculation flag" "0: CRC computation not complete on bank 1,1: CRC computation complete on bank 1" newline bitfld.long 0x0 26. "DBECCERR1,Bank 1 ECC double detection error flag" "0: no ECC double detection error occurred on bank 1,1: ECC double detection error occurred on bank 1" bitfld.long 0x0 25. "SNECCERR1,Bank 1 single correction error flag" "0: no ECC single correction error occurs on bank 1,1: ECC single correction error occurs on bank 1" newline bitfld.long 0x0 24. "RDSERR1,Bank 1 secure error flag" "0: no secure error occurs on bank 1,1: a secure error occurs on bank 1" bitfld.long 0x0 23. "RDPERR1,Bank 1 read protection error flag" "0: no read protection error occurs on bank 1,1: a read protection error occurs on bank 1" newline bitfld.long 0x0 21. "INCERR1,Bank 1 inconsistency error flag" "0: no inconsistency error occurs on bank 1,1: a inconsistency error occurs on bank 1" bitfld.long 0x0 19. "STRBERR1,Bank 1 strobe error flag" "0: no strobe error occurs on bank 1,1: a strobe error occurs on bank 1" newline bitfld.long 0x0 18. "PGSERR1,Bank 1 programming sequence error flag" "0: no sequence error occurs on bank 1,1: a sequence error occurs on bank 1" bitfld.long 0x0 17. "WRPERR1,Bank 1 write protection error flag" "0: no write protection error occurs on bank 1,1: a write protection error occurs on bank 1" newline bitfld.long 0x0 16. "EOP1,Bank 1 end-of-program flag" "0: no programming operation completed on bank 1,1: a programming operation completed on bank 1" bitfld.long 0x0 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0: no CRC calculation ongoing on bank 1,1: CRC calculation ongoing on bank 1" newline bitfld.long 0x0 2. "QW1,Bank 1 wait queue flag" "0: no write erase or option byte change operations..,1: at least one write erase or option byte change.." bitfld.long 0x0 1. "WBNE1,Bank 1 write buffer not empty flag" "0: write buffer of bank 1 empty or full,1: write buffer of bank 1 waiting data to complete" newline bitfld.long 0x0 0. "BSY1,Bank 1 busy flag" "0: no programming erase or option byte change..,1: programming erase or option byte change.." wgroup.long 0x14++0x3 line.long 0x0 "FLASH_CCR1," bitfld.long 0x0 28. "CLR_CRCRDERR1,Bank 1 CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x0 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear bit" "0,1" newline bitfld.long 0x0 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear bit" "0,1" bitfld.long 0x0 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear bit" "0,1" newline bitfld.long 0x0 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear bit" "0,1" bitfld.long 0x0 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear bit" "0,1" newline bitfld.long 0x0 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear bit" "0,1" bitfld.long 0x0 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear bit" "0,1" newline bitfld.long 0x0 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear bit" "0,1" bitfld.long 0x0 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear bit" "0,1" newline bitfld.long 0x0 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" group.long 0x18++0xB line.long 0x0 "FLASH_OPTCR,FLASH option control register" rbitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 5. "PG_OTP,OTP program control bit" "0,1" bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "FLASH_OPTSR_CUR,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "VDDIO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "WDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" bitfld.long 0x4 16. "VDDMMC_HSLV,IWDG Stop mode freeze option status" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" bitfld.long 0x4 7. "NRST_STDY,D1 DStandby entry reset option status" "0,1" newline bitfld.long 0x4 6. "NRST_STOP,D1 DStop entry reset option status" "0,1" bitfld.long 0x4 4. "IWDG_SW,IWDG1 control option status" "0,1" newline bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "FLASH_OPTSR_PRG,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "VDDIO_HSLV,VDDIO_HSLV" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "WDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline bitfld.long 0x8 16. "VDDMMC_HSLV,VDDMMC_HSLV" "0,1" hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" newline bitfld.long 0x8 7. "NRST_STDY,Option byte erase after D1 DStandby" "0,1" bitfld.long 0x8 6. "NRST_STOP,Option byte erase after D1 DStop option" "0,1" newline bitfld.long 0x8 4. "IWDG_SW,IWDG1 option configuration" "0,1" bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x24++0x3 line.long 0x0 "FLASH_OPTCCR,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "FLASH_PRAR_CUR1,FLASH protection address for bank 1" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 PCROP area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 PCROP area start status bits" group.long 0x2C++0x3 line.long 0x0 "FLASH_PRAR_PRG1,FLASH protection address for bank 1" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 PCROP area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 PCROP area start configuration bits" rgroup.long 0x30++0x3 line.long 0x0 "FLASH_SCAR_CUR1,FLASH secure address for bank 1" bitfld.long 0x0 31. "DMES1,Bank 1 secure access protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END1,Bank 1 secure-only area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START1,Bank 1 secure-only area start status bits" group.long 0x34++0x3 line.long 0x0 "FLASH_SCAR_PRG1,FLASH secure address for bank 1" bitfld.long 0x0 31. "DMES1,Bank 1 secure access protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END1,Bank 1 secure-only area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START1,Bank 1 secure-only area start configuration bits" rgroup.long 0x38++0x3 line.long 0x0 "FLASH_WPSGN_CUR1R,FLASH write sector group protection for bank 1" hexmask.long 0x0 0.--31. 1. "WRPSGn1,Bank 1 sector group protection option status byte" group.long 0x3C++0x3 line.long 0x0 "FLASH_WPSGN_PRG1R,FLASH write sector group protection for bank 1" hexmask.long 0x0 0.--31. 1. "WRPSGn1,Bank 1 sector group protection option status byte" rgroup.long 0x40++0x7 line.long 0x0 "FLASH_BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "FLASH_BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xF line.long 0x0 "FLASH_CRCCR1,FLASH CRC control register for bank 1" bitfld.long 0x0 22. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0: every burst has a size of 4 Flash words (128-bit),1: every burst has a size of 16 Flash words (128-bit),2: every burst has a size of 64 Flash words (128-bit),3: every burst has a size of 256 Flash words.." newline bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" newline bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear bit" "0,1" bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select bit" "0,1" newline bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CRC_SECT,Bank 1 CRC sector number" line.long 0x4 "FLASH_CRCSADD1R," hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "FLASH_CRCEADD1R," hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" line.long 0xC "FLASH_CRCDATAR,FLASH CRC data register" hexmask.long 0xC 0.--31. 1. "CRC_DATA,CRC result" rgroup.long 0x60++0x3 line.long 0x0 "FLASH_ECC_FA1R," bitfld.long 0x0 31. "OTP_FAIL_ECC,OTP ECC error bit" "0,1" hexmask.long.word 0x0 0.--15. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x68++0x3 line.long 0x0 "FLASH_OTPBL_CUR,FLASH OTP block lock" hexmask.long.word 0x0 0.--15. 1. "LOCKBL,OTP Block Lock" group.long 0x6C++0x3 line.long 0x0 "FLASH_OTPBL_PRG,FLASH OTP block lock" hexmask.long.word 0x0 0.--15. 1. "LOCKBL,OTP Block Lock" group.long 0x100++0x3 line.long 0x0 "FLASH_ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" wgroup.long 0x104++0x3 line.long 0x0 "FLASH_KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEY2R,Bank 2 access configuration unlock key" group.long 0x108++0x7 line.long 0x0 "FLASH_OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" line.long 0x4 "FLASH_CR2,FLASH control register for bank 2" bitfld.long 0x4 28. "CRCRDERRIE2,Bank 2 CRC read error interrupt enable bit" "0: no interrupt generated when a CRC read error..,1: interrupt generated when a CRC read error occurs.." bitfld.long 0x4 27. "CRCENDIE2,Bank 2 CRC end of calculation interrupt enable bit" "0: no interrupt generated when CRC computation..,1: interrupt generated when CRC computation.." newline bitfld.long 0x4 26. "DBECCERRIE2,Bank 2 ECC double detection error interrupt enable bit" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.." bitfld.long 0x4 25. "SNECCERRIE2,Bank 2 ECC single correction error interrupt enable bit" "0: no interrupt generated when an ECC single..,1: interrupt generated when an ECC single.." newline bitfld.long 0x4 24. "RDSERRIE2,Bank 2 secure error interrupt enable bit" "0: no interrupt generated when a secure error..,1: an interrupt is generated when a secure error.." bitfld.long 0x4 23. "RDPERRIE2,Bank 2 read protection error interrupt enable bit" "0: no interrupt generated when a read protection..,1: an interrupt is generated when a read protection.." newline bitfld.long 0x4 21. "INCERRIE2,Bank 2 inconsistency error interrupt enable bit" "0: no interrupt generated when a inconsistency..,1: interrupt generated when a inconsistency error.." bitfld.long 0x4 19. "STRBERRIE2,Bank 2 strobe error interrupt enable bit" "0: no interrupt generated when a strobe error..,1: interrupt generated when strobe error occurs on.." newline bitfld.long 0x4 18. "PGSERRIE2,Bank 2 programming sequence error interrupt enable bit" "0: no interrupt generated when a sequence error..,1: interrupt generated when sequence error occurs.." bitfld.long 0x4 17. "WRPERRIE2,Bank 2 write protection error interrupt enable bit" "0: no interrupt generated when a protection error..,1: interrupt generated when a protection error.." newline bitfld.long 0x4 16. "EOPIE2,Bank 2 end-of-program interrupt control bit" "0: no interrupt generated at the end of a program..,1: interrupt enabled when at the end of a program.." bitfld.long 0x4 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline hexmask.long.byte 0x4 6.--12. 1. "SSN2,Bank 2 sector erase selection number" bitfld.long 0x4 5. "START2,Bank 2 erase start control bit" "0,1" newline bitfld.long 0x4 4. "FW2,Bank 2 write forcing control bit" "0,1" bitfld.long 0x4 3. "BER2,Bank 2 erase request" "0: bank erase not requested on bank 2,1: bank erase requested on bank 2" newline bitfld.long 0x4 2. "SER2,Bank 2 sector erase request" "0: sector erase not requested on bank 2,1: sector erase requested on bank 2" bitfld.long 0x4 1. "PG2,Bank 2 internal buffer control bit" "0,1" newline bitfld.long 0x4 0. "LOCK2,Bank 2 configuration lock bit" "0: FLASH_CR2 register unlocked,1: FLASH_CR2 register locked" rgroup.long 0x110++0x3 line.long 0x0 "FLASH_SR2,FLASH status register for bank 2" bitfld.long 0x0 28. "CRCRDERR2,Bank 2 CRC read error flag" "0: no protected area inside the address read by CRC..,1: a protected area inside the address read by CRC.." bitfld.long 0x0 27. "CRCEND2,Bank 2 CRC end of calculation flag" "0: CRC computation not complete on bank 2,1: CRC computation complete on bank 2" newline bitfld.long 0x0 26. "DBECCERR2,Bank 2 ECC double detection error flag" "0: no ECC double detection error occurs on bank 2,1: ECC double detection error occurs on bank 2" bitfld.long 0x0 25. "SNECCERR2,Bank 2 single correction error flag" "0: no ECC single correction error occurs on bank 2,1: ECC single correction error occurs on bank 2" newline bitfld.long 0x0 24. "RDSERR2,Bank 2 secure error flag" "0: no secure error occurs on bank 2,1: a secure error occurs on bank 2" bitfld.long 0x0 23. "RDPERR2,Bank 2 read protection error flag" "0: no read protection error occurs on bank 2,1: a read protection error occurs on bank 2" newline bitfld.long 0x0 21. "INCERR2,Bank 2 inconsistency error flag" "0: no inconsistency error occurred on bank 2,1: an inconsistency error occurred on bank 2." bitfld.long 0x0 19. "STRBERR2,Bank 2 strobe error flag" "0: no strobe error occurred on bank 2,1: a strobe error occurred on bank 2." newline bitfld.long 0x0 18. "PGSERR2,Bank 2 programming sequence error flag" "0: no sequence error occurred on bank 2,1: a sequence error occurred on bank 2." bitfld.long 0x0 17. "WRPERR2,Bank 2 write protection error flag" "0: no write protection error occurred on bank 2,1: a write protection error occurred on bank 2" newline bitfld.long 0x0 16. "EOP2,Bank 2 end-of-program flag" "0: no programming operation completed on bank 2,1: a programming operation completed on bank 2" bitfld.long 0x0 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0: no CRC calculation ongoing on bank 2,1: CRC calculation ongoing on bank 2." newline bitfld.long 0x0 2. "QW2,Bank 2 wait queue flag" "0: no write or erase operation is waiting in the..,1: at least one write or erase operation is pending.." bitfld.long 0x0 1. "WBNE2,Bank 2 write buffer not empty flag" "0: write buffer of bank 2 empty or full,1: write buffer of bank 2 waiting data to complete" newline bitfld.long 0x0 0. "BSY2,Bank 2 busy flag" "0: no write or erase operation is executed on bank 2,1: a write or an erase operation is being executed.." wgroup.long 0x114++0x3 line.long 0x0 "FLASH_CCR2,FLASH clear control register for bank 2" bitfld.long 0x0 28. "CLR_CRCRDERR2,Bank 2 CRCRDERR2 flag clear bit" "0,1" bitfld.long 0x0 27. "CLR_CRCEND2,Bank 2 CRCEND2 flag clear bit" "0,1" newline bitfld.long 0x0 26. "CLR_DBECCERR2,Bank 2 DBECCERR2 flag clear bit" "0,1" bitfld.long 0x0 25. "CLR_SNECCERR2,Bank 2 SNECCERR2 flag clear bit" "0,1" newline bitfld.long 0x0 24. "CLR_RDSERR2,Bank 2 RDSERR2 flag clear bit" "0,1" bitfld.long 0x0 23. "CLR_RDPERR2,Bank 2 RDPERR2 flag clear bit" "0,1" newline bitfld.long 0x0 21. "CLR_INCERR2,Bank 2 INCERR2 flag clear bit" "0,1" bitfld.long 0x0 19. "CLR_STRBERR2,Bank 2 STRBERR2 flag clear bit" "0,1" newline bitfld.long 0x0 18. "CLR_PGSERR2,Bank 2 PGSERR2 flag clear bit" "0,1" bitfld.long 0x0 17. "CLR_WRPERR2,Bank 2 WRPERR2 flag clear bit" "0,1" newline bitfld.long 0x0 16. "CLR_EOP2,Bank 2 EOP2 flag clear bit" "0,1" group.long 0x118++0xB line.long 0x0 "FLASH_OPTCR_,FLASH option control register" rbitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 5. "PG_OTP,OTP program control bit" "0,1" bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "FLASH_OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "VDDIO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "WDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" bitfld.long 0x4 16. "VDDMMC_HSLV,IWDG Stop mode freeze option status" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" bitfld.long 0x4 7. "NRST_STDY,D1 DStandby entry reset option status" "0,1" newline bitfld.long 0x4 6. "NRST_STOP,D1 DStop entry reset option status" "0,1" bitfld.long 0x4 4. "IWDG_SW,IWDG1 control option status" "0,1" newline bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "FLASH_OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "VDDIO_HSLV,VDDIO_HSLV" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "WDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline bitfld.long 0x8 16. "VDDMMC_HSLV,VDDMMC_HSLV" "0,1" hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" newline bitfld.long 0x8 7. "NRST_STDY,Option byte erase after D1 DStandby" "0,1" bitfld.long 0x8 6. "NRST_STOP,Option byte erase after D1 DStop option" "0,1" newline bitfld.long 0x8 4. "IWDG_SW,IWDG1 option configuration" "0,1" bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "FLASH_OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "FLASH_PRAR_CUR2,FLASH protection address for bank 2" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 PCROP area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 PCROP area start status bits" group.long 0x12C++0x3 line.long 0x0 "FLASH_PRAR_PRG2,FLASH protection address for bank 2" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 PCROP area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 PCROP area start configuration bits" rgroup.long 0x130++0x3 line.long 0x0 "FLASH_SCAR_CUR2,FLASH secure address for bank 2" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 secure-only area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 secure-only area start status bits" group.long 0x134++0x3 line.long 0x0 "FLASH_SCAR_PRG2,FLASH secure address for bank 2" bitfld.long 0x0 31. "DMES2,Bank 2 secure access protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 secure-only area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 secure-only area start configuration bits" rgroup.long 0x138++0x3 line.long 0x0 "FLASH_WPSGN_CUR2R,FLASH write sector group protection for bank 2" hexmask.long 0x0 0.--31. 1. "WRPSGn2,Bank 2 sector group protection option status byte" group.long 0x13C++0x3 line.long 0x0 "FLASH_WPSGN_PRG2R,FLASH write sector group protection for bank 2" hexmask.long 0x0 0.--31. 1. "WRPSGn2,Bank 2 sector group protection option status byte" rgroup.long 0x140++0x7 line.long 0x0 "FLASH_BOOT_CURR_,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "FLASH_BOOT_PRGR_,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x150++0xB line.long 0x0 "FLASH_CRCCR2,FLASH CRC control register for bank 2" bitfld.long 0x0 22. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0: every burst has a size of 4 Flash words (128 bit),1: every burst has a size of 16 Flash words (128-bit),2: every burst has a size of 64 Flash words (128-bit),3: every burst has a size of 256 Flash words.." newline bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" newline bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear bit" "0,1" bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select bit" "0,1" newline bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CRC_SECT,Bank 2 CRC sector number" line.long 0x4 "FLASH_CRCSADD2R,FLASH CRC start address register for bank 2" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 2" line.long 0x8 "FLASH_CRCEADD2R,FLASH CRC end address register for bank 2" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 2" endif sif (cpuis("STM32H745??-CM4")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H745??-CM7")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H747??-CM4")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H747??-CM7")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H755??-CM4")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H755??-CM7")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H757??-CM4")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H757??-CM7")) group.long 0x2C++0x3 line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" endif sif (cpuis("STM32H742*")) rgroup.long 0x60++0x3 line.long 0x0 "ECC_FA1R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" rgroup.long 0x104++0x3 line.long 0x0 "KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEYR2,Bank 2 access configuration unlock" group.long 0x108++0x1B line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" line.long 0x4 "CR2,FLASH control register for bank" bitfld.long 0x4 28. "CRCRDERRIE2,Bank 2 CRC read error interrupt enable bit" "0,1" bitfld.long 0x4 27. "CRCENDIE2,Bank 2 end of CRC calculation interrupt" "0,1" newline bitfld.long 0x4 26. "DBECCERRIE2,Bank 2 ECC double detection error" "0,1" bitfld.long 0x4 25. "SNECCERRIE2,Bank 2 ECC single correction error" "0,1" newline bitfld.long 0x4 24. "RDSERRIE2,Bank 2 secure error interrupt enable" "0,1" bitfld.long 0x4 23. "RDPERRIE2,Bank 2 read protection error interrupt" "0,1" newline bitfld.long 0x4 22. "OPERRIE2,Bank 2 write/erase error interrupt" "0,1" bitfld.long 0x4 21. "INCERRIE2,Bank 2 inconsistency error interrupt" "0,1" newline bitfld.long 0x4 19. "STRBERRIE2,Bank 2 strobe error interrupt enable" "0,1" bitfld.long 0x4 18. "PGSERRIE2,Bank 2 programming sequence error" "0,1" newline bitfld.long 0x4 17. "WRPERRIE2,Bank 2 write protection error interrupt" "0,1" bitfld.long 0x4 16. "EOPIE2,Bank 2 end-of-program interrupt control" "0,1" newline bitfld.long 0x4 15. "CRC_EN,Bank 2 CRC control bit" "0,1" bitfld.long 0x4 14. "SPSS2,Bank 2 special sector selection bit" "0,1" newline bitfld.long 0x4 8.--10. "SNB2,Bank 2 sector erase selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "START2,Bank 2 bank or sector erase start" "0,1" newline bitfld.long 0x4 6. "FW2,Bank 2 write forcing control" "0,1" bitfld.long 0x4 4.--5. "PSIZE2,Bank 2 program size" "0,1,2,3" newline bitfld.long 0x4 3. "BER2,Bank 2 erase request" "0,1" bitfld.long 0x4 2. "SER2,Bank 2 sector erase" "0,1" newline bitfld.long 0x4 1. "PG2,Bank 2 program enable bit" "0,1" bitfld.long 0x4 0. "LOCK2,Bank 2 configuration lock" "0,1" line.long 0x8 "SR2,FLASH status register for bank" bitfld.long 0x8 27. "CRCEND2,Bank 2 CRC-complete flag" "0,1" bitfld.long 0x8 26. "DBECCERR2,Bank 2 ECC double detection error" "0,1" newline bitfld.long 0x8 25. "SNECCERR2,Bank 2 single correction error" "0,1" bitfld.long 0x8 24. "RDSERR2,Bank 2 secure error flag" "0,1" newline bitfld.long 0x8 23. "RDPERR2,Bank 2 read protection error" "0,1" bitfld.long 0x8 22. "OPERR2,Bank 2 write/erase error" "0,1" newline bitfld.long 0x8 21. "INCERR2,Bank 2 inconsistency error" "0,1" bitfld.long 0x8 19. "STRBERR2,Bank 2 strobe error flag" "0,1" newline bitfld.long 0x8 18. "PGSERR2,Bank 2 programming sequence error" "0,1" bitfld.long 0x8 17. "WRPERR2,Bank 2 write protection error" "0,1" newline bitfld.long 0x8 16. "EOP2,Bank 2 end-of-program flag" "0,1" bitfld.long 0x8 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0,1" newline bitfld.long 0x8 2. "QW2,Bank 2 wait queue flag" "0,1" bitfld.long 0x8 1. "WBNE2,Bank 2 write buffer not empty" "0,1" newline bitfld.long 0x8 0. "BSY2,Bank 2 ongoing program" "0,1" line.long 0xC "CCR2,FLASH clear control register for bank" bitfld.long 0xC 27. "CLR_CRCEND2,Bank 2 CRCEND1 flag clear" "0,1" bitfld.long 0xC 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear" "0,1" newline bitfld.long 0xC 25. "CLR_SNECCERR2,Bank 2 SNECCERR1 flag clear" "0,1" bitfld.long 0xC 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear" "0,1" newline bitfld.long 0xC 23. "CLR_RDPERR2,Bank 2 RDPERR1 flag clear" "0,1" bitfld.long 0xC 22. "CLR_OPERR2,Bank 2 OPERR1 flag clear" "0,1" newline bitfld.long 0xC 21. "CLR_INCERR2,Bank 2 INCERR1 flag clear" "0,1" bitfld.long 0xC 19. "CLR_STRBERR2,Bank 2 STRBERR1 flag clear" "0,1" newline bitfld.long 0xC 18. "CLR_PGSERR2,Bank 2 PGSERR1 flag clear" "0,1" bitfld.long 0xC 17. "CLR_WRPERR2,Bank 2 WRPERR1 flag clear" "0,1" newline bitfld.long 0xC 16. "CLR_EOP2,Bank 1 EOP1 flag clear bit" "0,1" line.long 0x10 "OPTCR_,FLASH option control register" bitfld.long 0x10 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x10 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x10 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x10 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x10 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x14 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x14 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x14 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x14 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x14 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x14 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x14 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x14 17. "IWDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x14 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x14 7. "NRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x14 6. "NRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x14 4. "IWDG1_SW,IWDG1 control option status" "0,1" bitfld.long 0x14 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x14 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x18 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x18 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x18 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x18 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x18 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x18 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x18 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x18 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x18 7. "nRST_STDY,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x18 6. "nRST_STOP,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x18 4. "IWDG1_SW,IWDG1 option configuration" "0,1" newline bitfld.long 0x18 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x12C++0xB line.long 0x0 "PRAR_PRG2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected address" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected address" line.long 0x4 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x8 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x8 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x8 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x8 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" rgroup.long 0x140++0x7 line.long 0x0 "BOOT_CURR_,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "BOOT_PRGR_,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x150++0xF line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 2" line.long 0xC "CRCDATAR_,FLASH CRC data register" hexmask.long 0xC 0.--31. 1. "CRC_DATA,CRC result" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H743*")) rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H745??-CM4")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H745??-CM7")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H747??-CM4")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H747??-CM7")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H750*")) rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H753*")) rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H755??-CM4")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H755??-CM7")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H757??-CM4")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H757??-CM7")) group.long 0x100++0x3 line.long 0x0 "ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" bitfld.long 0x0 0.--2. "LATENCY,Read latency" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0x118++0xB line.long 0x0 "OPTCR_,FLASH option control register" bitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" newline bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "IO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 28. "PERSO_OK,Device personalization status" "0,1" newline bitfld.long 0x4 26. "RSS1,User option bit 1" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option status" "0,1" hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" newline bitfld.long 0x4 7. "nRST_STBY_D1,D1 DStandby entry reset option status" "0,1" bitfld.long 0x4 6. "nRST_STOP_D1,D1 DStop entry reset option status" "0,1" newline bitfld.long 0x4 4. "IWDG1_HW,IWDG1 control option status" "0,1" bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" newline bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "IO_HSLV,I/O high-speed at low-voltage" "0,1" newline bitfld.long 0x8 27. "RSS2,User option configuration bit" "0,1" bitfld.long 0x8 26. "RSS1,User option configuration bit" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "FZ_IWDG_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "FZ_IWDG_STOP,IWDG Stop mode freeze option" "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" bitfld.long 0x8 7. "nRST_STBY_D1,Option byte erase after D1 DStandby" "0,1" newline bitfld.long 0x8 6. "nRST_STOP_D1,Option byte erase after D1 DStop option" "0,1" bitfld.long 0x8 4. "IWDG1_HW,IWDG1 option configuration" "0,1" newline bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "PRAR_CUR2,FLASH protection address for bank" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 highest PCROP protected" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 lowest PCROP protected" group.long 0x130++0x7 line.long 0x0 "SCAR_CUR2,FLASH secure address for bank" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected" line.long 0x4 "SCAR_PRG2,FLASH secure address for bank" bitfld.long 0x4 31. "DMES2,Bank 2 secure protected erase enable" "0,1" hexmask.long.word 0x4 16.--27. 1. "SEC_AREA_END2,Bank 2 highest secure protected address" newline hexmask.long.word 0x4 0.--11. 1. "SEC_AREA_START2,Bank 2 lowest secure protected address" rgroup.long 0x138++0x3 line.long 0x0 "WPSN_CUR2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection option" group.long 0x13C++0x3 line.long 0x0 "WPSN_PRG2R,FLASH write sector protection for bank" hexmask.long.byte 0x0 0.--7. 1. "WRPSn2,Bank 2 sector write protection" group.long 0x150++0xB line.long 0x0 "CRCCR2,FLASH CRC control register for bank" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0,1,2,3" bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" newline bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear" "0,1" newline bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select" "0,1" bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select" "0,1" newline bitfld.long 0x0 7. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 0.--2. "CRC_SECT,Bank 2 CRC sector number" "0,1,2,3,4,5,6,7" line.long 0x4 "CRCSADD2R,FLASH CRC start address register for bank" hexmask.long 0x4 0.--31. 1. "CRC_START_ADDR,CRC start address on bank" line.long 0x8 "CRCEADD2R,FLASH CRC end address register for bank" hexmask.long 0x8 0.--31. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "ECC_FA2R,FLASH ECC fail address for bank" hexmask.long.word 0x0 0.--14. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x160++0x3 line.long 0x0 "FLASH_ECC_FA2R,FLASH ECC fail address for bank 2" hexmask.long.word 0x0 0.--15. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" wgroup.long 0x4++0x7 line.long 0x0 "FLASH_KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEY1R,Non-volatile memory bank 1 configuration access unlock key" line.long 0x4 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x4 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0xC++0x3 line.long 0x0 "FLASH_CR1," bitfld.long 0x0 28. "CRCRDERRIE1,Bank 1 CRC read error interrupt enable bit" "0: no interrupt generated when a CRC read error..,1: interrupt generated when a CRC read error occurs.." bitfld.long 0x0 27. "CRCENDIE1,Bank 1 CRC end of calculation interrupt enable bit" "0: no interrupt generated when CRC computation..,1: interrupt generated when CRC computation.." newline bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error interrupt enable bit" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.." bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error interrupt enable bit" "0: no interrupt generated when an ECC single..,1: interrupt generated when an ECC single.." newline bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable bit" "0: no interrupt generated when a secure error..,1: an interrupt is generated when a secure error.." bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt enable bit" "0: no interrupt generated when a read protection..,1: an interrupt is generated when a read protection.." newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt enable bit" "0: no interrupt generated when a inconsistency..,1: interrupt generated when a inconsistency error.." bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable bit" "0: no interrupt generated when a strobe error..,1: interrupt generated when strobe error occurs on.." newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error interrupt enable bit" "0: no interrupt generated when a sequence error..,1: interrupt generated when sequence error occurs.." bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt enable bit" "0: no interrupt generated when a protection error..,1: interrupt generated when a protection error.." newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control bit" "0: no interrupt generated at the end of a program..,1: interrupt enabled when at the end of a program.." bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline hexmask.long.byte 0x0 6.--12. 1. "SSN1,Bank 1 sector erase selection number" bitfld.long 0x0 5. "START1,Bank 1 erase start control bit" "0,1" newline bitfld.long 0x0 4. "FW1,Bank 1 write forcing control bit" "0,1" bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0: bank erase not requested on bank 1,1: bank erase requested on bank 1" newline bitfld.long 0x0 2. "SER1,Bank 1 sector erase request" "0: sector erase not requested on bank 1,1: sector erase requested on bank 1" bitfld.long 0x0 1. "PG1,Bank 1 internal buffer control bit" "0: Internal buffer disabled for write operations to..,1: Internal buffer enabled for write operations to.." newline bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock bit" "0: FLASH_CR1 register unlocked,1: FLASH_CR1 register locked" rgroup.long 0x10++0x3 line.long 0x0 "FLASH_SR1," bitfld.long 0x0 28. "CRCRDERR1,Bank 1 CRC read error flag" "0: no protected area detected inside address read..,1: a protected area has been detected inside.." bitfld.long 0x0 27. "CRCEND1,Bank 1 CRC end of calculation flag" "0: CRC computation not complete on bank 1,1: CRC computation complete on bank 1" newline bitfld.long 0x0 26. "DBECCERR1,Bank 1 ECC double detection error flag" "0: no ECC double detection error occurred on bank 1,1: ECC double detection error occurred on bank 1" bitfld.long 0x0 25. "SNECCERR1,Bank 1 single correction error flag" "0: no ECC single correction error occurs on bank 1,1: ECC single correction error occurs on bank 1" newline bitfld.long 0x0 24. "RDSERR1,Bank 1 secure error flag" "0: no secure error occurs on bank 1,1: a secure error occurs on bank 1" bitfld.long 0x0 23. "RDPERR1,Bank 1 read protection error flag" "0: no read protection error occurs on bank 1,1: a read protection error occurs on bank 1" newline bitfld.long 0x0 21. "INCERR1,Bank 1 inconsistency error flag" "0: no inconsistency error occurs on bank 1,1: a inconsistency error occurs on bank 1" bitfld.long 0x0 19. "STRBERR1,Bank 1 strobe error flag" "0: no strobe error occurs on bank 1,1: a strobe error occurs on bank 1" newline bitfld.long 0x0 18. "PGSERR1,Bank 1 programming sequence error flag" "0: no sequence error occurs on bank 1,1: a sequence error occurs on bank 1" bitfld.long 0x0 17. "WRPERR1,Bank 1 write protection error flag" "0: no write protection error occurs on bank 1,1: a write protection error occurs on bank 1" newline bitfld.long 0x0 16. "EOP1,Bank 1 end-of-program flag" "0: no programming operation completed on bank 1,1: a programming operation completed on bank 1" bitfld.long 0x0 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0: no CRC calculation ongoing on bank 1,1: CRC calculation ongoing on bank 1" newline bitfld.long 0x0 2. "QW1,Bank 1 wait queue flag" "0: no write erase or option byte change operations..,1: at least one write erase or option byte change.." bitfld.long 0x0 1. "WBNE1,Bank 1 write buffer not empty flag" "0: write buffer of bank 1 empty or full,1: write buffer of bank 1 waiting data to complete" newline bitfld.long 0x0 0. "BSY1,Bank 1 busy flag" "0: no programming erase or option byte change..,1: programming erase or option byte change.." wgroup.long 0x14++0x3 line.long 0x0 "FLASH_CCR1," bitfld.long 0x0 28. "CLR_CRCRDERR1,Bank 1 CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x0 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear bit" "0,1" newline bitfld.long 0x0 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear bit" "0,1" bitfld.long 0x0 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear bit" "0,1" newline bitfld.long 0x0 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear bit" "0,1" bitfld.long 0x0 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear bit" "0,1" newline bitfld.long 0x0 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear bit" "0,1" bitfld.long 0x0 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear bit" "0,1" newline bitfld.long 0x0 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear bit" "0,1" bitfld.long 0x0 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear bit" "0,1" newline bitfld.long 0x0 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" group.long 0x18++0xB line.long 0x0 "FLASH_OPTCR,FLASH option control register" rbitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 5. "PG_OTP,OTP program control bit" "0,1" bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "FLASH_OPTSR_CUR,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "VDDIO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "WDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" bitfld.long 0x4 16. "VDDMMC_HSLV,IWDG Stop mode freeze option status" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" bitfld.long 0x4 7. "NRST_STDY,D1 DStandby entry reset option status" "0,1" newline bitfld.long 0x4 6. "NRST_STOP,D1 DStop entry reset option status" "0,1" bitfld.long 0x4 4. "IWDG_SW,IWDG1 control option status" "0,1" newline bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "FLASH_OPTSR_PRG,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "VDDIO_HSLV,VDDIO_HSLV" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "WDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline bitfld.long 0x8 16. "VDDMMC_HSLV,VDDMMC_HSLV" "0,1" hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" newline bitfld.long 0x8 7. "NRST_STDY,Option byte erase after D1 DStandby" "0,1" bitfld.long 0x8 6. "NRST_STOP,Option byte erase after D1 DStop option" "0,1" newline bitfld.long 0x8 4. "IWDG_SW,IWDG1 option configuration" "0,1" bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x24++0x3 line.long 0x0 "FLASH_OPTCCR,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "FLASH_PRAR_CUR1,FLASH protection address for bank 1" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 PCROP area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 PCROP area start status bits" group.long 0x2C++0x3 line.long 0x0 "FLASH_PRAR_PRG1,FLASH protection address for bank 1" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 PCROP area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 PCROP area start configuration bits" rgroup.long 0x30++0x3 line.long 0x0 "FLASH_SCAR_CUR1,FLASH secure address for bank 1" bitfld.long 0x0 31. "DMES1,Bank 1 secure access protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END1,Bank 1 secure-only area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START1,Bank 1 secure-only area start status bits" group.long 0x34++0x3 line.long 0x0 "FLASH_SCAR_PRG1,FLASH secure address for bank 1" bitfld.long 0x0 31. "DMES1,Bank 1 secure access protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END1,Bank 1 secure-only area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START1,Bank 1 secure-only area start configuration bits" rgroup.long 0x38++0x3 line.long 0x0 "FLASH_WPSGN_CUR1R,FLASH write sector group protection for bank 1" hexmask.long 0x0 0.--31. 1. "WRPSGn1,Bank 1 sector group protection option status byte" group.long 0x3C++0x3 line.long 0x0 "FLASH_WPSGN_PRG1R,FLASH write sector group protection for bank 1" hexmask.long 0x0 0.--31. 1. "WRPSGn1,Bank 1 sector group protection option status byte" rgroup.long 0x40++0x7 line.long 0x0 "FLASH_BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "FLASH_BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xF line.long 0x0 "FLASH_CRCCR1,FLASH CRC control register for bank 1" bitfld.long 0x0 22. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0: every burst has a size of 4 Flash words (128-bit),1: every burst has a size of 16 Flash words (128-bit),2: every burst has a size of 64 Flash words (128-bit),3: every burst has a size of 256 Flash words.." newline bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" newline bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear bit" "0,1" bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select bit" "0,1" newline bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CRC_SECT,Bank 1 CRC sector number" line.long 0x4 "FLASH_CRCSADD1R," hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "FLASH_CRCEADD1R," hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" line.long 0xC "FLASH_CRCDATAR,FLASH CRC data register" hexmask.long 0xC 0.--31. 1. "CRC_DATA,CRC result" rgroup.long 0x60++0x3 line.long 0x0 "FLASH_ECC_FA1R," bitfld.long 0x0 31. "OTP_FAIL_ECC,OTP ECC error bit" "0,1" hexmask.long.word 0x0 0.--15. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x68++0x3 line.long 0x0 "FLASH_OTPBL_CUR,FLASH OTP block lock" hexmask.long.word 0x0 0.--15. 1. "LOCKBL,OTP Block Lock" group.long 0x6C++0x3 line.long 0x0 "FLASH_OTPBL_PRG,FLASH OTP block lock" hexmask.long.word 0x0 0.--15. 1. "LOCKBL,OTP Block Lock" group.long 0x100++0x3 line.long 0x0 "FLASH_ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" wgroup.long 0x104++0x3 line.long 0x0 "FLASH_KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEY2R,Bank 2 access configuration unlock key" group.long 0x108++0x7 line.long 0x0 "FLASH_OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" line.long 0x4 "FLASH_CR2,FLASH control register for bank 2" bitfld.long 0x4 28. "CRCRDERRIE2,Bank 2 CRC read error interrupt enable bit" "0: no interrupt generated when a CRC read error..,1: interrupt generated when a CRC read error occurs.." bitfld.long 0x4 27. "CRCENDIE2,Bank 2 CRC end of calculation interrupt enable bit" "0: no interrupt generated when CRC computation..,1: interrupt generated when CRC computation.." newline bitfld.long 0x4 26. "DBECCERRIE2,Bank 2 ECC double detection error interrupt enable bit" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.." bitfld.long 0x4 25. "SNECCERRIE2,Bank 2 ECC single correction error interrupt enable bit" "0: no interrupt generated when an ECC single..,1: interrupt generated when an ECC single.." newline bitfld.long 0x4 24. "RDSERRIE2,Bank 2 secure error interrupt enable bit" "0: no interrupt generated when a secure error..,1: an interrupt is generated when a secure error.." bitfld.long 0x4 23. "RDPERRIE2,Bank 2 read protection error interrupt enable bit" "0: no interrupt generated when a read protection..,1: an interrupt is generated when a read protection.." newline bitfld.long 0x4 21. "INCERRIE2,Bank 2 inconsistency error interrupt enable bit" "0: no interrupt generated when a inconsistency..,1: interrupt generated when a inconsistency error.." bitfld.long 0x4 19. "STRBERRIE2,Bank 2 strobe error interrupt enable bit" "0: no interrupt generated when a strobe error..,1: interrupt generated when strobe error occurs on.." newline bitfld.long 0x4 18. "PGSERRIE2,Bank 2 programming sequence error interrupt enable bit" "0: no interrupt generated when a sequence error..,1: interrupt generated when sequence error occurs.." bitfld.long 0x4 17. "WRPERRIE2,Bank 2 write protection error interrupt enable bit" "0: no interrupt generated when a protection error..,1: interrupt generated when a protection error.." newline bitfld.long 0x4 16. "EOPIE2,Bank 2 end-of-program interrupt control bit" "0: no interrupt generated at the end of a program..,1: interrupt enabled when at the end of a program.." bitfld.long 0x4 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline hexmask.long.byte 0x4 6.--12. 1. "SSN2,Bank 2 sector erase selection number" bitfld.long 0x4 5. "START2,Bank 2 erase start control bit" "0,1" newline bitfld.long 0x4 4. "FW2,Bank 2 write forcing control bit" "0,1" bitfld.long 0x4 3. "BER2,Bank 2 erase request" "0: bank erase not requested on bank 2,1: bank erase requested on bank 2" newline bitfld.long 0x4 2. "SER2,Bank 2 sector erase request" "0: sector erase not requested on bank 2,1: sector erase requested on bank 2" bitfld.long 0x4 1. "PG2,Bank 2 internal buffer control bit" "0,1" newline bitfld.long 0x4 0. "LOCK2,Bank 2 configuration lock bit" "0: FLASH_CR2 register unlocked,1: FLASH_CR2 register locked" rgroup.long 0x110++0x3 line.long 0x0 "FLASH_SR2,FLASH status register for bank 2" bitfld.long 0x0 28. "CRCRDERR2,Bank 2 CRC read error flag" "0: no protected area inside the address read by CRC..,1: a protected area inside the address read by CRC.." bitfld.long 0x0 27. "CRCEND2,Bank 2 CRC end of calculation flag" "0: CRC computation not complete on bank 2,1: CRC computation complete on bank 2" newline bitfld.long 0x0 26. "DBECCERR2,Bank 2 ECC double detection error flag" "0: no ECC double detection error occurs on bank 2,1: ECC double detection error occurs on bank 2" bitfld.long 0x0 25. "SNECCERR2,Bank 2 single correction error flag" "0: no ECC single correction error occurs on bank 2,1: ECC single correction error occurs on bank 2" newline bitfld.long 0x0 24. "RDSERR2,Bank 2 secure error flag" "0: no secure error occurs on bank 2,1: a secure error occurs on bank 2" bitfld.long 0x0 23. "RDPERR2,Bank 2 read protection error flag" "0: no read protection error occurs on bank 2,1: a read protection error occurs on bank 2" newline bitfld.long 0x0 21. "INCERR2,Bank 2 inconsistency error flag" "0: no inconsistency error occurred on bank 2,1: an inconsistency error occurred on bank 2." bitfld.long 0x0 19. "STRBERR2,Bank 2 strobe error flag" "0: no strobe error occurred on bank 2,1: a strobe error occurred on bank 2." newline bitfld.long 0x0 18. "PGSERR2,Bank 2 programming sequence error flag" "0: no sequence error occurred on bank 2,1: a sequence error occurred on bank 2." bitfld.long 0x0 17. "WRPERR2,Bank 2 write protection error flag" "0: no write protection error occurred on bank 2,1: a write protection error occurred on bank 2" newline bitfld.long 0x0 16. "EOP2,Bank 2 end-of-program flag" "0: no programming operation completed on bank 2,1: a programming operation completed on bank 2" bitfld.long 0x0 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0: no CRC calculation ongoing on bank 2,1: CRC calculation ongoing on bank 2." newline bitfld.long 0x0 2. "QW2,Bank 2 wait queue flag" "0: no write or erase operation is waiting in the..,1: at least one write or erase operation is pending.." bitfld.long 0x0 1. "WBNE2,Bank 2 write buffer not empty flag" "0: write buffer of bank 2 empty or full,1: write buffer of bank 2 waiting data to complete" newline bitfld.long 0x0 0. "BSY2,Bank 2 busy flag" "0: no write or erase operation is executed on bank 2,1: a write or an erase operation is being executed.." wgroup.long 0x114++0x3 line.long 0x0 "FLASH_CCR2,FLASH clear control register for bank 2" bitfld.long 0x0 28. "CLR_CRCRDERR2,Bank 2 CRCRDERR2 flag clear bit" "0,1" bitfld.long 0x0 27. "CLR_CRCEND2,Bank 2 CRCEND2 flag clear bit" "0,1" newline bitfld.long 0x0 26. "CLR_DBECCERR2,Bank 2 DBECCERR2 flag clear bit" "0,1" bitfld.long 0x0 25. "CLR_SNECCERR2,Bank 2 SNECCERR2 flag clear bit" "0,1" newline bitfld.long 0x0 24. "CLR_RDSERR2,Bank 2 RDSERR2 flag clear bit" "0,1" bitfld.long 0x0 23. "CLR_RDPERR2,Bank 2 RDPERR2 flag clear bit" "0,1" newline bitfld.long 0x0 21. "CLR_INCERR2,Bank 2 INCERR2 flag clear bit" "0,1" bitfld.long 0x0 19. "CLR_STRBERR2,Bank 2 STRBERR2 flag clear bit" "0,1" newline bitfld.long 0x0 18. "CLR_PGSERR2,Bank 2 PGSERR2 flag clear bit" "0,1" bitfld.long 0x0 17. "CLR_WRPERR2,Bank 2 WRPERR2 flag clear bit" "0,1" newline bitfld.long 0x0 16. "CLR_EOP2,Bank 2 EOP2 flag clear bit" "0,1" group.long 0x118++0xB line.long 0x0 "FLASH_OPTCR_,FLASH option control register" rbitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 5. "PG_OTP,OTP program control bit" "0,1" bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "FLASH_OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "VDDIO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "WDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" bitfld.long 0x4 16. "VDDMMC_HSLV,IWDG Stop mode freeze option status" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" bitfld.long 0x4 7. "NRST_STDY,D1 DStandby entry reset option status" "0,1" newline bitfld.long 0x4 6. "NRST_STOP,D1 DStop entry reset option status" "0,1" bitfld.long 0x4 4. "IWDG_SW,IWDG1 control option status" "0,1" newline bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "FLASH_OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "VDDIO_HSLV,VDDIO_HSLV" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "WDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline bitfld.long 0x8 16. "VDDMMC_HSLV,VDDMMC_HSLV" "0,1" hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" newline bitfld.long 0x8 7. "NRST_STDY,Option byte erase after D1 DStandby" "0,1" bitfld.long 0x8 6. "NRST_STOP,Option byte erase after D1 DStop option" "0,1" newline bitfld.long 0x8 4. "IWDG_SW,IWDG1 option configuration" "0,1" bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "FLASH_OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "FLASH_PRAR_CUR2,FLASH protection address for bank 2" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 PCROP area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 PCROP area start status bits" group.long 0x12C++0x3 line.long 0x0 "FLASH_PRAR_PRG2,FLASH protection address for bank 2" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 PCROP area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 PCROP area start configuration bits" rgroup.long 0x130++0x3 line.long 0x0 "FLASH_SCAR_CUR2,FLASH secure address for bank 2" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 secure-only area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 secure-only area start status bits" group.long 0x134++0x3 line.long 0x0 "FLASH_SCAR_PRG2,FLASH secure address for bank 2" bitfld.long 0x0 31. "DMES2,Bank 2 secure access protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 secure-only area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 secure-only area start configuration bits" rgroup.long 0x138++0x3 line.long 0x0 "FLASH_WPSGN_CUR2R,FLASH write sector group protection for bank 2" hexmask.long 0x0 0.--31. 1. "WRPSGn2,Bank 2 sector group protection option status byte" group.long 0x13C++0x3 line.long 0x0 "FLASH_WPSGN_PRG2R,FLASH write sector group protection for bank 2" hexmask.long 0x0 0.--31. 1. "WRPSGn2,Bank 2 sector group protection option status byte" rgroup.long 0x140++0x7 line.long 0x0 "FLASH_BOOT_CURR_,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "FLASH_BOOT_PRGR_,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x150++0xB line.long 0x0 "FLASH_CRCCR2,FLASH CRC control register for bank 2" bitfld.long 0x0 22. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0: every burst has a size of 4 Flash words (128 bit),1: every burst has a size of 16 Flash words (128-bit),2: every burst has a size of 64 Flash words (128-bit),3: every burst has a size of 256 Flash words.." newline bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" newline bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear bit" "0,1" bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select bit" "0,1" newline bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CRC_SECT,Bank 2 CRC sector number" line.long 0x4 "FLASH_CRCSADD2R,FLASH CRC start address register for bank 2" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 2" line.long 0x8 "FLASH_CRCEADD2R,FLASH CRC end address register for bank 2" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "FLASH_ECC_FA2R,FLASH ECC fail address for bank 2" hexmask.long.word 0x0 0.--15. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x3 line.long 0x0 "FLASH_ACR,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" wgroup.long 0x4++0x7 line.long 0x0 "FLASH_KEYR1,FLASH key register for bank 1" hexmask.long 0x0 0.--31. 1. "KEY1R,Non-volatile memory bank 1 configuration access unlock key" line.long 0x4 "FLASH_OPTKEYR,FLASH option key register" hexmask.long 0x4 0.--31. 1. "OPTKEYR,Unlock key option bytes" group.long 0xC++0x3 line.long 0x0 "FLASH_CR1," bitfld.long 0x0 28. "CRCRDERRIE1,Bank 1 CRC read error interrupt enable bit" "0: no interrupt generated when a CRC read error..,1: interrupt generated when a CRC read error occurs.." bitfld.long 0x0 27. "CRCENDIE1,Bank 1 CRC end of calculation interrupt enable bit" "0: no interrupt generated when CRC computation..,1: interrupt generated when CRC computation.." newline bitfld.long 0x0 26. "DBECCERRIE1,Bank 1 ECC double detection error interrupt enable bit" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.." bitfld.long 0x0 25. "SNECCERRIE1,Bank 1 ECC single correction error interrupt enable bit" "0: no interrupt generated when an ECC single..,1: interrupt generated when an ECC single.." newline bitfld.long 0x0 24. "RDSERRIE1,Bank 1 secure error interrupt enable bit" "0: no interrupt generated when a secure error..,1: an interrupt is generated when a secure error.." bitfld.long 0x0 23. "RDPERRIE1,Bank 1 read protection error interrupt enable bit" "0: no interrupt generated when a read protection..,1: an interrupt is generated when a read protection.." newline bitfld.long 0x0 21. "INCERRIE1,Bank 1 inconsistency error interrupt enable bit" "0: no interrupt generated when a inconsistency..,1: interrupt generated when a inconsistency error.." bitfld.long 0x0 19. "STRBERRIE1,Bank 1 strobe error interrupt enable bit" "0: no interrupt generated when a strobe error..,1: interrupt generated when strobe error occurs on.." newline bitfld.long 0x0 18. "PGSERRIE1,Bank 1 programming sequence error interrupt enable bit" "0: no interrupt generated when a sequence error..,1: interrupt generated when sequence error occurs.." bitfld.long 0x0 17. "WRPERRIE1,Bank 1 write protection error interrupt enable bit" "0: no interrupt generated when a protection error..,1: interrupt generated when a protection error.." newline bitfld.long 0x0 16. "EOPIE1,Bank 1 end-of-program interrupt control bit" "0: no interrupt generated at the end of a program..,1: interrupt enabled when at the end of a program.." bitfld.long 0x0 15. "CRC_EN,Bank 1 CRC control bit" "0,1" newline hexmask.long.byte 0x0 6.--12. 1. "SSN1,Bank 1 sector erase selection number" bitfld.long 0x0 5. "START1,Bank 1 erase start control bit" "0,1" newline bitfld.long 0x0 4. "FW1,Bank 1 write forcing control bit" "0,1" bitfld.long 0x0 3. "BER1,Bank 1 erase request" "0: bank erase not requested on bank 1,1: bank erase requested on bank 1" newline bitfld.long 0x0 2. "SER1,Bank 1 sector erase request" "0: sector erase not requested on bank 1,1: sector erase requested on bank 1" bitfld.long 0x0 1. "PG1,Bank 1 internal buffer control bit" "0: Internal buffer disabled for write operations to..,1: Internal buffer enabled for write operations to.." newline bitfld.long 0x0 0. "LOCK1,Bank 1 configuration lock bit" "0: FLASH_CR1 register unlocked,1: FLASH_CR1 register locked" rgroup.long 0x10++0x3 line.long 0x0 "FLASH_SR1," bitfld.long 0x0 28. "CRCRDERR1,Bank 1 CRC read error flag" "0: no protected area detected inside address read..,1: a protected area has been detected inside.." bitfld.long 0x0 27. "CRCEND1,Bank 1 CRC end of calculation flag" "0: CRC computation not complete on bank 1,1: CRC computation complete on bank 1" newline bitfld.long 0x0 26. "DBECCERR1,Bank 1 ECC double detection error flag" "0: no ECC double detection error occurred on bank 1,1: ECC double detection error occurred on bank 1" bitfld.long 0x0 25. "SNECCERR1,Bank 1 single correction error flag" "0: no ECC single correction error occurs on bank 1,1: ECC single correction error occurs on bank 1" newline bitfld.long 0x0 24. "RDSERR1,Bank 1 secure error flag" "0: no secure error occurs on bank 1,1: a secure error occurs on bank 1" bitfld.long 0x0 23. "RDPERR1,Bank 1 read protection error flag" "0: no read protection error occurs on bank 1,1: a read protection error occurs on bank 1" newline bitfld.long 0x0 21. "INCERR1,Bank 1 inconsistency error flag" "0: no inconsistency error occurs on bank 1,1: a inconsistency error occurs on bank 1" bitfld.long 0x0 19. "STRBERR1,Bank 1 strobe error flag" "0: no strobe error occurs on bank 1,1: a strobe error occurs on bank 1" newline bitfld.long 0x0 18. "PGSERR1,Bank 1 programming sequence error flag" "0: no sequence error occurs on bank 1,1: a sequence error occurs on bank 1" bitfld.long 0x0 17. "WRPERR1,Bank 1 write protection error flag" "0: no write protection error occurs on bank 1,1: a write protection error occurs on bank 1" newline bitfld.long 0x0 16. "EOP1,Bank 1 end-of-program flag" "0: no programming operation completed on bank 1,1: a programming operation completed on bank 1" bitfld.long 0x0 3. "CRC_BUSY1,Bank 1 CRC busy flag" "0: no CRC calculation ongoing on bank 1,1: CRC calculation ongoing on bank 1" newline bitfld.long 0x0 2. "QW1,Bank 1 wait queue flag" "0: no write erase or option byte change operations..,1: at least one write erase or option byte change.." bitfld.long 0x0 1. "WBNE1,Bank 1 write buffer not empty flag" "0: write buffer of bank 1 empty or full,1: write buffer of bank 1 waiting data to complete" newline bitfld.long 0x0 0. "BSY1,Bank 1 busy flag" "0: no programming erase or option byte change..,1: programming erase or option byte change.." wgroup.long 0x14++0x3 line.long 0x0 "FLASH_CCR1," bitfld.long 0x0 28. "CLR_CRCRDERR1,Bank 1 CRCRDERR1 flag clear bit" "0,1" bitfld.long 0x0 27. "CLR_CRCEND1,Bank 1 CRCEND1 flag clear bit" "0,1" newline bitfld.long 0x0 26. "CLR_DBECCERR1,Bank 1 DBECCERR1 flag clear bit" "0,1" bitfld.long 0x0 25. "CLR_SNECCERR1,Bank 1 SNECCERR1 flag clear bit" "0,1" newline bitfld.long 0x0 24. "CLR_RDSERR1,Bank 1 RDSERR1 flag clear bit" "0,1" bitfld.long 0x0 23. "CLR_RDPERR1,Bank 1 RDPERR1 flag clear bit" "0,1" newline bitfld.long 0x0 21. "CLR_INCERR1,Bank 1 INCERR1 flag clear bit" "0,1" bitfld.long 0x0 19. "CLR_STRBERR1,Bank 1 STRBERR1 flag clear bit" "0,1" newline bitfld.long 0x0 18. "CLR_PGSERR1,Bank 1 PGSERR1 flag clear bit" "0,1" bitfld.long 0x0 17. "CLR_WRPERR1,Bank 1 WRPERR1 flag clear bit" "0,1" newline bitfld.long 0x0 16. "CLR_EOP1,Bank 1 EOP1 flag clear bit" "0,1" group.long 0x18++0xB line.long 0x0 "FLASH_OPTCR,FLASH option control register" rbitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 5. "PG_OTP,OTP program control bit" "0,1" bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "FLASH_OPTSR_CUR,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "VDDIO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "WDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" bitfld.long 0x4 16. "VDDMMC_HSLV,IWDG Stop mode freeze option status" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" bitfld.long 0x4 7. "NRST_STDY,D1 DStandby entry reset option status" "0,1" newline bitfld.long 0x4 6. "NRST_STOP,D1 DStop entry reset option status" "0,1" bitfld.long 0x4 4. "IWDG_SW,IWDG1 control option status" "0,1" newline bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "FLASH_OPTSR_PRG,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "VDDIO_HSLV,VDDIO_HSLV" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "WDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline bitfld.long 0x8 16. "VDDMMC_HSLV,VDDMMC_HSLV" "0,1" hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" newline bitfld.long 0x8 7. "NRST_STDY,Option byte erase after D1 DStandby" "0,1" bitfld.long 0x8 6. "NRST_STOP,Option byte erase after D1 DStop option" "0,1" newline bitfld.long 0x8 4. "IWDG_SW,IWDG1 option configuration" "0,1" bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x24++0x3 line.long 0x0 "FLASH_OPTCCR,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "FLASH_PRAR_CUR1,FLASH protection address for bank 1" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 PCROP area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 PCROP area start status bits" group.long 0x2C++0x3 line.long 0x0 "FLASH_PRAR_PRG1,FLASH protection address for bank 1" bitfld.long 0x0 31. "DMEP1,Bank 1 PCROP protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END1,Bank 1 PCROP area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START1,Bank 1 PCROP area start configuration bits" rgroup.long 0x30++0x3 line.long 0x0 "FLASH_SCAR_CUR1,FLASH secure address for bank 1" bitfld.long 0x0 31. "DMES1,Bank 1 secure access protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END1,Bank 1 secure-only area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START1,Bank 1 secure-only area start status bits" group.long 0x34++0x3 line.long 0x0 "FLASH_SCAR_PRG1,FLASH secure address for bank 1" bitfld.long 0x0 31. "DMES1,Bank 1 secure access protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END1,Bank 1 secure-only area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START1,Bank 1 secure-only area start configuration bits" rgroup.long 0x38++0x3 line.long 0x0 "FLASH_WPSGN_CUR1R,FLASH write sector group protection for bank 1" hexmask.long 0x0 0.--31. 1. "WRPSGn1,Bank 1 sector group protection option status byte" group.long 0x3C++0x3 line.long 0x0 "FLASH_WPSGN_PRG1R,FLASH write sector group protection for bank 1" hexmask.long 0x0 0.--31. 1. "WRPSGn1,Bank 1 sector group protection option status byte" rgroup.long 0x40++0x7 line.long 0x0 "FLASH_BOOT_CURR,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "FLASH_BOOT_PRGR,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x50++0xF line.long 0x0 "FLASH_CRCCR1,FLASH CRC control register for bank 1" bitfld.long 0x0 22. "ALL_BANK,Bank 1 CRC select bit" "0,1" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 1 CRC burst size" "0: every burst has a size of 4 Flash words (128-bit),1: every burst has a size of 16 Flash words (128-bit),2: every burst has a size of 64 Flash words (128-bit),3: every burst has a size of 256 Flash words.." newline bitfld.long 0x0 17. "CLEAN_CRC,Bank 1 CRC clear bit" "0,1" bitfld.long 0x0 16. "START_CRC,Bank 1 CRC start bit" "0,1" newline bitfld.long 0x0 10. "CLEAN_SECT,Bank 1 CRC sector list clear bit" "0,1" bitfld.long 0x0 9. "ADD_SECT,Bank 1 CRC sector select bit" "0,1" newline bitfld.long 0x0 8. "CRC_BY_SECT,Bank 1 CRC sector mode select bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CRC_SECT,Bank 1 CRC sector number" line.long 0x4 "FLASH_CRCSADD1R," hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 1" line.long 0x8 "FLASH_CRCEADD1R," hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 1" line.long 0xC "FLASH_CRCDATAR,FLASH CRC data register" hexmask.long 0xC 0.--31. 1. "CRC_DATA,CRC result" rgroup.long 0x60++0x3 line.long 0x0 "FLASH_ECC_FA1R," bitfld.long 0x0 31. "OTP_FAIL_ECC,OTP ECC error bit" "0,1" hexmask.long.word 0x0 0.--15. 1. "FAIL_ECC_ADDR1,Bank 1 ECC error address" rgroup.long 0x68++0x3 line.long 0x0 "FLASH_OTPBL_CUR,FLASH OTP block lock" hexmask.long.word 0x0 0.--15. 1. "LOCKBL,OTP Block Lock" group.long 0x6C++0x3 line.long 0x0 "FLASH_OTPBL_PRG,FLASH OTP block lock" hexmask.long.word 0x0 0.--15. 1. "LOCKBL,OTP Block Lock" group.long 0x100++0x3 line.long 0x0 "FLASH_ACR_,Access control register" bitfld.long 0x0 4.--5. "WRHIGHFREQ,Flash signal delay" "0,1,2,3" hexmask.long.byte 0x0 0.--3. 1. "LATENCY,Read latency" wgroup.long 0x104++0x3 line.long 0x0 "FLASH_KEYR2,FLASH key register for bank 2" hexmask.long 0x0 0.--31. 1. "KEY2R,Bank 2 access configuration unlock key" group.long 0x108++0x7 line.long 0x0 "FLASH_OPTKEYR_,FLASH option key register" hexmask.long 0x0 0.--31. 1. "OPTKEYR,Unlock key option bytes" line.long 0x4 "FLASH_CR2,FLASH control register for bank 2" bitfld.long 0x4 28. "CRCRDERRIE2,Bank 2 CRC read error interrupt enable bit" "0: no interrupt generated when a CRC read error..,1: interrupt generated when a CRC read error occurs.." bitfld.long 0x4 27. "CRCENDIE2,Bank 2 CRC end of calculation interrupt enable bit" "0: no interrupt generated when CRC computation..,1: interrupt generated when CRC computation.." newline bitfld.long 0x4 26. "DBECCERRIE2,Bank 2 ECC double detection error interrupt enable bit" "0: no interrupt generated when an ECC double..,1: interrupt generated if an ECC double detection.." bitfld.long 0x4 25. "SNECCERRIE2,Bank 2 ECC single correction error interrupt enable bit" "0: no interrupt generated when an ECC single..,1: interrupt generated when an ECC single.." newline bitfld.long 0x4 24. "RDSERRIE2,Bank 2 secure error interrupt enable bit" "0: no interrupt generated when a secure error..,1: an interrupt is generated when a secure error.." bitfld.long 0x4 23. "RDPERRIE2,Bank 2 read protection error interrupt enable bit" "0: no interrupt generated when a read protection..,1: an interrupt is generated when a read protection.." newline bitfld.long 0x4 21. "INCERRIE2,Bank 2 inconsistency error interrupt enable bit" "0: no interrupt generated when a inconsistency..,1: interrupt generated when a inconsistency error.." bitfld.long 0x4 19. "STRBERRIE2,Bank 2 strobe error interrupt enable bit" "0: no interrupt generated when a strobe error..,1: interrupt generated when strobe error occurs on.." newline bitfld.long 0x4 18. "PGSERRIE2,Bank 2 programming sequence error interrupt enable bit" "0: no interrupt generated when a sequence error..,1: interrupt generated when sequence error occurs.." bitfld.long 0x4 17. "WRPERRIE2,Bank 2 write protection error interrupt enable bit" "0: no interrupt generated when a protection error..,1: interrupt generated when a protection error.." newline bitfld.long 0x4 16. "EOPIE2,Bank 2 end-of-program interrupt control bit" "0: no interrupt generated at the end of a program..,1: interrupt enabled when at the end of a program.." bitfld.long 0x4 15. "CRC_EN,Bank 2 CRC control bit" "0,1" newline hexmask.long.byte 0x4 6.--12. 1. "SSN2,Bank 2 sector erase selection number" bitfld.long 0x4 5. "START2,Bank 2 erase start control bit" "0,1" newline bitfld.long 0x4 4. "FW2,Bank 2 write forcing control bit" "0,1" bitfld.long 0x4 3. "BER2,Bank 2 erase request" "0: bank erase not requested on bank 2,1: bank erase requested on bank 2" newline bitfld.long 0x4 2. "SER2,Bank 2 sector erase request" "0: sector erase not requested on bank 2,1: sector erase requested on bank 2" bitfld.long 0x4 1. "PG2,Bank 2 internal buffer control bit" "0,1" newline bitfld.long 0x4 0. "LOCK2,Bank 2 configuration lock bit" "0: FLASH_CR2 register unlocked,1: FLASH_CR2 register locked" rgroup.long 0x110++0x3 line.long 0x0 "FLASH_SR2,FLASH status register for bank 2" bitfld.long 0x0 28. "CRCRDERR2,Bank 2 CRC read error flag" "0: no protected area inside the address read by CRC..,1: a protected area inside the address read by CRC.." bitfld.long 0x0 27. "CRCEND2,Bank 2 CRC end of calculation flag" "0: CRC computation not complete on bank 2,1: CRC computation complete on bank 2" newline bitfld.long 0x0 26. "DBECCERR2,Bank 2 ECC double detection error flag" "0: no ECC double detection error occurs on bank 2,1: ECC double detection error occurs on bank 2" bitfld.long 0x0 25. "SNECCERR2,Bank 2 single correction error flag" "0: no ECC single correction error occurs on bank 2,1: ECC single correction error occurs on bank 2" newline bitfld.long 0x0 24. "RDSERR2,Bank 2 secure error flag" "0: no secure error occurs on bank 2,1: a secure error occurs on bank 2" bitfld.long 0x0 23. "RDPERR2,Bank 2 read protection error flag" "0: no read protection error occurs on bank 2,1: a read protection error occurs on bank 2" newline bitfld.long 0x0 21. "INCERR2,Bank 2 inconsistency error flag" "0: no inconsistency error occurred on bank 2,1: an inconsistency error occurred on bank 2." bitfld.long 0x0 19. "STRBERR2,Bank 2 strobe error flag" "0: no strobe error occurred on bank 2,1: a strobe error occurred on bank 2." newline bitfld.long 0x0 18. "PGSERR2,Bank 2 programming sequence error flag" "0: no sequence error occurred on bank 2,1: a sequence error occurred on bank 2." bitfld.long 0x0 17. "WRPERR2,Bank 2 write protection error flag" "0: no write protection error occurred on bank 2,1: a write protection error occurred on bank 2" newline bitfld.long 0x0 16. "EOP2,Bank 2 end-of-program flag" "0: no programming operation completed on bank 2,1: a programming operation completed on bank 2" bitfld.long 0x0 3. "CRC_BUSY2,Bank 2 CRC busy flag" "0: no CRC calculation ongoing on bank 2,1: CRC calculation ongoing on bank 2." newline bitfld.long 0x0 2. "QW2,Bank 2 wait queue flag" "0: no write or erase operation is waiting in the..,1: at least one write or erase operation is pending.." bitfld.long 0x0 1. "WBNE2,Bank 2 write buffer not empty flag" "0: write buffer of bank 2 empty or full,1: write buffer of bank 2 waiting data to complete" newline bitfld.long 0x0 0. "BSY2,Bank 2 busy flag" "0: no write or erase operation is executed on bank 2,1: a write or an erase operation is being executed.." wgroup.long 0x114++0x3 line.long 0x0 "FLASH_CCR2,FLASH clear control register for bank 2" bitfld.long 0x0 28. "CLR_CRCRDERR2,Bank 2 CRCRDERR2 flag clear bit" "0,1" bitfld.long 0x0 27. "CLR_CRCEND2,Bank 2 CRCEND2 flag clear bit" "0,1" newline bitfld.long 0x0 26. "CLR_DBECCERR2,Bank 2 DBECCERR2 flag clear bit" "0,1" bitfld.long 0x0 25. "CLR_SNECCERR2,Bank 2 SNECCERR2 flag clear bit" "0,1" newline bitfld.long 0x0 24. "CLR_RDSERR2,Bank 2 RDSERR2 flag clear bit" "0,1" bitfld.long 0x0 23. "CLR_RDPERR2,Bank 2 RDPERR2 flag clear bit" "0,1" newline bitfld.long 0x0 21. "CLR_INCERR2,Bank 2 INCERR2 flag clear bit" "0,1" bitfld.long 0x0 19. "CLR_STRBERR2,Bank 2 STRBERR2 flag clear bit" "0,1" newline bitfld.long 0x0 18. "CLR_PGSERR2,Bank 2 PGSERR2 flag clear bit" "0,1" bitfld.long 0x0 17. "CLR_WRPERR2,Bank 2 WRPERR2 flag clear bit" "0,1" newline bitfld.long 0x0 16. "CLR_EOP2,Bank 2 EOP2 flag clear bit" "0,1" group.long 0x118++0xB line.long 0x0 "FLASH_OPTCR_,FLASH option control register" rbitfld.long 0x0 31. "SWAP_BANK,Bank swapping configuration" "0,1" bitfld.long 0x0 30. "OPTCHANGEERRIE,Option byte change error interrupt" "0,1" newline bitfld.long 0x0 5. "PG_OTP,OTP program control bit" "0,1" bitfld.long 0x0 4. "MER,Flash mass erase enable" "0,1" newline bitfld.long 0x0 1. "OPTSTART,Option byte start change option" "0,1" bitfld.long 0x0 0. "OPTLOCK,FLASH_OPTCR lock option configuration" "0,1" line.long 0x4 "FLASH_OPTSR_CUR_,FLASH option status register" bitfld.long 0x4 31. "SWAP_BANK_OPT,Bank swapping option status" "0,1" bitfld.long 0x4 30. "OPTCHANGEERR,Option byte change error" "0,1" newline bitfld.long 0x4 29. "VDDIO_HSLV,I/O high-speed at low-voltage status bit" "0,1" bitfld.long 0x4 21. "SECURITY,Security enable option status" "0,1" newline bitfld.long 0x4 19.--20. "ST_RAM_SIZE,DTCM RAM size option" "0,1,2,3" bitfld.long 0x4 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option status" "0,1" newline bitfld.long 0x4 17. "WDG_FZ_STOP,IWDG Stop mode freeze option status" "0,1" bitfld.long 0x4 16. "VDDMMC_HSLV,IWDG Stop mode freeze option status" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RDP,Readout protection level option status" bitfld.long 0x4 7. "NRST_STDY,D1 DStandby entry reset option status" "0,1" newline bitfld.long 0x4 6. "NRST_STOP,D1 DStop entry reset option status" "0,1" bitfld.long 0x4 4. "IWDG_SW,IWDG1 control option status" "0,1" newline bitfld.long 0x4 2.--3. "BOR_LEV,Brownout level option status" "0,1,2,3" bitfld.long 0x4 0. "OPT_BUSY,Option byte change ongoing" "0,1" line.long 0x8 "FLASH_OPTSR_PRG_,FLASH option status register" bitfld.long 0x8 31. "SWAP_BANK_OPT,Bank swapping option configuration" "0,1" bitfld.long 0x8 29. "VDDIO_HSLV,VDDIO_HSLV" "0,1" newline bitfld.long 0x8 21. "SECURITY,Security option configuration" "0,1" bitfld.long 0x8 19.--20. "ST_RAM_SIZE,DTCM size select option configuration" "0,1,2,3" newline bitfld.long 0x8 18. "IWDG_FZ_SDBY,IWDG Standby mode freeze option" "0,1" bitfld.long 0x8 17. "WDG_FZ_STOP,IWDG Stop mode freeze option" "0,1" newline bitfld.long 0x8 16. "VDDMMC_HSLV,VDDMMC_HSLV" "0,1" hexmask.long.byte 0x8 8.--15. 1. "RDP,Readout protection level option" newline bitfld.long 0x8 7. "NRST_STDY,Option byte erase after D1 DStandby" "0,1" bitfld.long 0x8 6. "NRST_STOP,Option byte erase after D1 DStop option" "0,1" newline bitfld.long 0x8 4. "IWDG_SW,IWDG1 option configuration" "0,1" bitfld.long 0x8 2.--3. "BOR_LEV,BOR reset level option configuration" "0,1,2,3" wgroup.long 0x124++0x3 line.long 0x0 "FLASH_OPTCCR_,FLASH option clear control" bitfld.long 0x0 30. "CLR_OPTCHANGEERR,OPTCHANGEERR reset bit" "0,1" rgroup.long 0x128++0x3 line.long 0x0 "FLASH_PRAR_CUR2,FLASH protection address for bank 2" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 PCROP area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 PCROP area start status bits" group.long 0x12C++0x3 line.long 0x0 "FLASH_PRAR_PRG2,FLASH protection address for bank 2" bitfld.long 0x0 31. "DMEP2,Bank 2 PCROP protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "PROT_AREA_END2,Bank 2 PCROP area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "PROT_AREA_START2,Bank 2 PCROP area start configuration bits" rgroup.long 0x130++0x3 line.long 0x0 "FLASH_SCAR_CUR2,FLASH secure address for bank 2" bitfld.long 0x0 31. "DMES2,Bank 2 secure protected erase enable option status bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 secure-only area end status bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 secure-only area start status bits" group.long 0x134++0x3 line.long 0x0 "FLASH_SCAR_PRG2,FLASH secure address for bank 2" bitfld.long 0x0 31. "DMES2,Bank 2 secure access protected erase enable option configuration bit" "0,1" hexmask.long.word 0x0 16.--27. 1. "SEC_AREA_END2,Bank 2 secure-only area end configuration bits" newline hexmask.long.word 0x0 0.--11. 1. "SEC_AREA_START2,Bank 2 secure-only area start configuration bits" rgroup.long 0x138++0x3 line.long 0x0 "FLASH_WPSGN_CUR2R,FLASH write sector group protection for bank 2" hexmask.long 0x0 0.--31. 1. "WRPSGn2,Bank 2 sector group protection option status byte" group.long 0x13C++0x3 line.long 0x0 "FLASH_WPSGN_PRG2R,FLASH write sector group protection for bank 2" hexmask.long 0x0 0.--31. 1. "WRPSGn2,Bank 2 sector group protection option status byte" rgroup.long 0x140++0x7 line.long 0x0 "FLASH_BOOT_CURR_,FLASH register with boot" hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x0 0.--15. 1. "BOOT_ADD0,Boot address 0" line.long 0x4 "FLASH_BOOT_PRGR_,FLASH register with boot" hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot address 1" hexmask.long.word 0x4 0.--15. 1. "BOOT_ADD0,Boot address 0" group.long 0x150++0xB line.long 0x0 "FLASH_CRCCR2,FLASH CRC control register for bank 2" bitfld.long 0x0 22. "ALL_BANK,Bank 2 CRC select bit" "0,1" bitfld.long 0x0 20.--21. "CRC_BURST,Bank 2 CRC burst size" "0: every burst has a size of 4 Flash words (128 bit),1: every burst has a size of 16 Flash words (128-bit),2: every burst has a size of 64 Flash words (128-bit),3: every burst has a size of 256 Flash words.." newline bitfld.long 0x0 17. "CLEAN_CRC,Bank 2 CRC clear bit" "0,1" bitfld.long 0x0 16. "START_CRC,Bank 2 CRC start bit" "0,1" newline bitfld.long 0x0 10. "CLEAN_SECT,Bank 2 CRC sector list clear bit" "0,1" bitfld.long 0x0 9. "ADD_SECT,Bank 2 CRC sector select bit" "0,1" newline bitfld.long 0x0 8. "CRC_BY_SECT,Bank 2 CRC sector mode select bit" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CRC_SECT,Bank 2 CRC sector number" line.long 0x4 "FLASH_CRCSADD2R,FLASH CRC start address register for bank 2" hexmask.long.tbyte 0x4 2.--19. 1. "CRC_START_ADDR,CRC start address on bank 2" line.long 0x8 "FLASH_CRCEADD2R,FLASH CRC end address register for bank 2" hexmask.long.tbyte 0x8 2.--19. 1. "CRC_END_ADDR,CRC end address on bank 2" rgroup.long 0x160++0x3 line.long 0x0 "FLASH_ECC_FA2R,FLASH ECC fail address for bank 2" hexmask.long.word 0x0 0.--15. 1. "FAIL_ECC_ADDR2,Bank 2 ECC error address" endif tree.end sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "FMAC (Filter Math Accelerator)" base ad:0x48024000 group.long 0x0++0x13 line.long 0x0 "FMAC_X1BUFCFG,FMAC X1 buffer configuration register" bitfld.long 0x0 24.--25. "FULL_WM,Watermark for buffer full flag" "0: Threshold = 1,1: Threshold = 2,2: Threshold = 4,3: Threshold = 8" hexmask.long.byte 0x0 8.--15. 1. "X1_BUF_SIZE,Allocated size of X1 buffer in 16-bit words" newline hexmask.long.byte 0x0 0.--7. 1. "X1_BASE,Base address of X1 buffer" line.long 0x4 "FMAC_X2BUFCFG,FMAC X2 buffer configuration register" hexmask.long.byte 0x4 8.--15. 1. "X2_BUF_SIZE,Size of X2 buffer in 16-bit words" hexmask.long.byte 0x4 0.--7. 1. "X2_BASE,Base address of X2 buffer" line.long 0x8 "FMAC_YBUFCFG,FMAC Y buffer configuration register" bitfld.long 0x8 24.--25. "EMPTY_WM,Watermark for buffer empty flag" "0: Threshold = 1,1: Threshold = 2,2: Threshold = 4,3: Threshold = 8" hexmask.long.byte 0x8 8.--15. 1. "Y_BUF_SIZE,Size of Y buffer in 16-bit words" newline hexmask.long.byte 0x8 0.--7. 1. "Y_BASE,Base address of Y buffer" line.long 0xC "FMAC_PARAM,FMAC parameter register" bitfld.long 0xC 31. "START,Enable execution" "0: Stop execution,1: Start execution" hexmask.long.byte 0xC 24.--30. 1. "FUNC,Function" newline hexmask.long.byte 0xC 16.--23. 1. "R,Input parameter R." hexmask.long.byte 0xC 8.--15. 1. "Q,Input parameter Q." newline hexmask.long.byte 0xC 0.--7. 1. "P,Input parameter P." line.long 0x10 "FMAC_CR,FMAC control register" bitfld.long 0x10 16. "RESET,Reset FMAC unit" "0: Reset inactive,1: Reset active" bitfld.long 0x10 15. "CLIPEN,Enable clipping" "0: Clipping disabled. Values at the output of the..,1: Clipping enabled. Values at the output of the.." newline bitfld.long 0x10 9. "DMAWEN,Enable DMA write channel requests" "0: Disable. No DMA requests are generated,1: Enable. DMA requests are generated while the X1.." bitfld.long 0x10 8. "DMAREN,Enable DMA read channel requests" "0: Disable. No DMA requests are generated,1: Enable. DMA requests are generated while the Y.." newline bitfld.long 0x10 4. "SATIEN,Enable saturation error interrupts" "0: Disabled. No interrupts are generated upon..,1: Enabled. An interrupt request is generated if.." bitfld.long 0x10 3. "UNFLIEN,Enable underflow error interrupts" "0: Disabled. No interrupts are generated upon..,1: Enabled. An interrupt request is generated if.." newline bitfld.long 0x10 2. "OVFLIEN,Enable overflow error interrupts" "0: Disabled. No interrupts are generated upon..,1: Enabled. An interrupt request is generated if.." bitfld.long 0x10 1. "WIEN,Enable write interrupt" "0: Disabled. No write interrupt requests are..,1: Enabled. An interrupt request is generated while.." newline bitfld.long 0x10 0. "RIEN,Enable read interrupt" "0: Disabled. No read interrupt requests are..,1: Enabled. An interrupt request is generated while.." rgroup.long 0x14++0x3 line.long 0x0 "FMAC_SR,FMAC status register" bitfld.long 0x0 10. "SAT,Saturation error flag" "0: No saturation detected,1: Saturation detected. If the SATIEN bit is set an.." bitfld.long 0x0 9. "UNFL,Underflow error flag" "0: No underflow detected,1: Underflow detected. If the UNFLIEN bit is set an.." newline bitfld.long 0x0 8. "OVFL,Overflow error flag" "0: No overflow detected,1: Overflow detected. If the OVFLIEN bit is set an.." bitfld.long 0x0 1. "X1FULL,X1 buffer full flag" "0: X1 buffer not full. If the WIEN bit is set the..,1: X1 buffer full." newline bitfld.long 0x0 0. "YEMPTY,Y buffer empty flag" "0: Y buffer not empty. If the RIEN bit is set the..,1: Y buffer empty." wgroup.long 0x18++0x3 line.long 0x0 "FMAC_WDATA,FMAC write data register" hexmask.long.word 0x0 0.--15. 1. "WDATA,Write data" rgroup.long 0x1C++0x3 line.long 0x0 "FMAC_RDATA,FMAC read data register" hexmask.long.word 0x0 0.--15. 1. "RDATA,Read data" tree.end endif tree "FMC (Flexible Memory Controller)" base ad:0x52004000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x1F line.long 0x0 "BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H750*")) group.long 0x0++0x1F line.long 0x0 "FMC_BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "FMC_BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "FMC_BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "FMC_BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "FMC_BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "FMC_BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "FMC_BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "FMC_BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "FMC_PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "FMC_SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "FMC_PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "FMC_PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "FMC_ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "FMC_SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "FMC_SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "FMC_SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "FMC_SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "FMC_SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "FMC_SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "FMC_SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H753*")) group.long 0x0++0x1F line.long 0x0 "BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x1F line.long 0x0 "BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x1F line.long 0x0 "BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x1F line.long 0x0 "BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x1F line.long 0x0 "BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x1F line.long 0x0 "BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x0 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x8 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x10 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" bitfld.long 0x18 16.--18. "CPSIZE,CRAM Page Size These are used for" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "PCR,NAND Flash control registers" bitfld.long 0x0 17.--19. "ECCPS,ECC page size. These bits define the" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline bitfld.long 0x10 0.--2. "MODE,Command mode These bits define the" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x1F line.long 0x0 "FMC_BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "FMC_BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "FMC_BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x8 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "FMC_BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "FMC_BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x10 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "FMC_BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "FMC_BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x18 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "FMC_BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "FMC_PCR,NAND Flash control registers" hexmask.long.byte 0x0 17.--20. 1. "ECCPS,ECC page size. These bits define the" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "FMC_SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "FMC_PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "FMC_PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "FMC_ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "FMC_SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "FMC_SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "FMC_SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "FMC_SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "FMC_SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "MODE,Command mode These bits define the" line.long 0x14 "FMC_SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "FMC_SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x1F line.long 0x0 "FMC_BCR1,This register contains the control" bitfld.long 0x0 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x0 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x0 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x0 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x0 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x0 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x0 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x0 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x0 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x0 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x0 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x0 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x0 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x0 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x0 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x0 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x0 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x4 "FMC_BTR1,This register contains the control" bitfld.long 0x4 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x4 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x4 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x4 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x4 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x4 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x8 "FMC_BCR2,This register contains the control" bitfld.long 0x8 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x8 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x8 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x8 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x8 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x8 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x8 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x8 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x8 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x8 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x8 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x8 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x8 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x8 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x8 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x8 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x8 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x8 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0xC "FMC_BTR2,This register contains the control" bitfld.long 0xC 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0xC 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0xC 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0xC 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0xC 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0xC 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0xC 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x10 "FMC_BCR3,This register contains the control" bitfld.long 0x10 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x10 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x10 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x10 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x10 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x10 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x10 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x10 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x10 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x10 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x10 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x10 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x10 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x10 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x10 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x10 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x10 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x10 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x14 "FMC_BTR3,This register contains the control" bitfld.long 0x14 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x14 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x14 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x14 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x14 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x14 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x14 0.--3. 1. "ADDSET,Address setup phase duration These bits" line.long 0x18 "FMC_BCR4,This register contains the control" bitfld.long 0x18 31. "FMCEN,FMC controller Enable This bit" "0,1" bitfld.long 0x18 24.--25. "BMAP,FMC bank mapping These bits allows" "0,1,2,3" newline bitfld.long 0x18 21. "WFDIS,Write FIFO Disable This bit disables the" "0,1" bitfld.long 0x18 20. "CCLKEN,Continuous Clock Enable This bit enables" "0,1" newline bitfld.long 0x18 19. "CBURSTRW,Write burst enable For PSRAM (CRAM)" "0,1" hexmask.long.byte 0x18 16.--19. 1. "CPSIZE,CRAM Page Size These are used for" newline bitfld.long 0x18 15. "ASYNCWAIT,Wait signal during asynchronous" "0,1" bitfld.long 0x18 14. "EXTMOD,Extended mode enable. This bit enables" "0,1" newline bitfld.long 0x18 13. "WAITEN,Wait enable bit This bit" "0,1" bitfld.long 0x18 12. "WREN,Write enable bit This bit indicates" "0,1" newline bitfld.long 0x18 11. "WAITCFG,Wait timing configuration The NWAIT" "0,1" bitfld.long 0x18 9. "WAITPOL,Wait signal polarity bit This bit" "0,1" newline bitfld.long 0x18 8. "BURSTEN,Burst enable bit This bit" "0,1" bitfld.long 0x18 6. "FACCEN,Flash access enable This bit enables NOR" "0,1" newline bitfld.long 0x18 4.--5. "MWID,Memory data bus width Defines the" "0,1,2,3" bitfld.long 0x18 2.--3. "MTYP,Memory type These bits define the type" "0,1,2,3" newline bitfld.long 0x18 1. "MUXEN,Address/data multiplexing enable bit" "0,1" bitfld.long 0x18 0. "MBKEN,Memory bank enable bit This bit enables" "0,1" line.long 0x1C "FMC_BTR4,This register contains the control" bitfld.long 0x1C 28.--29. "ACCMOD,Access mode These bits specify the" "0,1,2,3" hexmask.long.byte 0x1C 24.--27. 1. "DATLAT,Data latency for synchronous memory For" newline hexmask.long.byte 0x1C 20.--23. 1. "CLKDIV,Clock divide ratio (for FMC_CLK signal)" hexmask.long.byte 0x1C 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x1C 8.--15. 1. "DATAST,Data-phase duration These bits are" hexmask.long.byte 0x1C 4.--7. 1. "ADDHLD,Address-hold phase duration These bits" newline hexmask.long.byte 0x1C 0.--3. 1. "ADDSET,Address setup phase duration These bits" group.long 0x80++0xF line.long 0x0 "FMC_PCR,NAND Flash control registers" hexmask.long.byte 0x0 17.--20. 1. "ECCPS,ECC page size. These bits define the" hexmask.long.byte 0x0 13.--16. 1. "TAR,ALE to RE delay. These bits set time" newline hexmask.long.byte 0x0 9.--12. 1. "TCLR,CLE to RE delay. These bits set time" bitfld.long 0x0 6. "ECCEN,ECC computation logic enable" "0,1" newline bitfld.long 0x0 4.--5. "PWID,Data bus width. These bits define the" "0,1,2,3" bitfld.long 0x0 2. "PBKEN,NAND Flash memory bank enable bit. This" "0,1" newline bitfld.long 0x0 1. "PWAITEN,Wait feature enable bit. This bit" "0,1" line.long 0x4 "FMC_SR,This register contains information about the" rbitfld.long 0x4 6. "FEMPT,FIFO empty. Read-only bit that provides" "0,1" bitfld.long 0x4 5. "IFEN,Interrupt falling edge detection enable" "0,1" newline bitfld.long 0x4 4. "ILEN,Interrupt high-level detection enable" "0,1" bitfld.long 0x4 3. "IREN,Interrupt rising edge detection enable" "0,1" newline bitfld.long 0x4 2. "IFS,Interrupt falling edge status The flag" "0,1" bitfld.long 0x4 1. "ILS,Interrupt high-level status The flag is" "0,1" newline bitfld.long 0x4 0. "IRS,Interrupt rising edge status The flag is" "0,1" line.long 0x8 "FMC_PMEM,The FMC_PMEM read/write register contains" hexmask.long.byte 0x8 24.--31. 1. "MEMHIZ,Common memory x data bus Hi-Z time These" hexmask.long.byte 0x8 16.--23. 1. "MEMHOLD,Common memory hold time These bits" newline hexmask.long.byte 0x8 8.--15. 1. "MEMWAIT,Common memory wait time These bits" hexmask.long.byte 0x8 0.--7. 1. "MEMSET,Common memory x setup time These bits" line.long 0xC "FMC_PATT,The FMC_PATT read/write register contains" hexmask.long.byte 0xC 24.--31. 1. "ATTHIZ,Attribute memory data bus Hi-Z time" hexmask.long.byte 0xC 16.--23. 1. "ATTHOLD,Attribute memory hold time These bits" newline hexmask.long.byte 0xC 8.--15. 1. "ATTWAIT,Attribute memory wait time These bits" hexmask.long.byte 0xC 0.--7. 1. "ATTSET,Attribute memory setup time These bits" rgroup.long 0x94++0x3 line.long 0x0 "FMC_ECCR,This register contain the current error" hexmask.long 0x0 0.--31. 1. "ECC,ECC result This field contains the value" group.long 0x104++0x3 line.long 0x0 "FMC_BWTR1,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x10C++0x3 line.long 0x0 "FMC_BWTR2,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x114++0x3 line.long 0x0 "FMC_BWTR3,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x11C++0x3 line.long 0x0 "FMC_BWTR4,This register contains the control" bitfld.long 0x0 28.--29. "ACCMOD,Access mode. These bits specify the" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "BUSTURN,Bus turnaround phase duration These bits" newline hexmask.long.byte 0x0 8.--15. 1. "DATAST,Data-phase duration. These bits are" hexmask.long.byte 0x0 4.--7. 1. "ADDHLD,Address-hold phase duration. These bits" newline hexmask.long.byte 0x0 0.--3. 1. "ADDSET,Address setup phase duration. These bits" group.long 0x140++0x17 line.long 0x0 "FMC_SDCR1,This register contains the control" bitfld.long 0x0 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x0 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x0 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x0 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x0 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x0 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x0 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x0 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x0 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x4 "FMC_SDCR2,This register contains the control" bitfld.long 0x4 13.--14. "RPIPE,Read pipe These bits define the delay " "0,1,2,3" bitfld.long 0x4 12. "RBURST,Burst read This bit enables burst read" "0,1" newline bitfld.long 0x4 10.--11. "SDCLK,SDRAM clock configuration These bits" "0,1,2,3" bitfld.long 0x4 9. "WP,Write protection This bit enables write" "0,1" newline bitfld.long 0x4 7.--8. "CAS,CAS Latency This bits sets the SDRAM CAS" "0,1,2,3" bitfld.long 0x4 6. "NB,Number of internal banks This bit sets" "0,1" newline bitfld.long 0x4 4.--5. "MWID,Memory data bus width. These bits define" "0,1,2,3" bitfld.long 0x4 2.--3. "NR,Number of row address bits These bits" "0,1,2,3" newline bitfld.long 0x4 0.--1. "NC,Number of column address bits These bits" "0,1,2,3" line.long 0x8 "FMC_SDTR1,This register contains the timing parameters" hexmask.long.byte 0x8 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0x8 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0x8 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0x8 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0x8 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0x8 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0x8 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0xC "FMC_SDTR2,This register contains the timing parameters" hexmask.long.byte 0xC 24.--27. 1. "TRCD,Row to column delay These bits define" hexmask.long.byte 0xC 20.--23. 1. "TRP,Row precharge delay These bits define" newline hexmask.long.byte 0xC 16.--19. 1. "TWR,Recovery delay These bits define the" hexmask.long.byte 0xC 12.--15. 1. "TRC,Row cycle delay These bits define the" newline hexmask.long.byte 0xC 8.--11. 1. "TRAS,Self refresh time These bits define the" hexmask.long.byte 0xC 4.--7. 1. "TXSR,Exit Self-refresh delay These bits" newline hexmask.long.byte 0xC 0.--3. 1. "TMRD,Load Mode Register to Active These bits" line.long 0x10 "FMC_SDCMR,This register contains the command issued" hexmask.long.word 0x10 9.--22. 1. "MRD,Mode Register definition This 14-bit" hexmask.long.byte 0x10 5.--8. 1. "NRFS,Number of Auto-refresh These bits define" newline bitfld.long 0x10 4. "CTB1,Command Target Bank 1 This bit indicates" "0,1" bitfld.long 0x10 3. "CTB2,Command Target Bank 2 This bit indicates" "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "MODE,Command mode These bits define the" line.long 0x14 "FMC_SDRTR,This register sets the refresh rate in" bitfld.long 0x14 14. "REIE,RES Interrupt Enable" "0,1" hexmask.long.word 0x14 1.--13. 1. "COUNT,Refresh Timer Count This 13-bit field" newline bitfld.long 0x14 0. "CRE,Clear Refresh error flag This bit is" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "FMC_SDSR,SDRAM Status register" bitfld.long 0x0 3.--4. "MODES2,Status Mode for Bank 2 These bits define" "0,1,2,3" bitfld.long 0x0 1.--2. "MODES1,Status Mode for Bank 1 These bits define" "0,1,2,3" newline bitfld.long 0x0 0. "RE,Refresh error flag An interrupt is" "0,1" endif tree.end tree "GPIO (General Purpose Inputs/Outputs)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOA" base ad:0x58020000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOB" base ad:0x58020400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOC" base ad:0x58020800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOD" base ad:0x58020C00 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOE" base ad:0x58021000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOF" base ad:0x58021400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOG" base ad:0x58021800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOH" base ad:0x58021C00 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H742*")) tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H743*")) tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H750*")) tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOJ" base ad:0x58022400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "GPIOK" base ad:0x58022800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif sif (cpuis("STM32H750*")) group.long 0x0++0xF line.long 0x0 "GPIO_MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "GPIO_OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "GPIO_OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "GPIO_PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "GPIO_IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "GPIO_ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "GPIO_BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "GPIO_LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "GPIO_AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "GPIO_AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" newline hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" endif tree.end endif sif (cpuis("STM32H753*")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H7A3*")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H7B0*")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif sif (cpuis("STM32H7B3*")) tree "GPIOA" base ad:0x58020000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOB" base ad:0x58020400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOC" base ad:0x58020800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOD" base ad:0x58020C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOE" base ad:0x58021000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOF" base ad:0x58021400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOG" base ad:0x58021800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOH" base ad:0x58021C00 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOI" base ad:0x58022000 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOJ" base ad:0x58022400 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end tree "GPIOK" base ad:0x58022800 group.long 0x0++0xF line.long 0x0 "MODER,GPIO port mode register" bitfld.long 0x0 30.--31. "MODE15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 28.--29. "MODE14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 26.--27. "MODE13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 24.--25. "MODE12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 22.--23. "MODE11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 20.--21. "MODE10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 18.--19. "MODE9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 16.--17. "MODE8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 14.--15. "MODE7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 12.--13. "MODE6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x0 10.--11. "MODE5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 8.--9. "MODE4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 6.--7. "MODE3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 4.--5. "MODE2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 2.--3. "MODE1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x0 0.--1. "MODE0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0x4 "OTYPER,GPIO port output type register" bitfld.long 0x4 15. "OT15,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 14. "OT14,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 13. "OT13,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 12. "OT12,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 11. "OT11,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 10. "OT10,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 9. "OT9,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 8. "OT8,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 7. "OT7,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 6. "OT6,Port x configuration bits (y = 0..15)" "0,1" newline bitfld.long 0x4 5. "OT5,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 4. "OT4,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 3. "OT3,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 2. "OT2,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 1. "OT1,Port x configuration bits (y = 0..15)" "0,1" bitfld.long 0x4 0. "OT0,Port x configuration bits (y = 0..15)" "0,1" line.long 0x8 "OSPEEDR,GPIO port output speed" bitfld.long 0x8 30.--31. "OSPEED15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 28.--29. "OSPEED14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 26.--27. "OSPEED13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 24.--25. "OSPEED12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 22.--23. "OSPEED11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 20.--21. "OSPEED10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 18.--19. "OSPEED9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 16.--17. "OSPEED8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 14.--15. "OSPEED7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 12.--13. "OSPEED6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0x8 10.--11. "OSPEED5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 8.--9. "OSPEED4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 6.--7. "OSPEED3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 4.--5. "OSPEED2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 2.--3. "OSPEED1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0x8 0.--1. "OSPEED0,[1:0]: Port x configuration bits (y =" "0,1,2,3" line.long 0xC "PUPDR,GPIO port pull-up/pull-down" bitfld.long 0xC 30.--31. "PUPD15,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 28.--29. "PUPD14,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 26.--27. "PUPD13,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 24.--25. "PUPD12,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 22.--23. "PUPD11,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 20.--21. "PUPD10,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 18.--19. "PUPD9,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 16.--17. "PUPD8,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 14.--15. "PUPD7,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 12.--13. "PUPD6,[1:0]: Port x configuration bits (y =" "0,1,2,3" newline bitfld.long 0xC 10.--11. "PUPD5,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 8.--9. "PUPD4,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 6.--7. "PUPD3,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 4.--5. "PUPD2,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 2.--3. "PUPD1,[1:0]: Port x configuration bits (y =" "0,1,2,3" bitfld.long 0xC 0.--1. "PUPD0,[1:0]: Port x configuration bits (y =" "0,1,2,3" rgroup.long 0x10++0x3 line.long 0x0 "IDR,GPIO port input data register" bitfld.long 0x0 15. "ID15,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 14. "ID14,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 13. "ID13,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 12. "ID12,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 11. "ID11,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 10. "ID10,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 9. "ID9,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 8. "ID8,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 7. "ID7,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 6. "ID6,Port input data bit (y = 0..15) These" "0,1" newline bitfld.long 0x0 5. "ID5,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 4. "ID4,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 3. "ID3,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 2. "ID2,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 1. "ID1,Port input data bit (y = 0..15) These" "0,1" bitfld.long 0x0 0. "ID0,Port input data bit (y = 0..15) These" "0,1" group.long 0x14++0x3 line.long 0x0 "ODR,GPIO port output data register" bitfld.long 0x0 15. "OD15,Port output data bit These bits can be" "0,1" bitfld.long 0x0 14. "OD14,Port output data bit These bits can be" "0,1" bitfld.long 0x0 13. "OD13,Port output data bit These bits can be" "0,1" bitfld.long 0x0 12. "OD12,Port output data bit These bits can be" "0,1" bitfld.long 0x0 11. "OD11,Port output data bit These bits can be" "0,1" bitfld.long 0x0 10. "OD10,Port output data bit These bits can be" "0,1" bitfld.long 0x0 9. "OD9,Port output data bit These bits can be" "0,1" bitfld.long 0x0 8. "OD8,Port output data bit These bits can be" "0,1" bitfld.long 0x0 7. "OD7,Port output data bit These bits can be" "0,1" bitfld.long 0x0 6. "OD6,Port output data bit These bits can be" "0,1" newline bitfld.long 0x0 5. "OD5,Port output data bit These bits can be" "0,1" bitfld.long 0x0 4. "OD4,Port output data bit These bits can be" "0,1" bitfld.long 0x0 3. "OD3,Port output data bit These bits can be" "0,1" bitfld.long 0x0 2. "OD2,Port output data bit These bits can be" "0,1" bitfld.long 0x0 1. "OD1,Port output data bit These bits can be" "0,1" bitfld.long 0x0 0. "OD0,Port output data bit These bits can be" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "BSRR,GPIO port bit set/reset" bitfld.long 0x0 31. "BR15,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 30. "BR14,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 29. "BR13,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 28. "BR12,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 27. "BR11,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 26. "BR10,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 25. "BR9,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 24. "BR8,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 23. "BR7,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 22. "BR6,Port x reset bit y (y = 0..15) These" "0,1" newline bitfld.long 0x0 21. "BR5,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 20. "BR4,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 19. "BR3,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 18. "BR2,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 17. "BR1,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 16. "BR0,Port x reset bit y (y = 0..15) These" "0,1" bitfld.long 0x0 15. "BS15,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "BS14,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "BS13,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "BS12,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 11. "BS11,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "BS10,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "BS9,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "BS8,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "BS7,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 6. "BS6,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "BS5,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "BS4,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "BS3,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "BS2,Port x set bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 1. "BS1,Port x set bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "BS0,Port x set bit y (y= 0..15) These bits" "0,1" group.long 0x1C++0xB line.long 0x0 "LCKR,This register is used to lock the" bitfld.long 0x0 16. "LCKK,Lock key This bit can be read any time." "0,1" bitfld.long 0x0 15. "LCK15,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 14. "LCK14,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 13. "LCK13,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 12. "LCK12,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 11. "LCK11,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 10. "LCK10,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 9. "LCK9,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 8. "LCK8,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 7. "LCK7,Port x lock bit y (y= 0..15) These bits" "0,1" newline bitfld.long 0x0 6. "LCK6,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 5. "LCK5,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 4. "LCK4,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 3. "LCK3,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 2. "LCK2,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 1. "LCK1,Port x lock bit y (y= 0..15) These bits" "0,1" bitfld.long 0x0 0. "LCK0,Port x lock bit y (y= 0..15) These bits" "0,1" line.long 0x4 "AFRL,GPIO alternate function low" hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,[3:0]: Alternate function selection for" hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,[3:0]: Alternate function selection for" line.long 0x8 "AFRH,GPIO alternate function high" hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,[3:0]: Alternate function selection for" hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,[3:0]: Alternate function selection for" tree.end endif tree.end sif (cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "HASH (HASH Hardware Accelerator)" base ad:0x48021400 group.long 0x0++0xB line.long 0x0 "CR,control register" bitfld.long 0x0 18. "ALGO1,ALGO" "0,1" bitfld.long 0x0 16. "LKEY,Long key selection" "0,1" bitfld.long 0x0 13. "MDMAT,Multiple DMA Transfers" "0,1" rbitfld.long 0x0 12. "DINNE,DIN not empty" "0,1" hexmask.long.byte 0x0 8.--11. 1. "NBW,Number of words already" bitfld.long 0x0 7. "ALGO0,Algorithm selection" "0,1" bitfld.long 0x0 6. "MODE,Mode selection" "0,1" bitfld.long 0x0 4.--5. "DATATYPE,Data type selection" "0,1,2,3" bitfld.long 0x0 3. "DMAE,DMA enable" "0,1" bitfld.long 0x0 2. "INIT,Initialize message digest" "0,1" line.long 0x4 "DIN,data input register" hexmask.long 0x4 0.--31. 1. "DATAIN,Data input" line.long 0x8 "STR,start register" bitfld.long 0x8 8. "DCAL,Digest calculation" "0,1" hexmask.long.byte 0x8 0.--4. 1. "NBLW,Number of valid bits in the last word of" rgroup.long 0xC++0x13 line.long 0x0 "HR0,digest registers" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HR1,digest registers" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HR2,digest registers" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HR3,digest registers" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HR4,digest registers" hexmask.long 0x10 0.--31. 1. "H4,H4" group.long 0x20++0x7 line.long 0x0 "IMR,interrupt enable register" bitfld.long 0x0 1. "DCIE,Digest calculation completion interrupt" "0,1" bitfld.long 0x0 0. "DINIE,Data input interrupt" "0,1" line.long 0x4 "SR,status register" rbitfld.long 0x4 3. "BUSY,Busy bit" "0,1" rbitfld.long 0x4 2. "DMAS,DMA Status" "0,1" bitfld.long 0x4 1. "DCIS,Digest calculation completion interrupt" "0,1" bitfld.long 0x4 0. "DINIS,Data input interrupt" "0,1" group.long 0xF8++0xD7 line.long 0x0 "CSR0,context swap registers" hexmask.long 0x0 0.--31. 1. "CSR0,CSR0" line.long 0x4 "CSR1,context swap registers" hexmask.long 0x4 0.--31. 1. "CSR1,CSR1" line.long 0x8 "CSR2,context swap registers" hexmask.long 0x8 0.--31. 1. "CSR2,CSR2" line.long 0xC "CSR3,context swap registers" hexmask.long 0xC 0.--31. 1. "CSR3,CSR3" line.long 0x10 "CSR4,context swap registers" hexmask.long 0x10 0.--31. 1. "CSR4,CSR4" line.long 0x14 "CSR5,context swap registers" hexmask.long 0x14 0.--31. 1. "CSR5,CSR5" line.long 0x18 "CSR6,context swap registers" hexmask.long 0x18 0.--31. 1. "CSR6,CSR6" line.long 0x1C "CSR7,context swap registers" hexmask.long 0x1C 0.--31. 1. "CSR7,CSR7" line.long 0x20 "CSR8,context swap registers" hexmask.long 0x20 0.--31. 1. "CSR8,CSR8" line.long 0x24 "CSR9,context swap registers" hexmask.long 0x24 0.--31. 1. "CSR9,CSR9" line.long 0x28 "CSR10,context swap registers" hexmask.long 0x28 0.--31. 1. "CSR10,CSR10" line.long 0x2C "CSR11,context swap registers" hexmask.long 0x2C 0.--31. 1. "CSR11,CSR11" line.long 0x30 "CSR12,context swap registers" hexmask.long 0x30 0.--31. 1. "CSR12,CSR12" line.long 0x34 "CSR13,context swap registers" hexmask.long 0x34 0.--31. 1. "CSR13,CSR13" line.long 0x38 "CSR14,context swap registers" hexmask.long 0x38 0.--31. 1. "CSR14,CSR14" line.long 0x3C "CSR15,context swap registers" hexmask.long 0x3C 0.--31. 1. "CSR15,CSR15" line.long 0x40 "CSR16,context swap registers" hexmask.long 0x40 0.--31. 1. "CSR16,CSR16" line.long 0x44 "CSR17,context swap registers" hexmask.long 0x44 0.--31. 1. "CSR17,CSR17" line.long 0x48 "CSR18,context swap registers" hexmask.long 0x48 0.--31. 1. "CSR18,CSR18" line.long 0x4C "CSR19,context swap registers" hexmask.long 0x4C 0.--31. 1. "CSR19,CSR19" line.long 0x50 "CSR20,context swap registers" hexmask.long 0x50 0.--31. 1. "CSR20,CSR20" line.long 0x54 "CSR21,context swap registers" hexmask.long 0x54 0.--31. 1. "CSR21,CSR21" line.long 0x58 "CSR22,context swap registers" hexmask.long 0x58 0.--31. 1. "CSR22,CSR22" line.long 0x5C "CSR23,context swap registers" hexmask.long 0x5C 0.--31. 1. "CSR23,CSR23" line.long 0x60 "CSR24,context swap registers" hexmask.long 0x60 0.--31. 1. "CSR24,CSR24" line.long 0x64 "CSR25,context swap registers" hexmask.long 0x64 0.--31. 1. "CSR25,CSR25" line.long 0x68 "CSR26,context swap registers" hexmask.long 0x68 0.--31. 1. "CSR26,CSR26" line.long 0x6C "CSR27,context swap registers" hexmask.long 0x6C 0.--31. 1. "CSR27,CSR27" line.long 0x70 "CSR28,context swap registers" hexmask.long 0x70 0.--31. 1. "CSR28,CSR28" line.long 0x74 "CSR29,context swap registers" hexmask.long 0x74 0.--31. 1. "CSR29,CSR29" line.long 0x78 "CSR30,context swap registers" hexmask.long 0x78 0.--31. 1. "CSR30,CSR30" line.long 0x7C "CSR31,context swap registers" hexmask.long 0x7C 0.--31. 1. "CSR31,CSR31" line.long 0x80 "CSR32,context swap registers" hexmask.long 0x80 0.--31. 1. "CSR32,CSR32" line.long 0x84 "CSR33,context swap registers" hexmask.long 0x84 0.--31. 1. "CSR33,CSR33" line.long 0x88 "CSR34,context swap registers" hexmask.long 0x88 0.--31. 1. "CSR34,CSR34" line.long 0x8C "CSR35,context swap registers" hexmask.long 0x8C 0.--31. 1. "CSR35,CSR35" line.long 0x90 "CSR36,context swap registers" hexmask.long 0x90 0.--31. 1. "CSR36,CSR36" line.long 0x94 "CSR37,context swap registers" hexmask.long 0x94 0.--31. 1. "CSR37,CSR37" line.long 0x98 "CSR38,context swap registers" hexmask.long 0x98 0.--31. 1. "CSR38,CSR38" line.long 0x9C "CSR39,context swap registers" hexmask.long 0x9C 0.--31. 1. "CSR39,CSR39" line.long 0xA0 "CSR40,context swap registers" hexmask.long 0xA0 0.--31. 1. "CSR40,CSR40" line.long 0xA4 "CSR41,context swap registers" hexmask.long 0xA4 0.--31. 1. "CSR41,CSR41" line.long 0xA8 "CSR42,context swap registers" hexmask.long 0xA8 0.--31. 1. "CSR42,CSR42" line.long 0xAC "CSR43,context swap registers" hexmask.long 0xAC 0.--31. 1. "CSR43,CSR43" line.long 0xB0 "CSR44,context swap registers" hexmask.long 0xB0 0.--31. 1. "CSR44,CSR44" line.long 0xB4 "CSR45,context swap registers" hexmask.long 0xB4 0.--31. 1. "CSR45,CSR45" line.long 0xB8 "CSR46,context swap registers" hexmask.long 0xB8 0.--31. 1. "CSR46,CSR46" line.long 0xBC "CSR47,context swap registers" hexmask.long 0xBC 0.--31. 1. "CSR47,CSR47" line.long 0xC0 "CSR48,context swap registers" hexmask.long 0xC0 0.--31. 1. "CSR48,CSR48" line.long 0xC4 "CSR49,context swap registers" hexmask.long 0xC4 0.--31. 1. "CSR49,CSR49" line.long 0xC8 "CSR50,context swap registers" hexmask.long 0xC8 0.--31. 1. "CSR50,CSR50" line.long 0xCC "CSR51,context swap registers" hexmask.long 0xCC 0.--31. 1. "CSR51,CSR51" line.long 0xD0 "CSR52,context swap registers" hexmask.long 0xD0 0.--31. 1. "CSR52,CSR52" line.long 0xD4 "CSR53,context swap registers" hexmask.long 0xD4 0.--31. 1. "CSR53,CSR53" rgroup.long 0x310++0x1F line.long 0x0 "HASH_HR0,HASH digest register" hexmask.long 0x0 0.--31. 1. "H0,H0" line.long 0x4 "HASH_HR1,read-only" hexmask.long 0x4 0.--31. 1. "H1,H1" line.long 0x8 "HASH_HR2,read-only" hexmask.long 0x8 0.--31. 1. "H2,H2" line.long 0xC "HASH_HR3,read-only" hexmask.long 0xC 0.--31. 1. "H3,H3" line.long 0x10 "HASH_HR4,read-only" hexmask.long 0x10 0.--31. 1. "H4,H4" line.long 0x14 "HASH_HR5,read-only" hexmask.long 0x14 0.--31. 1. "H5,H5" line.long 0x18 "HASH_HR6,read-only" hexmask.long 0x18 0.--31. 1. "H6,H6" line.long 0x1C "HASH_HR7,read-only" hexmask.long 0x1C 0.--31. 1. "H7,H7" tree.end endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "HRTIM (High-Resolution Timer)" base ad:0x0 sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "HRTIM_Master" base ad:0x40017400 group.long 0x0++0x3 line.long 0x0 "MCR,Master Timer Control Register" bitfld.long 0x0 30.--31. "BRSTDMA,Burst DMA Update" "0,1,2,3" bitfld.long 0x0 29. "MREPU,Master Timer Repetition" "0,1" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 21. "TECEN,Timer E counter enable" "0,1" bitfld.long 0x0 20. "TDCEN,Timer D counter enable" "0,1" bitfld.long 0x0 19. "TCCEN,Timer C counter enable" "0,1" bitfld.long 0x0 18. "TBCEN,Timer B counter enable" "0,1" bitfld.long 0x0 17. "TACEN,Timer A counter enable" "0,1" bitfld.long 0x0 16. "MCEN,Master Counter enable" "0,1" newline bitfld.long 0x0 14.--15. "SYNC_SRC,Synchronization source" "0,1,2,3" bitfld.long 0x0 12.--13. "SYNC_OUT,Synchronization output" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTM,Synchronization Starts" "0,1" bitfld.long 0x0 10. "SYNCRSTM,Synchronization Resets" "0,1" bitfld.long 0x0 8.--9. "SYNC_IN,ynchronization input" "0,1,2,3" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" bitfld.long 0x0 4. "RETRIG,Master Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Master Continuous mode" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--3. 1. "CK_PSC,HRTIM Master Clock" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 0.--2. "CK_PSC,HRTIM Master Clock" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4++0x3 line.long 0x0 "MISR,Master Timer Interrupt Status" bitfld.long 0x0 6. "MUPD,Master Update Interrupt" "0,1" bitfld.long 0x0 5. "SYNC,Sync Input Interrupt Flag" "0,1" bitfld.long 0x0 4. "MREP,Master Repetition Interrupt" "0,1" bitfld.long 0x0 3. "MCMP4,Master Compare 4 Interrupt" "0,1" bitfld.long 0x0 2. "MCMP3,Master Compare 3 Interrupt" "0,1" bitfld.long 0x0 1. "MCMP2,Master Compare 2 Interrupt" "0,1" bitfld.long 0x0 0. "MCMP1,Master Compare 1 Interrupt" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "MICR,Master Timer Interrupt Clear" bitfld.long 0x0 6. "MUPDC,Master update Interrupt flag" "0,1" bitfld.long 0x0 5. "SYNCC,Sync Input Interrupt flag" "0,1" bitfld.long 0x0 4. "MREPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "MCMP4C,Master Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "MCMP3C,Master Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "MCMP2C,Master Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "MCMP1C,Master Compare 1 Interrupt flag" "0,1" group.long 0xC++0x13 line.long 0x0 "MDIER4,MDIER4" bitfld.long 0x0 22. "MUPDDE,MUPDDE" "0,1" bitfld.long 0x0 21. "SYNCDE,SYNCDE" "0,1" bitfld.long 0x0 20. "MREPDE,MREPDE" "0,1" bitfld.long 0x0 19. "MCMP4DE,MCMP4DE" "0,1" bitfld.long 0x0 18. "MCMP3DE,MCMP3DE" "0,1" bitfld.long 0x0 17. "MCMP2DE,MCMP2DE" "0,1" bitfld.long 0x0 16. "MCMP1DE,MCMP1DE" "0,1" bitfld.long 0x0 6. "MUPDIE,MUPDIE" "0,1" bitfld.long 0x0 5. "SYNCIE,SYNCIE" "0,1" bitfld.long 0x0 4. "MREPIE,MREPIE" "0,1" newline bitfld.long 0x0 3. "MCMP4IE,MCMP4IE" "0,1" bitfld.long 0x0 2. "MCMP3IE,MCMP3IE" "0,1" bitfld.long 0x0 1. "MCMP2IE,MCMP2IE" "0,1" bitfld.long 0x0 0. "MCMP1IE,MCMP1IE" "0,1" line.long 0x4 "MCNTR,Master Timer Counter Register" hexmask.long.word 0x4 0.--15. 1. "MCNT,Counter value" line.long 0x8 "MPER,Master Timer Period Register" hexmask.long.word 0x8 0.--15. 1. "MPER,Master Timer Period value" line.long 0xC "MREP,Master Timer Repetition" hexmask.long.byte 0xC 0.--7. 1. "MREP,Master Timer Repetition counter" line.long 0x10 "MCMP1R,Master Timer Compare 1" hexmask.long.word 0x10 0.--15. 1. "MCMP1,Master Timer Compare 1" group.long 0x24++0xB line.long 0x0 "MCMP2R,Master Timer Compare 2" hexmask.long.word 0x0 0.--15. 1. "MCMP2,Master Timer Compare 2" line.long 0x4 "MCMP3R,Master Timer Compare 3" hexmask.long.word 0x4 0.--15. 1. "MCMP3,Master Timer Compare 3" line.long 0x8 "MCMP4R,Master Timer Compare 4" hexmask.long.word 0x8 0.--15. 1. "MCMP4,Master Timer Compare 4" tree.end endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "HRTIM_TIMA" base ad:0x40017480 group.long 0x0++0x3 line.long 0x0 "TIMACR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4++0x3 line.long 0x0 "TIMAISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMAICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMADIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTAR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERAR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPAR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1AR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CAR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2AR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3AR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4AR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1AR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2AR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTAR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETA1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTA1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETA2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTA2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFAR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFAR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTAR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 24. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 23. "TIMCCMP2,Timer C Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 21. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 20. "TIMBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x1C 19. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPAR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" endif hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1ACR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2ACR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTAR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTAR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "HRTIM_TIMB" base ad:0x40017500 group.long 0x0++0x3 line.long 0x0 "TIMBCR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4++0x3 line.long 0x0 "TIMBISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMBICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMBDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERBR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPBR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1BR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CBR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2BR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3BR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4BR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1BR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2BR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTBR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETB1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTB1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETB2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTB2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFBR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFBR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTBR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 24. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 23. "TIMCCMP2,Timer C Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPBR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" endif hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1BCR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2BCR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTBR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTBR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "HRTIM_TIMC" base ad:0x40017580 group.long 0x0++0x3 line.long 0x0 "TIMCCR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4++0x3 line.long 0x0 "TIMCISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMCICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMCDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTCR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERCR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPCR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1CR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CCR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2CR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3CR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4CR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1CR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2CR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTCR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETC1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTC1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETC2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTC2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFCR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFCR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTCR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPCR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" endif hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1CCR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2CCR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTCR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTCR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "HRTIM_TIMD" base ad:0x40017600 group.long 0x0++0x3 line.long 0x0 "TIMDCR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4++0x3 line.long 0x0 "TIMDISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMDICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMDDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTDR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERDR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPDR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1DR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CDR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2DR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3DR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4DR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1DR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2DR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTDR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETD1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTD1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETD2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTD2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFDR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFDR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTDR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 26. "TIMCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x1C 25. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPDR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" endif hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1DCR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2DCR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTDR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTDR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "HRTIM_TIME" base ad:0x40017680 group.long 0x0++0x3 line.long 0x0 "TIMECR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 0.--2. "CK_PSCx,HRTIM Timer x Clock" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4++0x3 line.long 0x0 "TIMEISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMEICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMEDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTER,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERER,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPER,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1ER,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CER,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2ER,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3ER,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4ER,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1ER,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2ER,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTER,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 10.--12. "DTPRSC,Deadtime Prescaler" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETE1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTE1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETE2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTE2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFER1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFER2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTER,TimerA Reset Register" bitfld.long 0x1C 30. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 29. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 28. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 27. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 26. "TIMCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x1C 25. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPER,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x20 4.--6. "CHPDTY,Timerx chopper duty cycle" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" endif hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1ECR,Timerx Capture 2 Control" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2ECR,CPT2xCR" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTER,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x2C 10.--12. "DLYPRT,Delayed Protection" "0,1,2,3,4,5,6,7" newline endif bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTER,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end endif sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "HRTIM_Common" base ad:0x40017780 group.long 0x0++0x13 line.long 0x0 "CR1,Control Register 1" sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 25.--27. "AD4USRC,ADC Trigger 4 Update" "0,1,2,3,4,5,6,7" bitfld.long 0x0 22.--24. "AD3USRC,ADC Trigger 3 Update" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19.--21. "AD2USRC,ADC Trigger 2 Update" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. "AD1USRC,ADC Trigger 1 Update" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 25.--28. 1. "AD4USRC,ADC Trigger 4 Update" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 22.--25. 1. "AD3USRC,ADC Trigger 3 Update" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 19.--22. 1. "AD2USRC,ADC Trigger 2 Update" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 16.--19. 1. "AD1USRC,ADC Trigger 1 Update" endif bitfld.long 0x0 5. "TEUDIS,Timer E Update Disable" "0,1" newline bitfld.long 0x0 4. "TDUDIS,Timer D Update Disable" "0,1" bitfld.long 0x0 3. "TCUDIS,Timer C Update Disable" "0,1" bitfld.long 0x0 2. "TBUDIS,Timer B Update Disable" "0,1" bitfld.long 0x0 1. "TAUDIS,Timer A Update Disable" "0,1" bitfld.long 0x0 0. "MUDIS,Master Update Disable" "0,1" line.long 0x4 "CR2,Control Register 2" bitfld.long 0x4 13. "TERST,Timer E counter software" "0,1" bitfld.long 0x4 12. "TDRST,Timer D counter software" "0,1" bitfld.long 0x4 11. "TCRST,Timer C counter software" "0,1" bitfld.long 0x4 10. "TBRST,Timer B counter software" "0,1" bitfld.long 0x4 9. "TARST,Timer A counter software" "0,1" bitfld.long 0x4 8. "MRST,Master Counter software" "0,1" bitfld.long 0x4 5. "TESWU,Timer E Software Update" "0,1" bitfld.long 0x4 4. "TDSWU,Timer D Software Update" "0,1" bitfld.long 0x4 3. "TCSWU,Timer C Software Update" "0,1" newline bitfld.long 0x4 2. "TBSWU,Timer B Software Update" "0,1" bitfld.long 0x4 1. "TASWU,Timer A Software update" "0,1" bitfld.long 0x4 0. "MSWU,Master Timer Software" "0,1" line.long 0x8 "ISR,Interrupt Status Register" rbitfld.long 0x8 17. "BMPER,Burst mode Period Interrupt" "0,1" rbitfld.long 0x8 16. "DLLRDY,DLL Ready Interrupt Flag" "0,1" bitfld.long 0x8 5. "SYSFLT,System Fault Interrupt" "0,1" rbitfld.long 0x8 4. "FLT5,Fault 5 Interrupt Flag" "0,1" rbitfld.long 0x8 3. "FLT4,Fault 4 Interrupt Flag" "0,1" rbitfld.long 0x8 2. "FLT3,Fault 3 Interrupt Flag" "0,1" rbitfld.long 0x8 1. "FLT2,Fault 2 Interrupt Flag" "0,1" rbitfld.long 0x8 0. "FLT1,Fault 1 Interrupt Flag" "0,1" line.long 0xC "ICR,Interrupt Clear Register" bitfld.long 0xC 17. "BMPERC,Burst mode period flag" "0,1" bitfld.long 0xC 16. "DLLRDYC,DLL Ready Interrupt flag" "0,1" bitfld.long 0xC 5. "SYSFLTC,System Fault Interrupt Flag" "0,1" bitfld.long 0xC 4. "FLT5C,Fault 5 Interrupt Flag" "0,1" bitfld.long 0xC 3. "FLT4C,Fault 4 Interrupt Flag" "0,1" bitfld.long 0xC 2. "FLT3C,Fault 3 Interrupt Flag" "0,1" bitfld.long 0xC 1. "FLT2C,Fault 2 Interrupt Flag" "0,1" bitfld.long 0xC 0. "FLT1C,Fault 1 Interrupt Flag" "0,1" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 17. "BMPERIE,Burst mode period Interrupt" "0,1" bitfld.long 0x10 16. "DLLRDYIE,DLL Ready Interrupt Enable" "0,1" bitfld.long 0x10 5. "SYSFLTE,System Fault Interrupt" "0,1" bitfld.long 0x10 4. "FLT5IE,Fault 5 Interrupt Enable" "0,1" bitfld.long 0x10 3. "FLT4IE,Fault 4 Interrupt Enable" "0,1" bitfld.long 0x10 2. "FLT3IE,Fault 3 Interrupt Enable" "0,1" bitfld.long 0x10 1. "FLT2IE,Fault 2 Interrupt Enable" "0,1" bitfld.long 0x10 0. "FLT1IE,Fault 1 Interrupt Enable" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "OENR,Output Enable Register" bitfld.long 0x0 9. "TE2OEN,Timer E Output 2 Enable" "0,1" bitfld.long 0x0 8. "TE1OEN,Timer E Output 1 Enable" "0,1" bitfld.long 0x0 7. "TD2OEN,Timer D Output 2 Enable" "0,1" bitfld.long 0x0 6. "TD1OEN,Timer D Output 1 Enable" "0,1" bitfld.long 0x0 5. "TC2OEN,Timer C Output 2 Enable" "0,1" bitfld.long 0x0 4. "TC1OEN,Timer C Output 1 Enable" "0,1" bitfld.long 0x0 3. "TB2OEN,Timer B Output 2 Enable" "0,1" bitfld.long 0x0 2. "TB1OEN,Timer B Output 1 Enable" "0,1" bitfld.long 0x0 1. "TA2OEN,Timer A Output 2 Enable" "0,1" newline bitfld.long 0x0 0. "TA1OEN,Timer A Output 1 Enable" "0,1" group.long 0x18++0x3 line.long 0x0 "DISR,DISR" bitfld.long 0x0 9. "TE2ODIS,TE2ODIS" "0,1" bitfld.long 0x0 8. "TE1ODIS,TE1ODIS" "0,1" bitfld.long 0x0 7. "TD2ODIS,TD2ODIS" "0,1" bitfld.long 0x0 6. "TD1ODIS,TD1ODIS" "0,1" bitfld.long 0x0 5. "TC2ODIS,TC2ODIS" "0,1" bitfld.long 0x0 4. "TC1ODIS,TC1ODIS" "0,1" bitfld.long 0x0 3. "TB2ODIS,TB2ODIS" "0,1" bitfld.long 0x0 2. "TB1ODIS,TB1ODIS" "0,1" bitfld.long 0x0 1. "TA2ODIS,TA2ODIS" "0,1" newline bitfld.long 0x0 0. "TA1ODIS,TA1ODIS" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ODSR,Output Disable Status Register" bitfld.long 0x0 9. "TE2ODS,Timer E Output 2 disable" "0,1" bitfld.long 0x0 8. "TE1ODS,Timer E Output 1 disable" "0,1" bitfld.long 0x0 7. "TD2ODS,Timer D Output 2 disable" "0,1" bitfld.long 0x0 6. "TD1ODS,Timer D Output 1 disable" "0,1" bitfld.long 0x0 5. "TC2ODS,Timer C Output 2 disable" "0,1" bitfld.long 0x0 4. "TC1ODS,Timer C Output 1 disable" "0,1" bitfld.long 0x0 3. "TB2ODS,Timer B Output 2 disable" "0,1" bitfld.long 0x0 2. "TB1ODS,Timer B Output 1 disable" "0,1" bitfld.long 0x0 1. "TA2ODS,Timer A Output 2 disable" "0,1" newline bitfld.long 0x0 0. "TA1ODS,Timer A Output 1 disable" "0,1" group.long 0x20++0x43 line.long 0x0 "BMCR,Burst Mode Control Register" bitfld.long 0x0 31. "BMSTAT,Burst Mode Status" "0,1" bitfld.long 0x0 21. "TEBM,Timer E Burst Mode" "0,1" bitfld.long 0x0 20. "TDBM,Timer D Burst Mode" "0,1" bitfld.long 0x0 19. "TCBM,Timer C Burst Mode" "0,1" bitfld.long 0x0 18. "TBBM,Timer B Burst Mode" "0,1" bitfld.long 0x0 17. "TABM,Timer A Burst Mode" "0,1" bitfld.long 0x0 16. "MTBM,Master Timer Burst Mode" "0,1" bitfld.long 0x0 10. "BMPREN,Burst Mode Preload Enable" "0,1" hexmask.long.byte 0x0 6.--9. 1. "BMPRSC,Burst Mode Prescaler" newline hexmask.long.byte 0x0 2.--5. 1. "BMCLK,Burst Mode Clock source" bitfld.long 0x0 1. "BMOM,Burst Mode operating mode" "0,1" bitfld.long 0x0 0. "BME,Burst Mode enable" "0,1" line.long 0x4 "BMTRG,BMTRG" bitfld.long 0x4 31. "OCHPEV,OCHPEV" "0,1" bitfld.long 0x4 26. "TECMP2,TECMP2" "0,1" bitfld.long 0x4 25. "TECMP1,TECMP1" "0,1" bitfld.long 0x4 24. "TEREP,TEREP" "0,1" bitfld.long 0x4 23. "TERST,TERST" "0,1" bitfld.long 0x4 22. "TDCMP2,TDCMP2" "0,1" bitfld.long 0x4 21. "TDCMP1,TDCMP1" "0,1" bitfld.long 0x4 20. "TDREP,TDREP" "0,1" bitfld.long 0x4 19. "TDRST,TDRST" "0,1" newline bitfld.long 0x4 18. "TCCMP2,TCCMP2" "0,1" bitfld.long 0x4 17. "TCCMP1,TCCMP1" "0,1" bitfld.long 0x4 16. "TCREP,TCREP" "0,1" bitfld.long 0x4 15. "TCRST,TCRST" "0,1" bitfld.long 0x4 14. "TBCMP2,TBCMP2" "0,1" bitfld.long 0x4 13. "TBCMP1,TBCMP1" "0,1" bitfld.long 0x4 12. "TBREP,TBREP" "0,1" bitfld.long 0x4 11. "TBRST,TBRST" "0,1" bitfld.long 0x4 10. "TACMP2,TACMP2" "0,1" newline bitfld.long 0x4 9. "TACMP1,TACMP1" "0,1" bitfld.long 0x4 8. "TAREP,TAREP" "0,1" bitfld.long 0x4 7. "TARST,TARST" "0,1" bitfld.long 0x4 6. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x4 5. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x4 4. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x4 3. "MSTCMP1,MSTCMP1" "0,1" bitfld.long 0x4 2. "MSTREP,MSTREP" "0,1" bitfld.long 0x4 1. "MSTRST,MSTRST" "0,1" newline bitfld.long 0x4 0. "SW,SW" "0,1" line.long 0x8 "BMCMPR6,BMCMPR6" hexmask.long.word 0x8 0.--15. 1. "BMCMP,BMCMP" line.long 0xC "BMPER,Burst Mode Period Register" hexmask.long.word 0xC 0.--15. 1. "BMPER,Burst mode Period" line.long 0x10 "EECR1,Timer External Event Control Register" bitfld.long 0x10 29. "EE5FAST,External Event 5 Fast mode" "0,1" bitfld.long 0x10 27.--28. "EE5SNS,External Event 5" "0,1,2,3" bitfld.long 0x10 26. "EE5POL,External Event 5 Polarity" "0,1" bitfld.long 0x10 24.--25. "EE5SRC,External Event 5 Source" "0,1,2,3" bitfld.long 0x10 23. "EE4FAST,External Event 4 Fast mode" "0,1" bitfld.long 0x10 21.--22. "EE4SNS,External Event 4" "0,1,2,3" bitfld.long 0x10 20. "EE4POL,External Event 4 Polarity" "0,1" bitfld.long 0x10 18.--19. "EE4SRC,External Event 4 Source" "0,1,2,3" bitfld.long 0x10 17. "EE3FAST,External Event 3 Fast mode" "0,1" newline bitfld.long 0x10 15.--16. "EE3SNS,External Event 3" "0,1,2,3" bitfld.long 0x10 14. "EE3POL,External Event 3 Polarity" "0,1" bitfld.long 0x10 12.--13. "EE3SRC,External Event 3 Source" "0,1,2,3" bitfld.long 0x10 11. "EE2FAST,External Event 2 Fast mode" "0,1" bitfld.long 0x10 9.--10. "EE2SNS,External Event 2" "0,1,2,3" bitfld.long 0x10 8. "EE2POL,External Event 2 Polarity" "0,1" bitfld.long 0x10 6.--7. "EE2SRC,External Event 2 Source" "0,1,2,3" bitfld.long 0x10 5. "EE1FAST,External Event 1 Fast mode" "0,1" bitfld.long 0x10 3.--4. "EE1SNS,External Event 1" "0,1,2,3" newline bitfld.long 0x10 2. "EE1POL,External Event 1 Polarity" "0,1" bitfld.long 0x10 0.--1. "EE1SRC,External Event 1 Source" "0,1,2,3" line.long 0x14 "EECR2,Timer External Event Control Register" bitfld.long 0x14 27.--28. "EE10SNS,External Event 10" "0,1,2,3" bitfld.long 0x14 26. "EE10POL,External Event 10 Polarity" "0,1" bitfld.long 0x14 24.--25. "EE10SRC,External Event 10 Source" "0,1,2,3" bitfld.long 0x14 21.--22. "EE9SNS,External Event 9" "0,1,2,3" bitfld.long 0x14 20. "EE9POL,External Event 9 Polarity" "0,1" bitfld.long 0x14 18.--19. "EE9SRC,External Event 9 Source" "0,1,2,3" bitfld.long 0x14 15.--16. "EE8SNS,External Event 8" "0,1,2,3" bitfld.long 0x14 14. "EE8POL,External Event 8 Polarity" "0,1" bitfld.long 0x14 12.--13. "EE8SRC,External Event 8 Source" "0,1,2,3" newline bitfld.long 0x14 9.--10. "EE7SNS,External Event 7" "0,1,2,3" bitfld.long 0x14 8. "EE7POL,External Event 7 Polarity" "0,1" bitfld.long 0x14 6.--7. "EE7SRC,External Event 7 Source" "0,1,2,3" bitfld.long 0x14 3.--4. "EE6SNS,External Event 6" "0,1,2,3" bitfld.long 0x14 2. "EE6POL,External Event 6 Polarity" "0,1" bitfld.long 0x14 0.--1. "EE6SRC,External Event 6 Source" "0,1,2,3" line.long 0x18 "EECR3,Timer External Event Control Register" bitfld.long 0x18 27.--28. "EE10SNS,EE10SNS" "0,1,2,3" bitfld.long 0x18 26. "EE10POL,EE10POL" "0,1" bitfld.long 0x18 24.--25. "EE10SRC,EE10SRC" "0,1,2,3" bitfld.long 0x18 21.--22. "EE9SNS,EE9SNS" "0,1,2,3" bitfld.long 0x18 20. "EE9POL,EE9POL" "0,1" bitfld.long 0x18 18.--19. "EE9SRC,EE9SRC" "0,1,2,3" bitfld.long 0x18 15.--16. "EE8SNS,EE8SNS" "0,1,2,3" bitfld.long 0x18 14. "EE8POL,EE8POL" "0,1" bitfld.long 0x18 12.--13. "EE8SRC,EE8SRC" "0,1,2,3" newline bitfld.long 0x18 9.--10. "EE7SNS,EE7SNS" "0,1,2,3" bitfld.long 0x18 8. "EE7POL,EE7POL" "0,1" bitfld.long 0x18 6.--7. "EE7SRC,EE7SRC" "0,1,2,3" bitfld.long 0x18 3.--4. "EE6SNS,EE6SNS" "0,1,2,3" bitfld.long 0x18 2. "EE6POL,EE6POL" "0,1" bitfld.long 0x18 0.--1. "EE6SRC,EE6SRC" "0,1,2,3" line.long 0x1C "ADC1R,ADC Trigger 1 Register" bitfld.long 0x1C 31. "AD1TEPER,ADC trigger 1 on Timer E" "0,1" bitfld.long 0x1C 30. "AD1TEC4,ADC trigger 1 on Timer E compare" "0,1" bitfld.long 0x1C 29. "AD1TEC3,ADC trigger 1 on Timer E compare" "0,1" bitfld.long 0x1C 28. "AD1TEC2,ADC trigger 1 on Timer E compare" "0,1" bitfld.long 0x1C 27. "AD1TDPER,ADC trigger 1 on Timer D" "0,1" bitfld.long 0x1C 26. "AD1TDC4,ADC trigger 1 on Timer D compare" "0,1" bitfld.long 0x1C 25. "AD1TDC3,ADC trigger 1 on Timer D compare" "0,1" bitfld.long 0x1C 24. "AD1TDC2,ADC trigger 1 on Timer D compare" "0,1" bitfld.long 0x1C 23. "AD1TCPER,ADC trigger 1 on Timer C" "0,1" newline bitfld.long 0x1C 22. "AD1TCC4,ADC trigger 1 on Timer C compare" "0,1" bitfld.long 0x1C 21. "AD1TCC3,ADC trigger 1 on Timer C compare" "0,1" bitfld.long 0x1C 20. "AD1TCC2,ADC trigger 1 on Timer C compare" "0,1" bitfld.long 0x1C 19. "AD1TBRST,ADC trigger 1 on Timer B" "0,1" bitfld.long 0x1C 18. "AD1TBPER,ADC trigger 1 on Timer B" "0,1" bitfld.long 0x1C 17. "AD1TBC4,ADC trigger 1 on Timer B compare" "0,1" bitfld.long 0x1C 16. "AD1TBC3,ADC trigger 1 on Timer B compare" "0,1" bitfld.long 0x1C 15. "AD1TBC2,ADC trigger 1 on Timer B compare" "0,1" bitfld.long 0x1C 14. "AD1TARST,ADC trigger 1 on Timer A" "0,1" newline bitfld.long 0x1C 13. "AD1TAPER,ADC trigger 1 on Timer A" "0,1" bitfld.long 0x1C 12. "AD1TAC4,ADC trigger 1 on Timer A compare" "0,1" bitfld.long 0x1C 11. "AD1TAC3,ADC trigger 1 on Timer A compare" "0,1" bitfld.long 0x1C 10. "AD1TAC2,ADC trigger 1 on Timer A compare" "0,1" bitfld.long 0x1C 9. "AD1EEV5,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 8. "AD1EEV4,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 7. "AD1EEV3,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 6. "AD1EEV2,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 5. "AD1EEV1,ADC trigger 1 on External Event" "0,1" newline bitfld.long 0x1C 4. "AD1MPER,ADC trigger 1 on Master" "0,1" bitfld.long 0x1C 3. "AD1MC4,ADC trigger 1 on Master Compare" "0,1" bitfld.long 0x1C 2. "AD1MC3,ADC trigger 1 on Master Compare" "0,1" bitfld.long 0x1C 1. "AD1MC2,ADC trigger 1 on Master Compare" "0,1" bitfld.long 0x1C 0. "AD1MC1,ADC trigger 1 on Master Compare" "0,1" line.long 0x20 "ADC2R,ADC Trigger 2 Register" bitfld.long 0x20 31. "AD2TERST,ADC trigger 2 on Timer E" "0,1" bitfld.long 0x20 30. "AD2TEC4,ADC trigger 2 on Timer E compare" "0,1" bitfld.long 0x20 29. "AD2TEC3,ADC trigger 2 on Timer E compare" "0,1" bitfld.long 0x20 28. "AD2TEC2,ADC trigger 2 on Timer E compare" "0,1" bitfld.long 0x20 27. "AD2TDRST,ADC trigger 2 on Timer D" "0,1" bitfld.long 0x20 26. "AD2TDPER,ADC trigger 2 on Timer D" "0,1" bitfld.long 0x20 25. "AD2TDC4,ADC trigger 2 on Timer D compare" "0,1" bitfld.long 0x20 24. "AD2TDC3,ADC trigger 2 on Timer D compare" "0,1" bitfld.long 0x20 23. "AD2TDC2,ADC trigger 2 on Timer D compare" "0,1" newline bitfld.long 0x20 22. "AD2TCRST,ADC trigger 2 on Timer C" "0,1" bitfld.long 0x20 21. "AD2TCPER,ADC trigger 2 on Timer C" "0,1" bitfld.long 0x20 20. "AD2TCC4,ADC trigger 2 on Timer C compare" "0,1" bitfld.long 0x20 19. "AD2TCC3,ADC trigger 2 on Timer C compare" "0,1" bitfld.long 0x20 18. "AD2TCC2,ADC trigger 2 on Timer C compare" "0,1" bitfld.long 0x20 17. "AD2TBPER,ADC trigger 2 on Timer B" "0,1" bitfld.long 0x20 16. "AD2TBC4,ADC trigger 2 on Timer B compare" "0,1" bitfld.long 0x20 15. "AD2TBC3,ADC trigger 2 on Timer B compare" "0,1" bitfld.long 0x20 14. "AD2TBC2,ADC trigger 2 on Timer B compare" "0,1" newline bitfld.long 0x20 13. "AD2TAPER,ADC trigger 2 on Timer A" "0,1" bitfld.long 0x20 12. "AD2TAC4,ADC trigger 2 on Timer A compare" "0,1" bitfld.long 0x20 11. "AD2TAC3,ADC trigger 2 on Timer A compare" "0,1" bitfld.long 0x20 10. "AD2TAC2,ADC trigger 2 on Timer A compare" "0,1" bitfld.long 0x20 9. "AD2EEV10,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 8. "AD2EEV9,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 7. "AD2EEV8,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 6. "AD2EEV7,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 5. "AD2EEV6,ADC trigger 2 on External Event" "0,1" newline bitfld.long 0x20 4. "AD2MPER,ADC trigger 2 on Master" "0,1" bitfld.long 0x20 3. "AD2MC4,ADC trigger 2 on Master Compare" "0,1" bitfld.long 0x20 2. "AD2MC3,ADC trigger 2 on Master Compare" "0,1" bitfld.long 0x20 1. "AD2MC2,ADC trigger 2 on Master Compare" "0,1" bitfld.long 0x20 0. "AD2MC1,ADC trigger 2 on Master Compare" "0,1" line.long 0x24 "ADC3R,ADC Trigger 3 Register" bitfld.long 0x24 31. "AD1TEPER,AD1TEPER" "0,1" bitfld.long 0x24 30. "AD1TEC4,AD1TEC4" "0,1" bitfld.long 0x24 29. "AD1TEC3,AD1TEC3" "0,1" bitfld.long 0x24 28. "AD1TEC2,AD1TEC2" "0,1" bitfld.long 0x24 27. "AD1TDPER,AD1TDPER" "0,1" bitfld.long 0x24 26. "AD1TDC4,AD1TDC4" "0,1" bitfld.long 0x24 25. "AD1TDC3,AD1TDC3" "0,1" bitfld.long 0x24 24. "AD1TDC2,AD1TDC2" "0,1" bitfld.long 0x24 23. "AD1TCPER,AD1TCPER" "0,1" newline bitfld.long 0x24 22. "AD1TCC4,AD1TCC4" "0,1" bitfld.long 0x24 21. "AD1TCC3,AD1TCC3" "0,1" bitfld.long 0x24 20. "AD1TCC2,AD1TCC2" "0,1" bitfld.long 0x24 19. "AD1TBRST,AD1TBRST" "0,1" bitfld.long 0x24 18. "AD1TBPER,AD1TBPER" "0,1" bitfld.long 0x24 17. "AD1TBC4,AD1TBC4" "0,1" bitfld.long 0x24 16. "AD1TBC3,AD1TBC3" "0,1" bitfld.long 0x24 15. "AD1TBC2,AD1TBC2" "0,1" bitfld.long 0x24 14. "AD1TARST,AD1TARST" "0,1" newline bitfld.long 0x24 13. "AD1TAPER,AD1TAPER" "0,1" bitfld.long 0x24 12. "AD1TAC4,AD1TAC4" "0,1" bitfld.long 0x24 11. "AD1TAC3,AD1TAC3" "0,1" bitfld.long 0x24 10. "AD1TAC2,AD1TAC2" "0,1" bitfld.long 0x24 9. "AD1EEV5,AD1EEV5" "0,1" bitfld.long 0x24 8. "AD1EEV4,AD1EEV4" "0,1" bitfld.long 0x24 7. "AD1EEV3,AD1EEV3" "0,1" bitfld.long 0x24 6. "AD1EEV2,AD1EEV2" "0,1" bitfld.long 0x24 5. "AD1EEV1,AD1EEV1" "0,1" newline bitfld.long 0x24 4. "AD1MPER,AD1MPER" "0,1" bitfld.long 0x24 3. "AD1MC4,AD1MC4" "0,1" bitfld.long 0x24 2. "AD1MC3,AD1MC3" "0,1" bitfld.long 0x24 1. "AD1MC2,AD1MC2" "0,1" bitfld.long 0x24 0. "AD1MC1,AD1MC1" "0,1" line.long 0x28 "ADC4R,ADC Trigger 4 Register" bitfld.long 0x28 31. "AD2TERST,AD2TERST" "0,1" bitfld.long 0x28 30. "AD2TEC4,AD2TEC4" "0,1" bitfld.long 0x28 29. "AD2TEC3,AD2TEC3" "0,1" bitfld.long 0x28 28. "AD2TEC2,AD2TEC2" "0,1" bitfld.long 0x28 27. "AD2TDRST,AD2TDRST" "0,1" bitfld.long 0x28 26. "AD2TDPER,AD2TDPER" "0,1" bitfld.long 0x28 25. "AD2TDC4,AD2TDC4" "0,1" bitfld.long 0x28 24. "AD2TDC3,AD2TDC3" "0,1" bitfld.long 0x28 23. "AD2TDC2,AD2TDC2" "0,1" newline bitfld.long 0x28 22. "AD2TCRST,AD2TCRST" "0,1" bitfld.long 0x28 21. "AD2TCPER,AD2TCPER" "0,1" bitfld.long 0x28 20. "AD2TCC4,AD2TCC4" "0,1" bitfld.long 0x28 19. "AD2TCC3,AD2TCC3" "0,1" bitfld.long 0x28 18. "AD2TCC2,AD2TCC2" "0,1" bitfld.long 0x28 17. "AD2TBPER,AD2TBPER" "0,1" bitfld.long 0x28 16. "AD2TBC4,AD2TBC4" "0,1" bitfld.long 0x28 15. "AD2TBC3,AD2TBC3" "0,1" bitfld.long 0x28 14. "AD2TBC2,AD2TBC2" "0,1" newline bitfld.long 0x28 13. "AD2TAPER,AD2TAPER" "0,1" bitfld.long 0x28 12. "AD2TAC4,AD2TAC4" "0,1" bitfld.long 0x28 11. "AD2TAC3,AD2TAC3" "0,1" bitfld.long 0x28 10. "AD2TAC2,AD2TAC2" "0,1" bitfld.long 0x28 9. "AD2EEV10,AD2EEV10" "0,1" bitfld.long 0x28 8. "AD2EEV9,AD2EEV9" "0,1" bitfld.long 0x28 7. "AD2EEV8,AD2EEV8" "0,1" bitfld.long 0x28 6. "AD2EEV7,AD2EEV7" "0,1" bitfld.long 0x28 5. "AD2EEV6,AD2EEV6" "0,1" newline bitfld.long 0x28 4. "AD2MPER,AD2MPER" "0,1" bitfld.long 0x28 3. "AD2MC4,AD2MC4" "0,1" bitfld.long 0x28 2. "AD2MC3,AD2MC3" "0,1" bitfld.long 0x28 1. "AD2MC2,AD2MC2" "0,1" bitfld.long 0x28 0. "AD2MC1,AD2MC1" "0,1" line.long 0x2C "DLLCR,DLL Control Register" bitfld.long 0x2C 2.--3. "CALRTE,DLL Calibration rate" "0,1,2,3" bitfld.long 0x2C 1. "CALEN,DLL Calibration Enable" "0,1" bitfld.long 0x2C 0. "CAL,DLL Calibration Start" "0,1" line.long 0x30 "FLTINR1,HRTIM Fault Input Register 1" bitfld.long 0x30 31. "FLT4LCK,FLT4LCK" "0,1" hexmask.long.byte 0x30 27.--30. 1. "FLT4F,FLT4F" bitfld.long 0x30 26. "FLT4SRC,FLT4SRC" "0,1" bitfld.long 0x30 25. "FLT4P,FLT4P" "0,1" bitfld.long 0x30 24. "FLT4E,FLT4E" "0,1" bitfld.long 0x30 23. "FLT3LCK,FLT3LCK" "0,1" hexmask.long.byte 0x30 19.--22. 1. "FLT3F,FLT3F" bitfld.long 0x30 18. "FLT3SRC,FLT3SRC" "0,1" bitfld.long 0x30 17. "FLT3P,FLT3P" "0,1" newline bitfld.long 0x30 16. "FLT3E,FLT3E" "0,1" bitfld.long 0x30 15. "FLT2LCK,FLT2LCK" "0,1" hexmask.long.byte 0x30 11.--14. 1. "FLT2F,FLT2F" bitfld.long 0x30 10. "FLT2SRC,FLT2SRC" "0,1" bitfld.long 0x30 9. "FLT2P,FLT2P" "0,1" bitfld.long 0x30 8. "FLT2E,FLT2E" "0,1" bitfld.long 0x30 7. "FLT1LCK,FLT1LCK" "0,1" hexmask.long.byte 0x30 3.--6. 1. "FLT1F,FLT1F" bitfld.long 0x30 2. "FLT1SRC,FLT1SRC" "0,1" newline bitfld.long 0x30 1. "FLT1P,FLT1P" "0,1" bitfld.long 0x30 0. "FLT1E,FLT1E" "0,1" line.long 0x34 "FLTINR2,HRTIM Fault Input Register 2" bitfld.long 0x34 24.--25. "FLTSD,FLTSD" "0,1,2,3" bitfld.long 0x34 7. "FLT5LCK,FLT5LCK" "0,1" hexmask.long.byte 0x34 3.--6. 1. "FLT5F,FLT5F" bitfld.long 0x34 2. "FLT5SRC,FLT5SRC" "0,1" bitfld.long 0x34 1. "FLT5P,FLT5P" "0,1" bitfld.long 0x34 0. "FLT5E,FLT5E" "0,1" line.long 0x38 "BDMUPDR,BDMUPDR" bitfld.long 0x38 9. "MCMP4,MCMP4" "0,1" bitfld.long 0x38 8. "MCMP3,MCMP3" "0,1" bitfld.long 0x38 7. "MCMP2,MCMP2" "0,1" bitfld.long 0x38 6. "MCMP1,MCMP1" "0,1" bitfld.long 0x38 5. "MREP,MREP" "0,1" bitfld.long 0x38 4. "MPER,MPER" "0,1" bitfld.long 0x38 3. "MCNT,MCNT" "0,1" bitfld.long 0x38 2. "MDIER,MDIER" "0,1" bitfld.long 0x38 1. "MICR,MICR" "0,1" newline bitfld.long 0x38 0. "MCR,MCR" "0,1" line.long 0x3C "BDTxUPR,Burst DMA Timerx update" bitfld.long 0x3C 20. "TIMxFLTR,HRTIM_FLTxR register update" "0,1" bitfld.long 0x3C 19. "TIMxOUTR,HRTIM_OUTxR register update" "0,1" bitfld.long 0x3C 18. "TIMxCHPR,HRTIM_CHPxR register update" "0,1" bitfld.long 0x3C 17. "TIMxRSTR,HRTIM_RSTxR register update" "0,1" bitfld.long 0x3C 16. "TIMxEEFR2,HRTIM_EEFxR2 register update" "0,1" bitfld.long 0x3C 15. "TIMxEEFR1,HRTIM_EEFxR1 register update" "0,1" bitfld.long 0x3C 14. "TIMxRST2R,HRTIM_RST2xR register update" "0,1" bitfld.long 0x3C 13. "TIMxSET2R,HRTIM_SET2xR register update" "0,1" bitfld.long 0x3C 12. "TIMxRST1R,HRTIM_RST1xR register update" "0,1" newline bitfld.long 0x3C 11. "TIMxSET1R,HRTIM_SET1xR register update" "0,1" bitfld.long 0x3C 10. "TIMx_DTxR,HRTIM_DTxR register update" "0,1" bitfld.long 0x3C 9. "TIMxCMP4,HRTIM_CMP4xR register update" "0,1" bitfld.long 0x3C 8. "TIMxCMP3,HRTIM_CMP3xR register update" "0,1" bitfld.long 0x3C 7. "TIMxCMP2,HRTIM_CMP2xR register update" "0,1" bitfld.long 0x3C 6. "TIMxCMP1,HRTIM_CMP1xR register update" "0,1" bitfld.long 0x3C 5. "TIMxREP,HRTIM_REPxR register update" "0,1" bitfld.long 0x3C 4. "TIMxPER,HRTIM_PERxR register update" "0,1" bitfld.long 0x3C 3. "TIMxCNT,HRTIM_CNTxR register update" "0,1" newline bitfld.long 0x3C 2. "TIMxDIER,HRTIM_TIMxDIER register update" "0,1" bitfld.long 0x3C 1. "TIMxICR,HRTIM_TIMxICR register update" "0,1" bitfld.long 0x3C 0. "TIMxCR,HRTIM_TIMxCR register update" "0,1" line.long 0x40 "BDMADR,Burst DMA Data Register" hexmask.long 0x40 0.--31. 1. "BDMADR,Burst DMA Data register" tree.end endif sif (cpuis("STM32H7B3*")) tree "HRTIM_Common" base ad:0x40017780 group.long 0x0++0x13 line.long 0x0 "CR1,Control Register 1" hexmask.long.byte 0x0 25.--28. 1. "AD4USRC,ADC Trigger 4 Update" hexmask.long.byte 0x0 22.--25. 1. "AD3USRC,ADC Trigger 3 Update" hexmask.long.byte 0x0 19.--22. 1. "AD2USRC,ADC Trigger 2 Update" hexmask.long.byte 0x0 16.--19. 1. "AD1USRC,ADC Trigger 1 Update" bitfld.long 0x0 5. "TEUDIS,Timer E Update Disable" "0,1" bitfld.long 0x0 4. "TDUDIS,Timer D Update Disable" "0,1" bitfld.long 0x0 3. "TCUDIS,Timer C Update Disable" "0,1" bitfld.long 0x0 2. "TBUDIS,Timer B Update Disable" "0,1" bitfld.long 0x0 1. "TAUDIS,Timer A Update Disable" "0,1" newline bitfld.long 0x0 0. "MUDIS,Master Update Disable" "0,1" line.long 0x4 "CR2,Control Register 2" bitfld.long 0x4 13. "TERST,Timer E counter software" "0,1" bitfld.long 0x4 12. "TDRST,Timer D counter software" "0,1" bitfld.long 0x4 11. "TCRST,Timer C counter software" "0,1" bitfld.long 0x4 10. "TBRST,Timer B counter software" "0,1" bitfld.long 0x4 9. "TARST,Timer A counter software" "0,1" bitfld.long 0x4 8. "MRST,Master Counter software" "0,1" bitfld.long 0x4 5. "TESWU,Timer E Software Update" "0,1" bitfld.long 0x4 4. "TDSWU,Timer D Software Update" "0,1" bitfld.long 0x4 3. "TCSWU,Timer C Software Update" "0,1" newline bitfld.long 0x4 2. "TBSWU,Timer B Software Update" "0,1" bitfld.long 0x4 1. "TASWU,Timer A Software update" "0,1" bitfld.long 0x4 0. "MSWU,Master Timer Software" "0,1" line.long 0x8 "ISR,Interrupt Status Register" rbitfld.long 0x8 17. "BMPER,Burst mode Period Interrupt" "0,1" rbitfld.long 0x8 16. "DLLRDY,DLL Ready Interrupt Flag" "0,1" bitfld.long 0x8 5. "SYSFLT,System Fault Interrupt" "0,1" rbitfld.long 0x8 4. "FLT5,Fault 5 Interrupt Flag" "0,1" rbitfld.long 0x8 3. "FLT4,Fault 4 Interrupt Flag" "0,1" rbitfld.long 0x8 2. "FLT3,Fault 3 Interrupt Flag" "0,1" rbitfld.long 0x8 1. "FLT2,Fault 2 Interrupt Flag" "0,1" rbitfld.long 0x8 0. "FLT1,Fault 1 Interrupt Flag" "0,1" line.long 0xC "ICR,Interrupt Clear Register" bitfld.long 0xC 17. "BMPERC,Burst mode period flag" "0,1" bitfld.long 0xC 16. "DLLRDYC,DLL Ready Interrupt flag" "0,1" bitfld.long 0xC 5. "SYSFLTC,System Fault Interrupt Flag" "0,1" bitfld.long 0xC 4. "FLT5C,Fault 5 Interrupt Flag" "0,1" bitfld.long 0xC 3. "FLT4C,Fault 4 Interrupt Flag" "0,1" bitfld.long 0xC 2. "FLT3C,Fault 3 Interrupt Flag" "0,1" bitfld.long 0xC 1. "FLT2C,Fault 2 Interrupt Flag" "0,1" bitfld.long 0xC 0. "FLT1C,Fault 1 Interrupt Flag" "0,1" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 17. "BMPERIE,Burst mode period Interrupt" "0,1" bitfld.long 0x10 16. "DLLRDYIE,DLL Ready Interrupt Enable" "0,1" bitfld.long 0x10 5. "SYSFLTE,System Fault Interrupt" "0,1" bitfld.long 0x10 4. "FLT5IE,Fault 5 Interrupt Enable" "0,1" bitfld.long 0x10 3. "FLT4IE,Fault 4 Interrupt Enable" "0,1" bitfld.long 0x10 2. "FLT3IE,Fault 3 Interrupt Enable" "0,1" bitfld.long 0x10 1. "FLT2IE,Fault 2 Interrupt Enable" "0,1" bitfld.long 0x10 0. "FLT1IE,Fault 1 Interrupt Enable" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "OENR,Output Enable Register" bitfld.long 0x0 9. "TE2OEN,Timer E Output 2 Enable" "0,1" bitfld.long 0x0 8. "TE1OEN,Timer E Output 1 Enable" "0,1" bitfld.long 0x0 7. "TD2OEN,Timer D Output 2 Enable" "0,1" bitfld.long 0x0 6. "TD1OEN,Timer D Output 1 Enable" "0,1" bitfld.long 0x0 5. "TC2OEN,Timer C Output 2 Enable" "0,1" bitfld.long 0x0 4. "TC1OEN,Timer C Output 1 Enable" "0,1" bitfld.long 0x0 3. "TB2OEN,Timer B Output 2 Enable" "0,1" bitfld.long 0x0 2. "TB1OEN,Timer B Output 1 Enable" "0,1" bitfld.long 0x0 1. "TA2OEN,Timer A Output 2 Enable" "0,1" newline bitfld.long 0x0 0. "TA1OEN,Timer A Output 1 Enable" "0,1" group.long 0x18++0x3 line.long 0x0 "DISR,DISR" bitfld.long 0x0 9. "TE2ODIS,TE2ODIS" "0,1" bitfld.long 0x0 8. "TE1ODIS,TE1ODIS" "0,1" bitfld.long 0x0 7. "TD2ODIS,TD2ODIS" "0,1" bitfld.long 0x0 6. "TD1ODIS,TD1ODIS" "0,1" bitfld.long 0x0 5. "TC2ODIS,TC2ODIS" "0,1" bitfld.long 0x0 4. "TC1ODIS,TC1ODIS" "0,1" bitfld.long 0x0 3. "TB2ODIS,TB2ODIS" "0,1" bitfld.long 0x0 2. "TB1ODIS,TB1ODIS" "0,1" bitfld.long 0x0 1. "TA2ODIS,TA2ODIS" "0,1" newline bitfld.long 0x0 0. "TA1ODIS,TA1ODIS" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ODSR,Output Disable Status Register" bitfld.long 0x0 9. "TE2ODS,Timer E Output 2 disable" "0,1" bitfld.long 0x0 8. "TE1ODS,Timer E Output 1 disable" "0,1" bitfld.long 0x0 7. "TD2ODS,Timer D Output 2 disable" "0,1" bitfld.long 0x0 6. "TD1ODS,Timer D Output 1 disable" "0,1" bitfld.long 0x0 5. "TC2ODS,Timer C Output 2 disable" "0,1" bitfld.long 0x0 4. "TC1ODS,Timer C Output 1 disable" "0,1" bitfld.long 0x0 3. "TB2ODS,Timer B Output 2 disable" "0,1" bitfld.long 0x0 2. "TB1ODS,Timer B Output 1 disable" "0,1" bitfld.long 0x0 1. "TA2ODS,Timer A Output 2 disable" "0,1" newline bitfld.long 0x0 0. "TA1ODS,Timer A Output 1 disable" "0,1" group.long 0x20++0x43 line.long 0x0 "BMCR,Burst Mode Control Register" bitfld.long 0x0 31. "BMSTAT,Burst Mode Status" "0,1" bitfld.long 0x0 21. "TEBM,Timer E Burst Mode" "0,1" bitfld.long 0x0 20. "TDBM,Timer D Burst Mode" "0,1" bitfld.long 0x0 19. "TCBM,Timer C Burst Mode" "0,1" bitfld.long 0x0 18. "TBBM,Timer B Burst Mode" "0,1" bitfld.long 0x0 17. "TABM,Timer A Burst Mode" "0,1" bitfld.long 0x0 16. "MTBM,Master Timer Burst Mode" "0,1" bitfld.long 0x0 10. "BMPREN,Burst Mode Preload Enable" "0,1" hexmask.long.byte 0x0 6.--9. 1. "BMPRSC,Burst Mode Prescaler" newline hexmask.long.byte 0x0 2.--5. 1. "BMCLK,Burst Mode Clock source" bitfld.long 0x0 1. "BMOM,Burst Mode operating mode" "0,1" bitfld.long 0x0 0. "BME,Burst Mode enable" "0,1" line.long 0x4 "BMTRG,BMTRG" bitfld.long 0x4 31. "OCHPEV,OCHPEV" "0,1" bitfld.long 0x4 26. "TECMP2,TECMP2" "0,1" bitfld.long 0x4 25. "TECMP1,TECMP1" "0,1" bitfld.long 0x4 24. "TEREP,TEREP" "0,1" bitfld.long 0x4 23. "TERST,TERST" "0,1" bitfld.long 0x4 22. "TDCMP2,TDCMP2" "0,1" bitfld.long 0x4 21. "TDCMP1,TDCMP1" "0,1" bitfld.long 0x4 20. "TDREP,TDREP" "0,1" bitfld.long 0x4 19. "TDRST,TDRST" "0,1" newline bitfld.long 0x4 18. "TCCMP2,TCCMP2" "0,1" bitfld.long 0x4 17. "TCCMP1,TCCMP1" "0,1" bitfld.long 0x4 16. "TCREP,TCREP" "0,1" bitfld.long 0x4 15. "TCRST,TCRST" "0,1" bitfld.long 0x4 14. "TBCMP2,TBCMP2" "0,1" bitfld.long 0x4 13. "TBCMP1,TBCMP1" "0,1" bitfld.long 0x4 12. "TBREP,TBREP" "0,1" bitfld.long 0x4 11. "TBRST,TBRST" "0,1" bitfld.long 0x4 10. "TACMP2,TACMP2" "0,1" newline bitfld.long 0x4 9. "TACMP1,TACMP1" "0,1" bitfld.long 0x4 8. "TAREP,TAREP" "0,1" bitfld.long 0x4 7. "TARST,TARST" "0,1" bitfld.long 0x4 6. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x4 5. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x4 4. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x4 3. "MSTCMP1,MSTCMP1" "0,1" bitfld.long 0x4 2. "MSTREP,MSTREP" "0,1" bitfld.long 0x4 1. "MSTRST,MSTRST" "0,1" newline bitfld.long 0x4 0. "SW,SW" "0,1" line.long 0x8 "BMCMPR6,BMCMPR6" hexmask.long.word 0x8 0.--15. 1. "BMCMP,BMCMP" line.long 0xC "BMPER,Burst Mode Period Register" hexmask.long.word 0xC 0.--15. 1. "BMPER,Burst mode Period" line.long 0x10 "EECR1,Timer External Event Control Register" bitfld.long 0x10 29. "EE5FAST,External Event 5 Fast mode" "0,1" bitfld.long 0x10 27.--28. "EE5SNS,External Event 5" "0,1,2,3" bitfld.long 0x10 26. "EE5POL,External Event 5 Polarity" "0,1" bitfld.long 0x10 24.--25. "EE5SRC,External Event 5 Source" "0,1,2,3" bitfld.long 0x10 23. "EE4FAST,External Event 4 Fast mode" "0,1" bitfld.long 0x10 21.--22. "EE4SNS,External Event 4" "0,1,2,3" bitfld.long 0x10 20. "EE4POL,External Event 4 Polarity" "0,1" bitfld.long 0x10 18.--19. "EE4SRC,External Event 4 Source" "0,1,2,3" bitfld.long 0x10 17. "EE3FAST,External Event 3 Fast mode" "0,1" newline bitfld.long 0x10 15.--16. "EE3SNS,External Event 3" "0,1,2,3" bitfld.long 0x10 14. "EE3POL,External Event 3 Polarity" "0,1" bitfld.long 0x10 12.--13. "EE3SRC,External Event 3 Source" "0,1,2,3" bitfld.long 0x10 11. "EE2FAST,External Event 2 Fast mode" "0,1" bitfld.long 0x10 9.--10. "EE2SNS,External Event 2" "0,1,2,3" bitfld.long 0x10 8. "EE2POL,External Event 2 Polarity" "0,1" bitfld.long 0x10 6.--7. "EE2SRC,External Event 2 Source" "0,1,2,3" bitfld.long 0x10 5. "EE1FAST,External Event 1 Fast mode" "0,1" bitfld.long 0x10 3.--4. "EE1SNS,External Event 1" "0,1,2,3" newline bitfld.long 0x10 2. "EE1POL,External Event 1 Polarity" "0,1" bitfld.long 0x10 0.--1. "EE1SRC,External Event 1 Source" "0,1,2,3" line.long 0x14 "EECR2,Timer External Event Control Register" bitfld.long 0x14 27.--28. "EE10SNS,External Event 10" "0,1,2,3" bitfld.long 0x14 26. "EE10POL,External Event 10 Polarity" "0,1" bitfld.long 0x14 24.--25. "EE10SRC,External Event 10 Source" "0,1,2,3" bitfld.long 0x14 21.--22. "EE9SNS,External Event 9" "0,1,2,3" bitfld.long 0x14 20. "EE9POL,External Event 9 Polarity" "0,1" bitfld.long 0x14 18.--19. "EE9SRC,External Event 9 Source" "0,1,2,3" bitfld.long 0x14 15.--16. "EE8SNS,External Event 8" "0,1,2,3" bitfld.long 0x14 14. "EE8POL,External Event 8 Polarity" "0,1" bitfld.long 0x14 12.--13. "EE8SRC,External Event 8 Source" "0,1,2,3" newline bitfld.long 0x14 9.--10. "EE7SNS,External Event 7" "0,1,2,3" bitfld.long 0x14 8. "EE7POL,External Event 7 Polarity" "0,1" bitfld.long 0x14 6.--7. "EE7SRC,External Event 7 Source" "0,1,2,3" bitfld.long 0x14 3.--4. "EE6SNS,External Event 6" "0,1,2,3" bitfld.long 0x14 2. "EE6POL,External Event 6 Polarity" "0,1" bitfld.long 0x14 0.--1. "EE6SRC,External Event 6 Source" "0,1,2,3" line.long 0x18 "EECR3,Timer External Event Control Register" bitfld.long 0x18 27.--28. "EE10SNS,EE10SNS" "0,1,2,3" bitfld.long 0x18 26. "EE10POL,EE10POL" "0,1" bitfld.long 0x18 24.--25. "EE10SRC,EE10SRC" "0,1,2,3" bitfld.long 0x18 21.--22. "EE9SNS,EE9SNS" "0,1,2,3" bitfld.long 0x18 20. "EE9POL,EE9POL" "0,1" bitfld.long 0x18 18.--19. "EE9SRC,EE9SRC" "0,1,2,3" bitfld.long 0x18 15.--16. "EE8SNS,EE8SNS" "0,1,2,3" bitfld.long 0x18 14. "EE8POL,EE8POL" "0,1" bitfld.long 0x18 12.--13. "EE8SRC,EE8SRC" "0,1,2,3" newline bitfld.long 0x18 9.--10. "EE7SNS,EE7SNS" "0,1,2,3" bitfld.long 0x18 8. "EE7POL,EE7POL" "0,1" bitfld.long 0x18 6.--7. "EE7SRC,EE7SRC" "0,1,2,3" bitfld.long 0x18 3.--4. "EE6SNS,EE6SNS" "0,1,2,3" bitfld.long 0x18 2. "EE6POL,EE6POL" "0,1" bitfld.long 0x18 0.--1. "EE6SRC,EE6SRC" "0,1,2,3" line.long 0x1C "ADC1R,ADC Trigger 1 Register" bitfld.long 0x1C 31. "AD1TEPER,ADC trigger 1 on Timer E" "0,1" bitfld.long 0x1C 30. "AD1TEC4,ADC trigger 1 on Timer E compare" "0,1" bitfld.long 0x1C 29. "AD1TEC3,ADC trigger 1 on Timer E compare" "0,1" bitfld.long 0x1C 28. "AD1TEC2,ADC trigger 1 on Timer E compare" "0,1" bitfld.long 0x1C 27. "AD1TDPER,ADC trigger 1 on Timer D" "0,1" bitfld.long 0x1C 26. "AD1TDC4,ADC trigger 1 on Timer D compare" "0,1" bitfld.long 0x1C 25. "AD1TDC3,ADC trigger 1 on Timer D compare" "0,1" bitfld.long 0x1C 24. "AD1TDC2,ADC trigger 1 on Timer D compare" "0,1" bitfld.long 0x1C 23. "AD1TCPER,ADC trigger 1 on Timer C" "0,1" newline bitfld.long 0x1C 22. "AD1TCC4,ADC trigger 1 on Timer C compare" "0,1" bitfld.long 0x1C 21. "AD1TCC3,ADC trigger 1 on Timer C compare" "0,1" bitfld.long 0x1C 20. "AD1TCC2,ADC trigger 1 on Timer C compare" "0,1" bitfld.long 0x1C 19. "AD1TBRST,ADC trigger 1 on Timer B" "0,1" bitfld.long 0x1C 18. "AD1TBPER,ADC trigger 1 on Timer B" "0,1" bitfld.long 0x1C 17. "AD1TBC4,ADC trigger 1 on Timer B compare" "0,1" bitfld.long 0x1C 16. "AD1TBC3,ADC trigger 1 on Timer B compare" "0,1" bitfld.long 0x1C 15. "AD1TBC2,ADC trigger 1 on Timer B compare" "0,1" bitfld.long 0x1C 14. "AD1TARST,ADC trigger 1 on Timer A" "0,1" newline bitfld.long 0x1C 13. "AD1TAPER,ADC trigger 1 on Timer A" "0,1" bitfld.long 0x1C 12. "AD1TAC4,ADC trigger 1 on Timer A compare" "0,1" bitfld.long 0x1C 11. "AD1TAC3,ADC trigger 1 on Timer A compare" "0,1" bitfld.long 0x1C 10. "AD1TAC2,ADC trigger 1 on Timer A compare" "0,1" bitfld.long 0x1C 9. "AD1EEV5,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 8. "AD1EEV4,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 7. "AD1EEV3,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 6. "AD1EEV2,ADC trigger 1 on External Event" "0,1" bitfld.long 0x1C 5. "AD1EEV1,ADC trigger 1 on External Event" "0,1" newline bitfld.long 0x1C 4. "AD1MPER,ADC trigger 1 on Master" "0,1" bitfld.long 0x1C 3. "AD1MC4,ADC trigger 1 on Master Compare" "0,1" bitfld.long 0x1C 2. "AD1MC3,ADC trigger 1 on Master Compare" "0,1" bitfld.long 0x1C 1. "AD1MC2,ADC trigger 1 on Master Compare" "0,1" bitfld.long 0x1C 0. "AD1MC1,ADC trigger 1 on Master Compare" "0,1" line.long 0x20 "ADC2R,ADC Trigger 2 Register" bitfld.long 0x20 31. "AD2TERST,ADC trigger 2 on Timer E" "0,1" bitfld.long 0x20 30. "AD2TEC4,ADC trigger 2 on Timer E compare" "0,1" bitfld.long 0x20 29. "AD2TEC3,ADC trigger 2 on Timer E compare" "0,1" bitfld.long 0x20 28. "AD2TEC2,ADC trigger 2 on Timer E compare" "0,1" bitfld.long 0x20 27. "AD2TDRST,ADC trigger 2 on Timer D" "0,1" bitfld.long 0x20 26. "AD2TDPER,ADC trigger 2 on Timer D" "0,1" bitfld.long 0x20 25. "AD2TDC4,ADC trigger 2 on Timer D compare" "0,1" bitfld.long 0x20 24. "AD2TDC3,ADC trigger 2 on Timer D compare" "0,1" bitfld.long 0x20 23. "AD2TDC2,ADC trigger 2 on Timer D compare" "0,1" newline bitfld.long 0x20 22. "AD2TCRST,ADC trigger 2 on Timer C" "0,1" bitfld.long 0x20 21. "AD2TCPER,ADC trigger 2 on Timer C" "0,1" bitfld.long 0x20 20. "AD2TCC4,ADC trigger 2 on Timer C compare" "0,1" bitfld.long 0x20 19. "AD2TCC3,ADC trigger 2 on Timer C compare" "0,1" bitfld.long 0x20 18. "AD2TCC2,ADC trigger 2 on Timer C compare" "0,1" bitfld.long 0x20 17. "AD2TBPER,ADC trigger 2 on Timer B" "0,1" bitfld.long 0x20 16. "AD2TBC4,ADC trigger 2 on Timer B compare" "0,1" bitfld.long 0x20 15. "AD2TBC3,ADC trigger 2 on Timer B compare" "0,1" bitfld.long 0x20 14. "AD2TBC2,ADC trigger 2 on Timer B compare" "0,1" newline bitfld.long 0x20 13. "AD2TAPER,ADC trigger 2 on Timer A" "0,1" bitfld.long 0x20 12. "AD2TAC4,ADC trigger 2 on Timer A compare" "0,1" bitfld.long 0x20 11. "AD2TAC3,ADC trigger 2 on Timer A compare" "0,1" bitfld.long 0x20 10. "AD2TAC2,ADC trigger 2 on Timer A compare" "0,1" bitfld.long 0x20 9. "AD2EEV10,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 8. "AD2EEV9,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 7. "AD2EEV8,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 6. "AD2EEV7,ADC trigger 2 on External Event" "0,1" bitfld.long 0x20 5. "AD2EEV6,ADC trigger 2 on External Event" "0,1" newline bitfld.long 0x20 4. "AD2MPER,ADC trigger 2 on Master" "0,1" bitfld.long 0x20 3. "AD2MC4,ADC trigger 2 on Master Compare" "0,1" bitfld.long 0x20 2. "AD2MC3,ADC trigger 2 on Master Compare" "0,1" bitfld.long 0x20 1. "AD2MC2,ADC trigger 2 on Master Compare" "0,1" bitfld.long 0x20 0. "AD2MC1,ADC trigger 2 on Master Compare" "0,1" line.long 0x24 "ADC3R,ADC Trigger 3 Register" bitfld.long 0x24 31. "AD1TEPER,AD1TEPER" "0,1" bitfld.long 0x24 30. "AD1TEC4,AD1TEC4" "0,1" bitfld.long 0x24 29. "AD1TEC3,AD1TEC3" "0,1" bitfld.long 0x24 28. "AD1TEC2,AD1TEC2" "0,1" bitfld.long 0x24 27. "AD1TDPER,AD1TDPER" "0,1" bitfld.long 0x24 26. "AD1TDC4,AD1TDC4" "0,1" bitfld.long 0x24 25. "AD1TDC3,AD1TDC3" "0,1" bitfld.long 0x24 24. "AD1TDC2,AD1TDC2" "0,1" bitfld.long 0x24 23. "AD1TCPER,AD1TCPER" "0,1" newline bitfld.long 0x24 22. "AD1TCC4,AD1TCC4" "0,1" bitfld.long 0x24 21. "AD1TCC3,AD1TCC3" "0,1" bitfld.long 0x24 20. "AD1TCC2,AD1TCC2" "0,1" bitfld.long 0x24 19. "AD1TBRST,AD1TBRST" "0,1" bitfld.long 0x24 18. "AD1TBPER,AD1TBPER" "0,1" bitfld.long 0x24 17. "AD1TBC4,AD1TBC4" "0,1" bitfld.long 0x24 16. "AD1TBC3,AD1TBC3" "0,1" bitfld.long 0x24 15. "AD1TBC2,AD1TBC2" "0,1" bitfld.long 0x24 14. "AD1TARST,AD1TARST" "0,1" newline bitfld.long 0x24 13. "AD1TAPER,AD1TAPER" "0,1" bitfld.long 0x24 12. "AD1TAC4,AD1TAC4" "0,1" bitfld.long 0x24 11. "AD1TAC3,AD1TAC3" "0,1" bitfld.long 0x24 10. "AD1TAC2,AD1TAC2" "0,1" bitfld.long 0x24 9. "AD1EEV5,AD1EEV5" "0,1" bitfld.long 0x24 8. "AD1EEV4,AD1EEV4" "0,1" bitfld.long 0x24 7. "AD1EEV3,AD1EEV3" "0,1" bitfld.long 0x24 6. "AD1EEV2,AD1EEV2" "0,1" bitfld.long 0x24 5. "AD1EEV1,AD1EEV1" "0,1" newline bitfld.long 0x24 4. "AD1MPER,AD1MPER" "0,1" bitfld.long 0x24 3. "AD1MC4,AD1MC4" "0,1" bitfld.long 0x24 2. "AD1MC3,AD1MC3" "0,1" bitfld.long 0x24 1. "AD1MC2,AD1MC2" "0,1" bitfld.long 0x24 0. "AD1MC1,AD1MC1" "0,1" line.long 0x28 "ADC4R,ADC Trigger 4 Register" bitfld.long 0x28 31. "AD2TERST,AD2TERST" "0,1" bitfld.long 0x28 30. "AD2TEC4,AD2TEC4" "0,1" bitfld.long 0x28 29. "AD2TEC3,AD2TEC3" "0,1" bitfld.long 0x28 28. "AD2TEC2,AD2TEC2" "0,1" bitfld.long 0x28 27. "AD2TDRST,AD2TDRST" "0,1" bitfld.long 0x28 26. "AD2TDPER,AD2TDPER" "0,1" bitfld.long 0x28 25. "AD2TDC4,AD2TDC4" "0,1" bitfld.long 0x28 24. "AD2TDC3,AD2TDC3" "0,1" bitfld.long 0x28 23. "AD2TDC2,AD2TDC2" "0,1" newline bitfld.long 0x28 22. "AD2TCRST,AD2TCRST" "0,1" bitfld.long 0x28 21. "AD2TCPER,AD2TCPER" "0,1" bitfld.long 0x28 20. "AD2TCC4,AD2TCC4" "0,1" bitfld.long 0x28 19. "AD2TCC3,AD2TCC3" "0,1" bitfld.long 0x28 18. "AD2TCC2,AD2TCC2" "0,1" bitfld.long 0x28 17. "AD2TBPER,AD2TBPER" "0,1" bitfld.long 0x28 16. "AD2TBC4,AD2TBC4" "0,1" bitfld.long 0x28 15. "AD2TBC3,AD2TBC3" "0,1" bitfld.long 0x28 14. "AD2TBC2,AD2TBC2" "0,1" newline bitfld.long 0x28 13. "AD2TAPER,AD2TAPER" "0,1" bitfld.long 0x28 12. "AD2TAC4,AD2TAC4" "0,1" bitfld.long 0x28 11. "AD2TAC3,AD2TAC3" "0,1" bitfld.long 0x28 10. "AD2TAC2,AD2TAC2" "0,1" bitfld.long 0x28 9. "AD2EEV10,AD2EEV10" "0,1" bitfld.long 0x28 8. "AD2EEV9,AD2EEV9" "0,1" bitfld.long 0x28 7. "AD2EEV8,AD2EEV8" "0,1" bitfld.long 0x28 6. "AD2EEV7,AD2EEV7" "0,1" bitfld.long 0x28 5. "AD2EEV6,AD2EEV6" "0,1" newline bitfld.long 0x28 4. "AD2MPER,AD2MPER" "0,1" bitfld.long 0x28 3. "AD2MC4,AD2MC4" "0,1" bitfld.long 0x28 2. "AD2MC3,AD2MC3" "0,1" bitfld.long 0x28 1. "AD2MC2,AD2MC2" "0,1" bitfld.long 0x28 0. "AD2MC1,AD2MC1" "0,1" line.long 0x2C "DLLCR,DLL Control Register" bitfld.long 0x2C 2.--3. "CALRTE,DLL Calibration rate" "0,1,2,3" bitfld.long 0x2C 1. "CALEN,DLL Calibration Enable" "0,1" bitfld.long 0x2C 0. "CAL,DLL Calibration Start" "0,1" line.long 0x30 "FLTINR1,HRTIM Fault Input Register 1" bitfld.long 0x30 31. "FLT4LCK,FLT4LCK" "0,1" hexmask.long.byte 0x30 27.--30. 1. "FLT4F,FLT4F" bitfld.long 0x30 26. "FLT4SRC,FLT4SRC" "0,1" bitfld.long 0x30 25. "FLT4P,FLT4P" "0,1" bitfld.long 0x30 24. "FLT4E,FLT4E" "0,1" bitfld.long 0x30 23. "FLT3LCK,FLT3LCK" "0,1" hexmask.long.byte 0x30 19.--22. 1. "FLT3F,FLT3F" bitfld.long 0x30 18. "FLT3SRC,FLT3SRC" "0,1" bitfld.long 0x30 17. "FLT3P,FLT3P" "0,1" newline bitfld.long 0x30 16. "FLT3E,FLT3E" "0,1" bitfld.long 0x30 15. "FLT2LCK,FLT2LCK" "0,1" hexmask.long.byte 0x30 11.--14. 1. "FLT2F,FLT2F" bitfld.long 0x30 10. "FLT2SRC,FLT2SRC" "0,1" bitfld.long 0x30 9. "FLT2P,FLT2P" "0,1" bitfld.long 0x30 8. "FLT2E,FLT2E" "0,1" bitfld.long 0x30 7. "FLT1LCK,FLT1LCK" "0,1" hexmask.long.byte 0x30 3.--6. 1. "FLT1F,FLT1F" bitfld.long 0x30 2. "FLT1SRC,FLT1SRC" "0,1" newline bitfld.long 0x30 1. "FLT1P,FLT1P" "0,1" bitfld.long 0x30 0. "FLT1E,FLT1E" "0,1" line.long 0x34 "FLTINR2,HRTIM Fault Input Register 2" bitfld.long 0x34 24.--25. "FLTSD,FLTSD" "0,1,2,3" bitfld.long 0x34 7. "FLT5LCK,FLT5LCK" "0,1" hexmask.long.byte 0x34 3.--6. 1. "FLT5F,FLT5F" bitfld.long 0x34 2. "FLT5SRC,FLT5SRC" "0,1" bitfld.long 0x34 1. "FLT5P,FLT5P" "0,1" bitfld.long 0x34 0. "FLT5E,FLT5E" "0,1" line.long 0x38 "BDMUPDR,BDMUPDR" bitfld.long 0x38 9. "MCMP4,MCMP4" "0,1" bitfld.long 0x38 8. "MCMP3,MCMP3" "0,1" bitfld.long 0x38 7. "MCMP2,MCMP2" "0,1" bitfld.long 0x38 6. "MCMP1,MCMP1" "0,1" bitfld.long 0x38 5. "MREP,MREP" "0,1" bitfld.long 0x38 4. "MPER,MPER" "0,1" bitfld.long 0x38 3. "MCNT,MCNT" "0,1" bitfld.long 0x38 2. "MDIER,MDIER" "0,1" bitfld.long 0x38 1. "MICR,MICR" "0,1" newline bitfld.long 0x38 0. "MCR,MCR" "0,1" line.long 0x3C "BDTxUPR,Burst DMA Timerx update" bitfld.long 0x3C 20. "TIMxFLTR,HRTIM_FLTxR register update" "0,1" bitfld.long 0x3C 19. "TIMxOUTR,HRTIM_OUTxR register update" "0,1" bitfld.long 0x3C 18. "TIMxCHPR,HRTIM_CHPxR register update" "0,1" bitfld.long 0x3C 17. "TIMxRSTR,HRTIM_RSTxR register update" "0,1" bitfld.long 0x3C 16. "TIMxEEFR2,HRTIM_EEFxR2 register update" "0,1" bitfld.long 0x3C 15. "TIMxEEFR1,HRTIM_EEFxR1 register update" "0,1" bitfld.long 0x3C 14. "TIMxRST2R,HRTIM_RST2xR register update" "0,1" bitfld.long 0x3C 13. "TIMxSET2R,HRTIM_SET2xR register update" "0,1" bitfld.long 0x3C 12. "TIMxRST1R,HRTIM_RST1xR register update" "0,1" newline bitfld.long 0x3C 11. "TIMxSET1R,HRTIM_SET1xR register update" "0,1" bitfld.long 0x3C 10. "TIMx_DTxR,HRTIM_DTxR register update" "0,1" bitfld.long 0x3C 9. "TIMxCMP4,HRTIM_CMP4xR register update" "0,1" bitfld.long 0x3C 8. "TIMxCMP3,HRTIM_CMP3xR register update" "0,1" bitfld.long 0x3C 7. "TIMxCMP2,HRTIM_CMP2xR register update" "0,1" bitfld.long 0x3C 6. "TIMxCMP1,HRTIM_CMP1xR register update" "0,1" bitfld.long 0x3C 5. "TIMxREP,HRTIM_REPxR register update" "0,1" bitfld.long 0x3C 4. "TIMxPER,HRTIM_PERxR register update" "0,1" bitfld.long 0x3C 3. "TIMxCNT,HRTIM_CNTxR register update" "0,1" newline bitfld.long 0x3C 2. "TIMxDIER,HRTIM_TIMxDIER register update" "0,1" bitfld.long 0x3C 1. "TIMxICR,HRTIM_TIMxICR register update" "0,1" bitfld.long 0x3C 0. "TIMxCR,HRTIM_TIMxCR register update" "0,1" line.long 0x40 "BDMADR,Burst DMA Data Register" hexmask.long 0x40 0.--31. 1. "BDMADR,Burst DMA Data register" tree.end endif sif (cpuis("STM32H7B3*")) tree "HRTIM_Master" base ad:0x40017400 group.long 0x0++0x3 line.long 0x0 "MCR,Master Timer Control Register" bitfld.long 0x0 30.--31. "BRSTDMA,Burst DMA Update" "0,1,2,3" bitfld.long 0x0 29. "MREPU,Master Timer Repetition" "0,1" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 21. "TECEN,Timer E counter enable" "0,1" bitfld.long 0x0 20. "TDCEN,Timer D counter enable" "0,1" bitfld.long 0x0 19. "TCCEN,Timer C counter enable" "0,1" bitfld.long 0x0 18. "TBCEN,Timer B counter enable" "0,1" bitfld.long 0x0 17. "TACEN,Timer A counter enable" "0,1" bitfld.long 0x0 16. "MCEN,Master Counter enable" "0,1" newline bitfld.long 0x0 14.--15. "SYNC_SRC,Synchronization source" "0,1,2,3" bitfld.long 0x0 12.--13. "SYNC_OUT,Synchronization output" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTM,Synchronization Starts" "0,1" bitfld.long 0x0 10. "SYNCRSTM,Synchronization Resets" "0,1" bitfld.long 0x0 8.--9. "SYNC_IN,ynchronization input" "0,1,2,3" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" bitfld.long 0x0 4. "RETRIG,Master Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Master Continuous mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "CK_PSC,HRTIM Master Clock" rgroup.long 0x4++0x3 line.long 0x0 "MISR,Master Timer Interrupt Status" bitfld.long 0x0 6. "MUPD,Master Update Interrupt" "0,1" bitfld.long 0x0 5. "SYNC,Sync Input Interrupt Flag" "0,1" bitfld.long 0x0 4. "MREP,Master Repetition Interrupt" "0,1" bitfld.long 0x0 3. "MCMP4,Master Compare 4 Interrupt" "0,1" bitfld.long 0x0 2. "MCMP3,Master Compare 3 Interrupt" "0,1" bitfld.long 0x0 1. "MCMP2,Master Compare 2 Interrupt" "0,1" bitfld.long 0x0 0. "MCMP1,Master Compare 1 Interrupt" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "MICR,Master Timer Interrupt Clear" bitfld.long 0x0 6. "MUPDC,Master update Interrupt flag" "0,1" bitfld.long 0x0 5. "SYNCC,Sync Input Interrupt flag" "0,1" bitfld.long 0x0 4. "MREPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "MCMP4C,Master Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "MCMP3C,Master Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "MCMP2C,Master Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "MCMP1C,Master Compare 1 Interrupt flag" "0,1" group.long 0xC++0x13 line.long 0x0 "MDIER4,MDIER4" bitfld.long 0x0 22. "MUPDDE,MUPDDE" "0,1" bitfld.long 0x0 21. "SYNCDE,SYNCDE" "0,1" bitfld.long 0x0 20. "MREPDE,MREPDE" "0,1" bitfld.long 0x0 19. "MCMP4DE,MCMP4DE" "0,1" bitfld.long 0x0 18. "MCMP3DE,MCMP3DE" "0,1" bitfld.long 0x0 17. "MCMP2DE,MCMP2DE" "0,1" bitfld.long 0x0 16. "MCMP1DE,MCMP1DE" "0,1" bitfld.long 0x0 6. "MUPDIE,MUPDIE" "0,1" bitfld.long 0x0 5. "SYNCIE,SYNCIE" "0,1" bitfld.long 0x0 4. "MREPIE,MREPIE" "0,1" newline bitfld.long 0x0 3. "MCMP4IE,MCMP4IE" "0,1" bitfld.long 0x0 2. "MCMP3IE,MCMP3IE" "0,1" bitfld.long 0x0 1. "MCMP2IE,MCMP2IE" "0,1" bitfld.long 0x0 0. "MCMP1IE,MCMP1IE" "0,1" line.long 0x4 "MCNTR,Master Timer Counter Register" hexmask.long.word 0x4 0.--15. 1. "MCNT,Counter value" line.long 0x8 "MPER,Master Timer Period Register" hexmask.long.word 0x8 0.--15. 1. "MPER,Master Timer Period value" line.long 0xC "MREP,Master Timer Repetition" hexmask.long.byte 0xC 0.--7. 1. "MREP,Master Timer Repetition counter" line.long 0x10 "MCMP1R,Master Timer Compare 1" hexmask.long.word 0x10 0.--15. 1. "MCMP1,Master Timer Compare 1" group.long 0x24++0xB line.long 0x0 "MCMP2R,Master Timer Compare 2" hexmask.long.word 0x0 0.--15. 1. "MCMP2,Master Timer Compare 2" line.long 0x4 "MCMP3R,Master Timer Compare 3" hexmask.long.word 0x4 0.--15. 1. "MCMP3,Master Timer Compare 3" line.long 0x8 "MCMP4R,Master Timer Compare 4" hexmask.long.word 0x8 0.--15. 1. "MCMP4,Master Timer Compare 4" tree.end tree "HRTIM_TIMA" base ad:0x40017480 group.long 0x0++0x3 line.long 0x0 "TIMACR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" rgroup.long 0x4++0x3 line.long 0x0 "TIMAISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMAICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMADIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTAR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERAR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPAR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1AR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CAR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2AR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3AR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4AR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1AR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2AR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTAR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" newline hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETA1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTA1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETA2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTA2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFAR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFAR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTAR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 24. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 23. "TIMCCMP2,Timer C Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 21. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 20. "TIMBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x1C 19. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPAR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1ACR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2ACR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTAR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" newline bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTAR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end tree "HRTIM_TIMB" base ad:0x40017500 group.long 0x0++0x3 line.long 0x0 "TIMBCR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" rgroup.long 0x4++0x3 line.long 0x0 "TIMBISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMBICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMBDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERBR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPBR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1BR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CBR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2BR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3BR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4BR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1BR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2BR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTBR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" newline hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETB1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTB1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETB2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTB2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFBR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFBR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTBR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 24. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 23. "TIMCCMP2,Timer C Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPBR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1BCR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2BCR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTBR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" newline bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTBR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end tree "HRTIM_TIMC" base ad:0x40017580 group.long 0x0++0x3 line.long 0x0 "TIMCCR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" rgroup.long 0x4++0x3 line.long 0x0 "TIMCISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMCICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMCDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTCR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERCR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPCR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1CR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CCR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2CR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3CR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4CR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1CR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2CR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTCR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" newline hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETC1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTC1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETC2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTC2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFCR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFCR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTCR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 26. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 25. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPCR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1CCR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2CCR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" newline bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTCR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" newline bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTCR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end tree "HRTIM_TIMD" base ad:0x40017600 group.long 0x0++0x3 line.long 0x0 "TIMDCR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" rgroup.long 0x4++0x3 line.long 0x0 "TIMDISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMDICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMDDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTDR,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERDR,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPDR,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1DR,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CDR,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2DR,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3DR,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4DR,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1DR,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2DR,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTDR,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" newline hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETD1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTD1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETD2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTD2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFDR1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFDR2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTDR,TimerA Reset Register" bitfld.long 0x1C 30. "TIMECMP4,Timer E Compare 4" "0,1" bitfld.long 0x1C 29. "TIMECMP2,Timer E Compare 2" "0,1" bitfld.long 0x1C 28. "TIMECMP1,Timer E Compare 1" "0,1" bitfld.long 0x1C 27. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 26. "TIMCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x1C 25. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPDR,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1DCR,Timerx Capture 2 Control" bitfld.long 0x24 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x24 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x24 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x24 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2DCR,CPT2xCR" bitfld.long 0x28 31. "TECMP2,Timer E Compare 2" "0,1" bitfld.long 0x28 30. "TECMP1,Timer E Compare 1" "0,1" bitfld.long 0x28 29. "TE1RST,Timer E output 1 Reset" "0,1" bitfld.long 0x28 28. "TE1SET,Timer E output 1 Set" "0,1" bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTDR,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" newline bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTDR,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end tree "HRTIM_TIME" base ad:0x40017680 group.long 0x0++0x3 line.long 0x0 "TIMECR,Timerx Control Register" hexmask.long.byte 0x0 28.--31. 1. "UPDGAT,Update Gating" bitfld.long 0x0 27. "PREEN,Preload enable" "0,1" bitfld.long 0x0 25.--26. "DACSYNC,AC Synchronization" "0,1,2,3" bitfld.long 0x0 24. "MSTU,Master Timer update" "0,1" bitfld.long 0x0 23. "TEU,TEU" "0,1" bitfld.long 0x0 22. "TDU,TDU" "0,1" bitfld.long 0x0 21. "TCU,TCU" "0,1" bitfld.long 0x0 20. "TBU,TBU" "0,1" newline bitfld.long 0x0 18. "TxRSTU,Timerx reset update" "0,1" bitfld.long 0x0 17. "TxREPU,Timer x Repetition update" "0,1" bitfld.long 0x0 14.--15. "DELCMP4,Delayed CMP4 mode" "0,1,2,3" bitfld.long 0x0 12.--13. "DELCMP2,Delayed CMP2 mode" "0,1,2,3" bitfld.long 0x0 11. "SYNCSTRTx,Synchronization Starts Timer" "0,1" bitfld.long 0x0 10. "SYNCRSTx,Synchronization Resets Timer" "0,1" bitfld.long 0x0 6. "PSHPLL,Push-Pull mode enable" "0,1" bitfld.long 0x0 5. "HALF,Half mode enable" "0,1" newline bitfld.long 0x0 4. "RETRIG,Re-triggerable mode" "0,1" bitfld.long 0x0 3. "CONT,Continuous mode" "0,1" hexmask.long.byte 0x0 0.--3. 1. "CK_PSCx,HRTIM Timer x Clock" rgroup.long 0x4++0x3 line.long 0x0 "TIMEISR,Timerx Interrupt Status" bitfld.long 0x0 19. "O2STAT,Output 2 State" "0,1" bitfld.long 0x0 18. "O1STAT,Output 1 State" "0,1" bitfld.long 0x0 17. "IPPSTAT,Idle Push Pull Status" "0,1" bitfld.long 0x0 16. "CPPSTAT,Current Push Pull Status" "0,1" bitfld.long 0x0 14. "DLYPRT,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RST,Reset Interrupt Flag" "0,1" bitfld.long 0x0 12. "RSTx2,Output 2 Reset Interrupt" "0,1" bitfld.long 0x0 11. "SETx2,Output 2 Set Interrupt" "0,1" newline bitfld.long 0x0 10. "RSTx1,Output 1 Reset Interrupt" "0,1" bitfld.long 0x0 9. "SETx1,Output 1 Set Interrupt" "0,1" bitfld.long 0x0 8. "CPT2,Capture2 Interrupt Flag" "0,1" bitfld.long 0x0 7. "CPT1,Capture1 Interrupt Flag" "0,1" bitfld.long 0x0 6. "UPD,Update Interrupt Flag" "0,1" bitfld.long 0x0 4. "REP,Repetition Interrupt Flag" "0,1" bitfld.long 0x0 3. "CMP4,Compare 4 Interrupt Flag" "0,1" bitfld.long 0x0 2. "CMP3,Compare 3 Interrupt Flag" "0,1" newline bitfld.long 0x0 1. "CMP2,Compare 2 Interrupt Flag" "0,1" bitfld.long 0x0 0. "CMP1,Compare 1 Interrupt Flag" "0,1" wgroup.long 0x8++0x3 line.long 0x0 "TIMEICR,Timerx Interrupt Clear" bitfld.long 0x0 14. "DLYPRTC,Delayed Protection Flag" "0,1" bitfld.long 0x0 13. "RSTC,Reset Interrupt flag Clear" "0,1" bitfld.long 0x0 12. "RSTx2C,Output 2 Reset flag Clear" "0,1" bitfld.long 0x0 11. "SET2xC,Output 2 Set flag Clear" "0,1" bitfld.long 0x0 10. "RSTx1C,Output 1 Reset flag Clear" "0,1" bitfld.long 0x0 9. "SET1xC,Output 1 Set flag Clear" "0,1" bitfld.long 0x0 8. "CPT2C,Capture2 Interrupt flag" "0,1" bitfld.long 0x0 7. "CPT1C,Capture1 Interrupt flag" "0,1" newline bitfld.long 0x0 6. "UPDC,Update Interrupt flag" "0,1" bitfld.long 0x0 4. "REPC,Repetition Interrupt flag" "0,1" bitfld.long 0x0 3. "CMP4C,Compare 4 Interrupt flag" "0,1" bitfld.long 0x0 2. "CMP3C,Compare 3 Interrupt flag" "0,1" bitfld.long 0x0 1. "CMP2C,Compare 2 Interrupt flag" "0,1" bitfld.long 0x0 0. "CMP1C,Compare 1 Interrupt flag" "0,1" group.long 0xC++0x23 line.long 0x0 "TIMEDIER5,TIMxDIER5" bitfld.long 0x0 30. "DLYPRTDE,DLYPRTDE" "0,1" bitfld.long 0x0 29. "RSTDE,RSTDE" "0,1" bitfld.long 0x0 28. "RSTx2DE,RSTx2DE" "0,1" bitfld.long 0x0 27. "SETx2DE,SETx2DE" "0,1" bitfld.long 0x0 26. "RSTx1DE,RSTx1DE" "0,1" bitfld.long 0x0 25. "SET1xDE,SET1xDE" "0,1" bitfld.long 0x0 24. "CPT2DE,CPT2DE" "0,1" bitfld.long 0x0 23. "CPT1DE,CPT1DE" "0,1" newline bitfld.long 0x0 22. "UPDDE,UPDDE" "0,1" bitfld.long 0x0 20. "REPDE,REPDE" "0,1" bitfld.long 0x0 19. "CMP4DE,CMP4DE" "0,1" bitfld.long 0x0 18. "CMP3DE,CMP3DE" "0,1" bitfld.long 0x0 17. "CMP2DE,CMP2DE" "0,1" bitfld.long 0x0 16. "CMP1DE,CMP1DE" "0,1" bitfld.long 0x0 14. "DLYPRTIE,DLYPRTIE" "0,1" bitfld.long 0x0 13. "RSTIE,RSTIE" "0,1" newline bitfld.long 0x0 12. "RSTx2IE,RSTx2IE" "0,1" bitfld.long 0x0 11. "SETx2IE,SETx2IE" "0,1" bitfld.long 0x0 10. "RSTx1IE,RSTx1IE" "0,1" bitfld.long 0x0 9. "SET1xIE,SET1xIE" "0,1" bitfld.long 0x0 8. "CPT2IE,CPT2IE" "0,1" bitfld.long 0x0 7. "CPT1IE,CPT1IE" "0,1" bitfld.long 0x0 6. "UPDIE,UPDIE" "0,1" bitfld.long 0x0 4. "REPIE,REPIE" "0,1" newline bitfld.long 0x0 3. "CMP4IE,CMP4IE" "0,1" bitfld.long 0x0 2. "CMP3IE,CMP3IE" "0,1" bitfld.long 0x0 1. "CMP2IE,CMP2IE" "0,1" bitfld.long 0x0 0. "CMP1IE,CMP1IE" "0,1" line.long 0x4 "CNTER,Timerx Counter Register" hexmask.long.word 0x4 0.--15. 1. "CNTx,Timerx Counter value" line.long 0x8 "PERER,Timerx Period Register" hexmask.long.word 0x8 0.--15. 1. "PERx,Timerx Period value" line.long 0xC "REPER,Timerx Repetition Register" hexmask.long.byte 0xC 0.--7. 1. "REPx,Timerx Repetition counter" line.long 0x10 "CMP1ER,Timerx Compare 1 Register" hexmask.long.word 0x10 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x14 "CMP1CER,Timerx Compare 1 Compound" hexmask.long.byte 0x14 16.--23. 1. "REPx,Timerx Repetition value (aliased from" hexmask.long.word 0x14 0.--15. 1. "CMP1x,Timerx Compare 1 value" line.long 0x18 "CMP2ER,Timerx Compare 2 Register" hexmask.long.word 0x18 0.--15. 1. "CMP2x,Timerx Compare 2 value" line.long 0x1C "CMP3ER,Timerx Compare 3 Register" hexmask.long.word 0x1C 0.--15. 1. "CMP3x,Timerx Compare 3 value" line.long 0x20 "CMP4ER,Timerx Compare 4 Register" hexmask.long.word 0x20 0.--15. 1. "CMP4x,Timerx Compare 4 value" rgroup.long 0x30++0x7 line.long 0x0 "CPT1ER,Timerx Capture 1 Register" hexmask.long.word 0x0 0.--15. 1. "CPT1x,Timerx Capture 1 value" line.long 0x4 "CPT2ER,Timerx Capture 2 Register" hexmask.long.word 0x4 0.--15. 1. "CPT2x,Timerx Capture 2 value" group.long 0x38++0x33 line.long 0x0 "DTER,Timerx Deadtime Register" bitfld.long 0x0 31. "DTFLKx,Deadtime Falling Lock" "0,1" bitfld.long 0x0 30. "DTFSLKx,Deadtime Falling Sign Lock" "0,1" bitfld.long 0x0 25. "SDTFx,Sign Deadtime Falling" "0,1" hexmask.long.word 0x0 16.--24. 1. "DTFx,Deadtime Falling value" bitfld.long 0x0 15. "DTRLKx,Deadtime Rising Lock" "0,1" bitfld.long 0x0 14. "DTRSLKx,Deadtime Rising Sign Lock" "0,1" hexmask.long.byte 0x0 10.--13. 1. "DTPRSC,Deadtime Prescaler" bitfld.long 0x0 9. "SDTRx,Sign Deadtime Rising value" "0,1" newline hexmask.long.word 0x0 0.--8. 1. "DTRx,Deadtime Rising value" line.long 0x4 "SETE1R,Timerx Output1 Set Register" bitfld.long 0x4 31. "UPDATE,Registers update (transfer preload to" "0,1" bitfld.long 0x4 30. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x4 29. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x4 28. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x4 27. "EXTEVNT7,External Event 7" "0,1" bitfld.long 0x4 26. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x4 25. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x4 24. "EXTEVNT4,External Event 4" "0,1" newline bitfld.long 0x4 23. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x4 22. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x4 21. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x4 20. "TIMEVNT9,Timer Event 9" "0,1" bitfld.long 0x4 19. "TIMEVNT8,Timer Event 8" "0,1" bitfld.long 0x4 18. "TIMEVNT7,Timer Event 7" "0,1" bitfld.long 0x4 17. "TIMEVNT6,Timer Event 6" "0,1" bitfld.long 0x4 16. "TIMEVNT5,Timer Event 5" "0,1" newline bitfld.long 0x4 15. "TIMEVNT4,Timer Event 4" "0,1" bitfld.long 0x4 14. "TIMEVNT3,Timer Event 3" "0,1" bitfld.long 0x4 13. "TIMEVNT2,Timer Event 2" "0,1" bitfld.long 0x4 12. "TIMEVNT1,Timer Event 1" "0,1" bitfld.long 0x4 11. "MSTCMP4,Master Compare 4" "0,1" bitfld.long 0x4 10. "MSTCMP3,Master Compare 3" "0,1" bitfld.long 0x4 9. "MSTCMP2,Master Compare 2" "0,1" bitfld.long 0x4 8. "MSTCMP1,Master Compare 1" "0,1" newline bitfld.long 0x4 7. "MSTPER,Master Period" "0,1" bitfld.long 0x4 6. "CMP4,Timer A compare 4" "0,1" bitfld.long 0x4 5. "CMP3,Timer A compare 3" "0,1" bitfld.long 0x4 4. "CMP2,Timer A compare 2" "0,1" bitfld.long 0x4 3. "CMP1,Timer A compare 1" "0,1" bitfld.long 0x4 2. "PER,Timer A Period" "0,1" bitfld.long 0x4 1. "RESYNC,Timer A resynchronizaton" "0,1" bitfld.long 0x4 0. "SST,Software Set trigger" "0,1" line.long 0x8 "RSTE1R,Timerx Output1 Reset Register" bitfld.long 0x8 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x8 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x8 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x8 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x8 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x8 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x8 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x8 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x8 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x8 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x8 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x8 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x8 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x8 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x8 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x8 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x8 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x8 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x8 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x8 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x8 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x8 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x8 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x8 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x8 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x8 6. "CMP4,CMP4" "0,1" bitfld.long 0x8 5. "CMP3,CMP3" "0,1" bitfld.long 0x8 4. "CMP2,CMP2" "0,1" bitfld.long 0x8 3. "CMP1,CMP1" "0,1" bitfld.long 0x8 2. "PER,PER" "0,1" bitfld.long 0x8 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x8 0. "SRT,SRT" "0,1" line.long 0xC "SETE2R,Timerx Output2 Set Register" bitfld.long 0xC 31. "UPDATE,UPDATE" "0,1" bitfld.long 0xC 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0xC 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0xC 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0xC 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0xC 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0xC 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0xC 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0xC 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0xC 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0xC 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0xC 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0xC 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0xC 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0xC 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0xC 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0xC 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0xC 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0xC 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0xC 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0xC 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0xC 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0xC 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0xC 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0xC 7. "MSTPER,MSTPER" "0,1" bitfld.long 0xC 6. "CMP4,CMP4" "0,1" bitfld.long 0xC 5. "CMP3,CMP3" "0,1" bitfld.long 0xC 4. "CMP2,CMP2" "0,1" bitfld.long 0xC 3. "CMP1,CMP1" "0,1" bitfld.long 0xC 2. "PER,PER" "0,1" bitfld.long 0xC 1. "RESYNC,RESYNC" "0,1" bitfld.long 0xC 0. "SST,SST" "0,1" line.long 0x10 "RSTE2R,Timerx Output2 Reset Register" bitfld.long 0x10 31. "UPDATE,UPDATE" "0,1" bitfld.long 0x10 30. "EXTEVNT10,EXTEVNT10" "0,1" bitfld.long 0x10 29. "EXTEVNT9,EXTEVNT9" "0,1" bitfld.long 0x10 28. "EXTEVNT8,EXTEVNT8" "0,1" bitfld.long 0x10 27. "EXTEVNT7,EXTEVNT7" "0,1" bitfld.long 0x10 26. "EXTEVNT6,EXTEVNT6" "0,1" bitfld.long 0x10 25. "EXTEVNT5,EXTEVNT5" "0,1" bitfld.long 0x10 24. "EXTEVNT4,EXTEVNT4" "0,1" newline bitfld.long 0x10 23. "EXTEVNT3,EXTEVNT3" "0,1" bitfld.long 0x10 22. "EXTEVNT2,EXTEVNT2" "0,1" bitfld.long 0x10 21. "EXTEVNT1,EXTEVNT1" "0,1" bitfld.long 0x10 20. "TIMEVNT9,TIMEVNT9" "0,1" bitfld.long 0x10 19. "TIMEVNT8,TIMEVNT8" "0,1" bitfld.long 0x10 18. "TIMEVNT7,TIMEVNT7" "0,1" bitfld.long 0x10 17. "TIMEVNT6,TIMEVNT6" "0,1" bitfld.long 0x10 16. "TIMEVNT5,TIMEVNT5" "0,1" newline bitfld.long 0x10 15. "TIMEVNT4,TIMEVNT4" "0,1" bitfld.long 0x10 14. "TIMEVNT3,TIMEVNT3" "0,1" bitfld.long 0x10 13. "TIMEVNT2,TIMEVNT2" "0,1" bitfld.long 0x10 12. "TIMEVNT1,TIMEVNT1" "0,1" bitfld.long 0x10 11. "MSTCMP4,MSTCMP4" "0,1" bitfld.long 0x10 10. "MSTCMP3,MSTCMP3" "0,1" bitfld.long 0x10 9. "MSTCMP2,MSTCMP2" "0,1" bitfld.long 0x10 8. "MSTCMP1,MSTCMP1" "0,1" newline bitfld.long 0x10 7. "MSTPER,MSTPER" "0,1" bitfld.long 0x10 6. "CMP4,CMP4" "0,1" bitfld.long 0x10 5. "CMP3,CMP3" "0,1" bitfld.long 0x10 4. "CMP2,CMP2" "0,1" bitfld.long 0x10 3. "CMP1,CMP1" "0,1" bitfld.long 0x10 2. "PER,PER" "0,1" bitfld.long 0x10 1. "RESYNC,RESYNC" "0,1" bitfld.long 0x10 0. "SRT,SRT" "0,1" line.long 0x14 "EEFER1,Timerx External Event Filtering Register" hexmask.long.byte 0x14 25.--28. 1. "EE5FLTR,External Event 5 filter" bitfld.long 0x14 24. "EE5LTCH,External Event 5 latch" "0,1" hexmask.long.byte 0x14 19.--22. 1. "EE4FLTR,External Event 4 filter" bitfld.long 0x14 18. "EE4LTCH,External Event 4 latch" "0,1" hexmask.long.byte 0x14 13.--16. 1. "EE3FLTR,External Event 3 filter" bitfld.long 0x14 12. "EE3LTCH,External Event 3 latch" "0,1" hexmask.long.byte 0x14 7.--10. 1. "EE2FLTR,External Event 2 filter" bitfld.long 0x14 6. "EE2LTCH,External Event 2 latch" "0,1" newline hexmask.long.byte 0x14 1.--4. 1. "EE1FLTR,External Event 1 filter" bitfld.long 0x14 0. "EE1LTCH,External Event 1 latch" "0,1" line.long 0x18 "EEFER2,Timerx External Event Filtering Register" hexmask.long.byte 0x18 25.--28. 1. "EE10FLTR,External Event 10 filter" bitfld.long 0x18 24. "EE10LTCH,External Event 10 latch" "0,1" hexmask.long.byte 0x18 19.--22. 1. "EE9FLTR,External Event 9 filter" bitfld.long 0x18 18. "EE9LTCH,External Event 9 latch" "0,1" hexmask.long.byte 0x18 13.--16. 1. "EE8FLTR,External Event 8 filter" bitfld.long 0x18 12. "EE8LTCH,External Event 8 latch" "0,1" hexmask.long.byte 0x18 7.--10. 1. "EE7FLTR,External Event 7 filter" bitfld.long 0x18 6. "EE7LTCH,External Event 7 latch" "0,1" newline hexmask.long.byte 0x18 1.--4. 1. "EE6FLTR,External Event 6 filter" bitfld.long 0x18 0. "EE6LTCH,External Event 6 latch" "0,1" line.long 0x1C "RSTER,TimerA Reset Register" bitfld.long 0x1C 30. "TIMDCMP4,Timer D Compare 4" "0,1" bitfld.long 0x1C 29. "TIMDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x1C 28. "TIMDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x1C 27. "TIMCCMP4,Timer C Compare 4" "0,1" bitfld.long 0x1C 26. "TIMCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x1C 25. "TIMCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x1C 24. "TIMBCMP4,Timer B Compare 4" "0,1" bitfld.long 0x1C 23. "TIMBCMP2,Timer B Compare 2" "0,1" newline bitfld.long 0x1C 22. "TIMBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x1C 21. "TIMACMP4,Timer A Compare 4" "0,1" bitfld.long 0x1C 20. "TIMACMP2,Timer A Compare 2" "0,1" bitfld.long 0x1C 19. "TIMACMP1,Timer A Compare 1" "0,1" bitfld.long 0x1C 18. "EXTEVNT10,External Event 10" "0,1" bitfld.long 0x1C 17. "EXTEVNT9,External Event 9" "0,1" bitfld.long 0x1C 16. "EXTEVNT8,External Event 8" "0,1" bitfld.long 0x1C 15. "EXTEVNT7,External Event 7" "0,1" newline bitfld.long 0x1C 14. "EXTEVNT6,External Event 6" "0,1" bitfld.long 0x1C 13. "EXTEVNT5,External Event 5" "0,1" bitfld.long 0x1C 12. "EXTEVNT4,External Event 4" "0,1" bitfld.long 0x1C 11. "EXTEVNT3,External Event 3" "0,1" bitfld.long 0x1C 10. "EXTEVNT2,External Event 2" "0,1" bitfld.long 0x1C 9. "EXTEVNT1,External Event 1" "0,1" bitfld.long 0x1C 8. "MSTCMP4,Master compare 4" "0,1" bitfld.long 0x1C 7. "MSTCMP3,Master compare 3" "0,1" newline bitfld.long 0x1C 6. "MSTCMP2,Master compare 2" "0,1" bitfld.long 0x1C 5. "MSTCMP1,Master compare 1" "0,1" bitfld.long 0x1C 4. "MSTPER,Master timer Period" "0,1" bitfld.long 0x1C 3. "CMP4,Timer A compare 4 reset" "0,1" bitfld.long 0x1C 2. "CMP2,Timer A compare 2 reset" "0,1" bitfld.long 0x1C 1. "UPDT,Timer A Update reset" "0,1" line.long 0x20 "CHPER,Timerx Chopper Register" hexmask.long.byte 0x20 7.--10. 1. "STRTPW,STRTPW" hexmask.long.byte 0x20 4.--7. 1. "CHPDTY,Timerx chopper duty cycle" hexmask.long.byte 0x20 0.--3. 1. "CHPFRQ,Timerx carrier frequency" line.long 0x24 "CPT1ECR,Timerx Capture 2 Control" bitfld.long 0x24 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x24 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x24 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x24 24. "TD1SET,Timer D output 1 Set" "0,1" bitfld.long 0x24 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x24 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x24 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x24 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x24 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x24 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x24 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x24 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x24 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x24 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x24 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x24 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x24 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x24 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x24 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x24 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x24 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x24 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x24 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x24 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x24 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x24 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x24 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x24 0. "SWCPT,Software Capture" "0,1" line.long 0x28 "CPT2ECR,CPT2xCR" bitfld.long 0x28 27. "TDCMP2,Timer D Compare 2" "0,1" bitfld.long 0x28 26. "TDCMP1,Timer D Compare 1" "0,1" bitfld.long 0x28 25. "TD1RST,Timer D output 1 Reset" "0,1" bitfld.long 0x28 24. "TD1SET,Timer D output 1 Set" "0,1" bitfld.long 0x28 23. "TCCMP2,Timer C Compare 2" "0,1" bitfld.long 0x28 22. "TCCMP1,Timer C Compare 1" "0,1" bitfld.long 0x28 21. "TC1RST,Timer C output 1 Reset" "0,1" bitfld.long 0x28 20. "TC1SET,Timer C output 1 Set" "0,1" newline bitfld.long 0x28 19. "TBCMP2,Timer B Compare 2" "0,1" bitfld.long 0x28 18. "TBCMP1,Timer B Compare 1" "0,1" bitfld.long 0x28 17. "TB1RST,Timer B output 1 Reset" "0,1" bitfld.long 0x28 16. "TB1SET,Timer B output 1 Set" "0,1" bitfld.long 0x28 15. "TACMP2,Timer A Compare 2" "0,1" bitfld.long 0x28 14. "TACMP1,Timer A Compare 1" "0,1" bitfld.long 0x28 13. "TA1RST,Timer A output 1 Reset" "0,1" bitfld.long 0x28 12. "TA1SET,Timer A output 1 Set" "0,1" newline bitfld.long 0x28 11. "EXEV10CPT,External Event 10 Capture" "0,1" bitfld.long 0x28 10. "EXEV9CPT,External Event 9 Capture" "0,1" bitfld.long 0x28 9. "EXEV8CPT,External Event 8 Capture" "0,1" bitfld.long 0x28 8. "EXEV7CPT,External Event 7 Capture" "0,1" bitfld.long 0x28 7. "EXEV6CPT,External Event 6 Capture" "0,1" bitfld.long 0x28 6. "EXEV5CPT,External Event 5 Capture" "0,1" bitfld.long 0x28 5. "EXEV4CPT,External Event 4 Capture" "0,1" bitfld.long 0x28 4. "EXEV3CPT,External Event 3 Capture" "0,1" newline bitfld.long 0x28 3. "EXEV2CPT,External Event 2 Capture" "0,1" bitfld.long 0x28 2. "EXEV1CPT,External Event 1 Capture" "0,1" bitfld.long 0x28 1. "UDPCPT,Update Capture" "0,1" bitfld.long 0x28 0. "SWCPT,Software Capture" "0,1" line.long 0x2C "OUTER,Timerx Output Register" bitfld.long 0x2C 23. "DIDL2,Output 2 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 22. "CHP2,Output 2 Chopper enable" "0,1" bitfld.long 0x2C 20.--21. "FAULT2,Output 2 Fault state" "0,1,2,3" bitfld.long 0x2C 19. "IDLES2,Output 2 Idle State" "0,1" bitfld.long 0x2C 18. "IDLEM2,Output 2 Idle mode" "0,1" bitfld.long 0x2C 17. "POL2,Output 2 polarity" "0,1" hexmask.long.byte 0x2C 10.--13. 1. "DLYPRT,Delayed Protection" bitfld.long 0x2C 9. "DLYPRTEN,Delayed Protection Enable" "0,1" newline bitfld.long 0x2C 8. "DTEN,Deadtime enable" "0,1" bitfld.long 0x2C 7. "DIDL1,Output 1 Deadtime upon burst mode Idle" "0,1" bitfld.long 0x2C 6. "CHP1,Output 1 Chopper enable" "0,1" bitfld.long 0x2C 4.--5. "FAULT1,Output 1 Fault state" "0,1,2,3" bitfld.long 0x2C 3. "IDLES1,Output 1 Idle State" "0,1" bitfld.long 0x2C 2. "IDLEM1,Output 1 Idle mode" "0,1" bitfld.long 0x2C 1. "POL1,Output 1 polarity" "0,1" line.long 0x30 "FLTER,Timerx Fault Register" bitfld.long 0x30 31. "FLTLCK,Fault sources Lock" "0,1" bitfld.long 0x30 4. "FLT5EN,Fault 5 enable" "0,1" bitfld.long 0x30 3. "FLT4EN,Fault 4 enable" "0,1" bitfld.long 0x30 2. "FLT3EN,Fault 3 enable" "0,1" bitfld.long 0x30 1. "FLT2EN,Fault 2 enable" "0,1" bitfld.long 0x30 0. "FLT1EN,Fault 1 enable" "0,1" tree.end endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) base ad:0x58026400 elif (cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) base ad:0x48020800 endif tree "HSEM (Hardware Semaphore)" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) group.long 0x0++0x7F line.long 0x0 "HSEM_R0,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "HSEM_R1,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "HSEM_R2,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "HSEM_R3,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "HSEM_R4,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "HSEM_R5,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "HSEM_R6,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "HSEM_R7,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "HSEM_R8,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "HSEM_R9,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "HSEM_R10,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "HSEM_R11,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "HSEM_R12,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "HSEM_R13,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "HSEM_R14,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "HSEM_R15,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "HSEM_R16,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "HSEM_R17,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "HSEM_R18,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "HSEM_R19,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "HSEM_R20,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "HSEM_R21,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "HSEM_R22,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "HSEM_R23,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "HSEM_R24,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "HSEM_R25,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "HSEM_R26,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "HSEM_R27,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "HSEM_R28,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "HSEM_R29,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "HSEM_R30,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "HSEM_R31,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" rgroup.long 0x80++0x7F line.long 0x0 "HSEM_RLR0,HSEM Read lock register" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "HSEM_RLR1,HSEM Read lock register" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x4 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "HSEM_RLR2,HSEM Read lock register" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x8 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "HSEM_RLR3,HSEM Read lock register" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0xC 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "HSEM_RLR4,HSEM Read lock register" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x10 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "HSEM_RLR5,HSEM Read lock register" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x14 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "HSEM_RLR6,HSEM Read lock register" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x18 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "HSEM_RLR7,HSEM Read lock register" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x1C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "HSEM_RLR8,HSEM Read lock register" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x20 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "HSEM_RLR9,HSEM Read lock register" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x24 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "HSEM_RLR10,HSEM Read lock register" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x28 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "HSEM_RLR11,HSEM Read lock register" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x2C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "HSEM_RLR12,HSEM Read lock register" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x30 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "HSEM_RLR13,HSEM Read lock register" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x34 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "HSEM_RLR14,HSEM Read lock register" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x38 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "HSEM_RLR15,HSEM Read lock register" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x3C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "HSEM_RLR16,HSEM Read lock register" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x40 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "HSEM_RLR17,HSEM Read lock register" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x44 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "HSEM_RLR18,HSEM Read lock register" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x48 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "HSEM_RLR19,HSEM Read lock register" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x4C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "HSEM_RLR20,HSEM Read lock register" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x50 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "HSEM_RLR21,HSEM Read lock register" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x54 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "HSEM_RLR22,HSEM Read lock register" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x58 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "HSEM_RLR23,HSEM Read lock register" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x5C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "HSEM_RLR24,HSEM Read lock register" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x60 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "HSEM_RLR25,HSEM Read lock register" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x64 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "HSEM_RLR26,HSEM Read lock register" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x68 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "HSEM_RLR27,HSEM Read lock register" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x6C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "HSEM_RLR28,HSEM Read lock register" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x70 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "HSEM_RLR29,HSEM Read lock register" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x74 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "HSEM_RLR30,HSEM Read lock register" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x78 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "HSEM_RLR31,HSEM Read lock register" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x7C 8.--11. 1. "COREID,Semaphore COREID" newline endif hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" group.long 0x140++0x7 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) hexmask.long.byte 0x0 8.--11. 1. "COREID,MasterID of semaphores to be" newline endif sif (cpuis("STM32H742*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,MasterID of semaphores to be" endif sif (cpuis("STM32H743*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,MasterID of semaphores to be" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,MasterID of semaphores to be" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x0 8.--15. 1. "MASTERID,MasterID of semaphores to be" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x0 8.--11. 1. "COREID,COREID of semaphores to be" endif line.long 0x4 "HSEM_KEYR,HSEM Interrupt clear register" hexmask.long.word 0x4 16.--31. 1. "KEY,Semaphore Clear Key" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x7F line.long 0x0 "R0,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "R1,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "R2,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "R3,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "R4,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "R5,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "R6,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "R7,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "R8,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "R9,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "R10,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "R11,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "R12,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "R13,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "R14,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "R15,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "R16,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "R17,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "R18,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "R19,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "R20,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "R21,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "R22,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "R23,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "R24,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "R25,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "R26,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "R27,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "R28,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "R29,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "R30,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "R31,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" rgroup.long 0x80++0x7F line.long 0x0 "RLR0,HSEM Read lock register" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "RLR1,HSEM Read lock register" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "RLR2,HSEM Read lock register" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "RLR3,HSEM Read lock register" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "RLR4,HSEM Read lock register" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "RLR5,HSEM Read lock register" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "RLR6,HSEM Read lock register" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "RLR7,HSEM Read lock register" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "RLR8,HSEM Read lock register" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "RLR9,HSEM Read lock register" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "RLR10,HSEM Read lock register" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "RLR11,HSEM Read lock register" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "RLR12,HSEM Read lock register" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "RLR13,HSEM Read lock register" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "RLR14,HSEM Read lock register" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "RLR15,HSEM Read lock register" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "RLR16,HSEM Read lock register" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "RLR17,HSEM Read lock register" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "RLR18,HSEM Read lock register" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "RLR19,HSEM Read lock register" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "RLR20,HSEM Read lock register" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "RLR21,HSEM Read lock register" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "RLR22,HSEM Read lock register" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "RLR23,HSEM Read lock register" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "RLR24,HSEM Read lock register" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "RLR25,HSEM Read lock register" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "RLR26,HSEM Read lock register" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "RLR27,HSEM Read lock register" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "RLR28,HSEM Read lock register" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "RLR29,HSEM Read lock register" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "RLR30,HSEM Read lock register" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "RLR31,HSEM Read lock register" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" group.long 0x100++0x3 line.long 0x0 "IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x100++0x3 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "HSEM_C1ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "HSEM_C1ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "HSEM_C1MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" endif sif (cpuis("STM32H742*")) group.long 0x100++0x3 line.long 0x0 "HSEM_IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "HSEM_ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "HSEM_ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "HSEM_MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" endif sif (cpuis("STM32H743*")) group.long 0x100++0x3 line.long 0x0 "HSEM_IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "HSEM_ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "HSEM_ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "HSEM_MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" endif sif (cpuis("STM32H745??-CM4")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H745??-CM7")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H747??-CM4")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H747??-CM7")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H750*")) group.long 0x100++0x3 line.long 0x0 "HSEM_IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "HSEM_ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "HSEM_ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "HSEM_MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" endif sif (cpuis("STM32H753*")) group.long 0x100++0x3 line.long 0x0 "HSEM_IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "HSEM_ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "HSEM_ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "HSEM_MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H755??-CM7")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H757??-CM4")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H757??-CM7")) group.long 0x100++0x7 line.long 0x0 "HSEM_C1IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C1ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x108++0x7 line.long 0x0 "HSEM_C1ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C1MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" group.long 0x110++0x7 line.long 0x0 "HSEM_C2IER,HSEM Interrupt enable register" hexmask.long 0x0 0.--31. 1. "ISE,Interrupt semaphore x enable bit" line.long 0x4 "HSEM_C2ICR,HSEM Interrupt clear register" hexmask.long 0x4 0.--31. 1. "ISC,Interrupt semaphore x clear bit" rgroup.long 0x118++0x7 line.long 0x0 "HSEM_C2ISR,HSEM Interrupt status register" hexmask.long 0x0 0.--31. 1. "ISF,Interrupt semaphore x status bit before enable (mask)" line.long 0x4 "HSEM_C2MISR,HSEM Masked interrupt status register" hexmask.long 0x4 0.--31. 1. "MISF,masked interrupt semaphore x status bit after enable (mask)" endif sif (cpuis("STM32H745??-CM4")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H745??-CM7")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H747??-CM4")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H747??-CM7")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H755??-CM4")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H755??-CM7")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H757??-CM4")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H757??-CM7")) wgroup.long 0x140++0x3 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" endif sif (cpuis("STM32H7A3*")) group.long 0x140++0x7 line.long 0x0 "CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,MasterID of semaphores to be" line.long 0x4 "KEYR,HSEM Interrupt clear register" hexmask.long.word 0x4 16.--31. 1. "KEY,Semaphore Clear Key" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x7F line.long 0x0 "HSEM_R0,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "HSEM_R1,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "HSEM_R2,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "HSEM_R3,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "HSEM_R4,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "HSEM_R5,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "HSEM_R6,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "HSEM_R7,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "HSEM_R8,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "HSEM_R9,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "HSEM_R10,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "HSEM_R11,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "HSEM_R12,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "HSEM_R13,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "HSEM_R14,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "HSEM_R15,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "HSEM_R16,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "HSEM_R17,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "HSEM_R18,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "HSEM_R19,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "HSEM_R20,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "HSEM_R21,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "HSEM_R22,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "HSEM_R23,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "HSEM_R24,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "HSEM_R25,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "HSEM_R26,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "HSEM_R27,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "HSEM_R28,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "HSEM_R29,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "HSEM_R30,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "HSEM_R31,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" rgroup.long 0x80++0x7F line.long 0x0 "HSEM_RLR0,HSEM Read lock register" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "HSEM_RLR1,HSEM Read lock register" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "HSEM_RLR2,HSEM Read lock register" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "HSEM_RLR3,HSEM Read lock register" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "HSEM_RLR4,HSEM Read lock register" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "HSEM_RLR5,HSEM Read lock register" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "HSEM_RLR6,HSEM Read lock register" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "HSEM_RLR7,HSEM Read lock register" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "HSEM_RLR8,HSEM Read lock register" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "HSEM_RLR9,HSEM Read lock register" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "HSEM_RLR10,HSEM Read lock register" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "HSEM_RLR11,HSEM Read lock register" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "HSEM_RLR12,HSEM Read lock register" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "HSEM_RLR13,HSEM Read lock register" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "HSEM_RLR14,HSEM Read lock register" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "HSEM_RLR15,HSEM Read lock register" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "HSEM_RLR16,HSEM Read lock register" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "HSEM_RLR17,HSEM Read lock register" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "HSEM_RLR18,HSEM Read lock register" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "HSEM_RLR19,HSEM Read lock register" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "HSEM_RLR20,HSEM Read lock register" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "HSEM_RLR21,HSEM Read lock register" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "HSEM_RLR22,HSEM Read lock register" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "HSEM_RLR23,HSEM Read lock register" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "HSEM_RLR24,HSEM Read lock register" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "HSEM_RLR25,HSEM Read lock register" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "HSEM_RLR26,HSEM Read lock register" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "HSEM_RLR27,HSEM Read lock register" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "HSEM_RLR28,HSEM Read lock register" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "HSEM_RLR29,HSEM Read lock register" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "HSEM_RLR30,HSEM Read lock register" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "HSEM_RLR31,HSEM Read lock register" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" group.long 0x100++0x3 line.long 0x0 "HSEM_IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "HSEM_ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "HSEM_ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "HSEM_MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" group.long 0x140++0x7 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,MasterID of semaphores to be" line.long 0x4 "HSEM_KEYR,HSEM Interrupt clear register" hexmask.long.word 0x4 16.--31. 1. "KEY,Semaphore Clear Key" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x7F line.long 0x0 "HSEM_R0,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "HSEM_R1,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "HSEM_R2,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "HSEM_R3,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "HSEM_R4,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "HSEM_R5,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "HSEM_R6,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "HSEM_R7,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "HSEM_R8,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "HSEM_R9,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "HSEM_R10,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "HSEM_R11,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "HSEM_R12,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "HSEM_R13,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "HSEM_R14,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "HSEM_R15,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "HSEM_R16,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "HSEM_R17,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "HSEM_R18,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "HSEM_R19,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "HSEM_R20,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "HSEM_R21,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "HSEM_R22,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "HSEM_R23,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "HSEM_R24,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "HSEM_R25,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "HSEM_R26,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "HSEM_R27,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "HSEM_R28,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "HSEM_R29,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "HSEM_R30,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "HSEM_R31,HSEM register HSEM_R0 HSEM_R31" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" rgroup.long 0x80++0x7F line.long 0x0 "HSEM_RLR0,HSEM Read lock register" bitfld.long 0x0 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x0 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4 "HSEM_RLR1,HSEM Read lock register" bitfld.long 0x4 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x8 "HSEM_RLR2,HSEM Read lock register" bitfld.long 0x8 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x8 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x8 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0xC "HSEM_RLR3,HSEM Read lock register" bitfld.long 0xC 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0xC 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0xC 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x10 "HSEM_RLR4,HSEM Read lock register" bitfld.long 0x10 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x10 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x10 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x14 "HSEM_RLR5,HSEM Read lock register" bitfld.long 0x14 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x14 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x14 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x18 "HSEM_RLR6,HSEM Read lock register" bitfld.long 0x18 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x18 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x18 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x1C "HSEM_RLR7,HSEM Read lock register" bitfld.long 0x1C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x1C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x1C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x20 "HSEM_RLR8,HSEM Read lock register" bitfld.long 0x20 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x20 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x20 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x24 "HSEM_RLR9,HSEM Read lock register" bitfld.long 0x24 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x24 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x24 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x28 "HSEM_RLR10,HSEM Read lock register" bitfld.long 0x28 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x28 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x28 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x2C "HSEM_RLR11,HSEM Read lock register" bitfld.long 0x2C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x2C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x2C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x30 "HSEM_RLR12,HSEM Read lock register" bitfld.long 0x30 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x30 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x30 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x34 "HSEM_RLR13,HSEM Read lock register" bitfld.long 0x34 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x34 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x34 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x38 "HSEM_RLR14,HSEM Read lock register" bitfld.long 0x38 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x38 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x38 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x3C "HSEM_RLR15,HSEM Read lock register" bitfld.long 0x3C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x3C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x3C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x40 "HSEM_RLR16,HSEM Read lock register" bitfld.long 0x40 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x40 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x40 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x44 "HSEM_RLR17,HSEM Read lock register" bitfld.long 0x44 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x44 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x44 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x48 "HSEM_RLR18,HSEM Read lock register" bitfld.long 0x48 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x48 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x48 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x4C "HSEM_RLR19,HSEM Read lock register" bitfld.long 0x4C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x4C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x4C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x50 "HSEM_RLR20,HSEM Read lock register" bitfld.long 0x50 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x50 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x50 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x54 "HSEM_RLR21,HSEM Read lock register" bitfld.long 0x54 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x54 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x54 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x58 "HSEM_RLR22,HSEM Read lock register" bitfld.long 0x58 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x58 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x58 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x5C "HSEM_RLR23,HSEM Read lock register" bitfld.long 0x5C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x5C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x5C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x60 "HSEM_RLR24,HSEM Read lock register" bitfld.long 0x60 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x60 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x60 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x64 "HSEM_RLR25,HSEM Read lock register" bitfld.long 0x64 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x64 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x64 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x68 "HSEM_RLR26,HSEM Read lock register" bitfld.long 0x68 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x68 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x68 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x6C "HSEM_RLR27,HSEM Read lock register" bitfld.long 0x6C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x6C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x6C 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x70 "HSEM_RLR28,HSEM Read lock register" bitfld.long 0x70 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x70 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x70 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x74 "HSEM_RLR29,HSEM Read lock register" bitfld.long 0x74 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x74 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x74 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x78 "HSEM_RLR30,HSEM Read lock register" bitfld.long 0x78 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x78 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x78 0.--7. 1. "PROCID,Semaphore ProcessID" line.long 0x7C "HSEM_RLR31,HSEM Read lock register" bitfld.long 0x7C 31. "LOCK,Lock indication" "0,1" hexmask.long.byte 0x7C 8.--15. 1. "MASTERID,Semaphore MasterID" newline hexmask.long.byte 0x7C 0.--7. 1. "PROCID,Semaphore ProcessID" group.long 0x100++0x3 line.long 0x0 "HSEM_IER,HSEM Interrupt enable register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n enable" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt semaphore n enable" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt semaphore n enable" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt semaphore n enable" "0,1" rgroup.long 0x104++0xB line.long 0x0 "HSEM_ICR,HSEM Interrupt clear register" bitfld.long 0x0 31. "ISEM31,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 30. "ISEM30,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 29. "ISEM29,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 28. "ISEM28,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 27. "ISEM27,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 26. "ISEM26,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 25. "ISEM25,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 24. "ISEM24,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 23. "ISEM23,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 22. "ISEM22,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 21. "ISEM21,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 20. "ISEM20,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 19. "ISEM19,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 18. "ISEM18,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 17. "ISEM17,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 16. "ISEM16,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 15. "ISEM15,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 14. "ISEM14,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 13. "ISEM13,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 12. "ISEM12,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 11. "ISEM11,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 10. "ISEM10,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 9. "ISEM9,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 8. "ISEM8,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 7. "ISEM7,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 6. "ISEM6,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 5. "ISEM5,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 4. "ISEM4,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 3. "ISEM3,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 2. "ISEM2,Interrupt(N) semaphore n clear" "0,1" newline bitfld.long 0x0 1. "ISEM1,Interrupt(N) semaphore n clear" "0,1" bitfld.long 0x0 0. "ISEM0,Interrupt(N) semaphore n clear" "0,1" line.long 0x4 "HSEM_ISR,HSEM Interrupt status register" bitfld.long 0x4 31. "ISEM31,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 30. "ISEM30,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 29. "ISEM29,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 28. "ISEM28,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 27. "ISEM27,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 26. "ISEM26,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 25. "ISEM25,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 24. "ISEM24,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 23. "ISEM23,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 22. "ISEM22,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 21. "ISEM21,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 20. "ISEM20,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 19. "ISEM19,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 18. "ISEM18,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 17. "ISEM17,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 16. "ISEM16,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 15. "ISEM15,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 14. "ISEM14,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 13. "ISEM13,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 12. "ISEM12,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 11. "ISEM11,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 10. "ISEM10,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 9. "ISEM9,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 8. "ISEM8,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 7. "ISEM7,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 6. "ISEM6,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 5. "ISEM5,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 4. "ISEM4,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 3. "ISEM3,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 2. "ISEM2,Interrupt(N) semaphore n status bit" "0,1" newline bitfld.long 0x4 1. "ISEM1,Interrupt(N) semaphore n status bit" "0,1" bitfld.long 0x4 0. "ISEM0,Interrupt(N) semaphore n status bit" "0,1" line.long 0x8 "HSEM_MISR,HSEM Masked interrupt status" bitfld.long 0x8 31. "ISEM31,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 30. "ISEM30,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 29. "ISEM29,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 28. "ISEM28,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 27. "ISEM27,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 26. "ISEM26,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 25. "ISEM25,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 24. "ISEM24,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 23. "ISEM23,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 22. "ISEM22,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 21. "ISEM21,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 20. "ISEM20,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 19. "ISEM19,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 18. "ISEM18,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 17. "ISEM17,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 16. "ISEM16,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 15. "ISEM15,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 14. "ISEM14,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 13. "ISEM13,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 12. "ISEM12,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 11. "ISEM11,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 10. "ISEM10,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 9. "ISEM9,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 8. "ISEM8,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 7. "ISEM7,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 6. "ISEM6,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 5. "ISEM5,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 4. "ISEM4,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 3. "ISEM3,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 2. "ISEM2,masked interrupt(N) semaphore n status" "0,1" newline bitfld.long 0x8 1. "ISEM1,masked interrupt(N) semaphore n status" "0,1" bitfld.long 0x8 0. "ISEM0,masked interrupt(N) semaphore n status" "0,1" group.long 0x140++0x7 line.long 0x0 "HSEM_CR,HSEM Clear register" hexmask.long.word 0x0 16.--31. 1. "KEY,Semaphore clear Key" hexmask.long.byte 0x0 8.--15. 1. "MASTERID,MasterID of semaphores to be" line.long 0x4 "HSEM_KEYR,HSEM Interrupt clear register" hexmask.long.word 0x4 16.--31. 1. "KEY,Semaphore Clear Key" endif tree.end tree "I2C (Inter-Integrated Circuit Interface)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "I2C1" base ad:0x40005400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif sif (cpuis("STM32H750*")) group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "I2C2" base ad:0x40005800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif sif (cpuis("STM32H750*")) group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "I2C3" base ad:0x40005C00 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif sif (cpuis("STM32H750*")) group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "I2C4" base ad:0x58001C00 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif sif (cpuis("STM32H750*")) group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" newline bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" newline bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" newline bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" newline bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" newline bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" newline bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" newline bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" newline bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" newline bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" newline bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" newline bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" newline bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" newline bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" newline bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" newline hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" newline hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" newline bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" newline hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" newline rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" newline rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" newline rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" newline rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" newline rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" newline rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" newline rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" newline bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" newline bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" newline bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" newline bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "I2C5" base ad:0x40006400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H753*")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H7A3*")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks Note: These bits can" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H7B0*")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif sif (cpuis("STM32H7B3*")) tree "I2C1" base ad:0x40005400 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C2" base ad:0x40005800 group.long 0x0++0x1B line.long 0x0 "CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C3" base ad:0x40005C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end tree "I2C4" base ad:0x58001C00 group.long 0x0++0x1B line.long 0x0 "I2C_CR1,Access: No wait states. except if a write" bitfld.long 0x0 23. "PECEN,PEC enable Note: If the SMBus feature is" "?,?" bitfld.long 0x0 22. "ALERTEN,SMBus alert enable Device mode" "?,?" bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "?,?" bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable Note: If the" "?,?" bitfld.long 0x0 19. "GCEN,General call enable" "0,1" bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable Note: If" "?,?" bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable This bit is" "0,1" bitfld.long 0x0 16. "SBC,Slave byte control This bit is used to" "0,1" bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1" newline bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1" bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF Note: This bit" "0,1" hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter These bits are used" bitfld.long 0x0 7. "ERRIE,Error interrupts enable Note: Any of" "0,1" bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable Note:" "0,1" bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1" bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt" "0,1" bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave" "0,1" bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1" newline bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1" bitfld.long 0x0 0. "PE,Peripheral enable Note: When PE=0 the" "0,1" line.long 0x4 "I2C_CR2,Access: No wait states. except if a write" bitfld.long 0x4 26. "PECBYTE,Packet error checking byte This bit is" "?,?" bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode) This" "0,1" bitfld.long 0x4 24. "RELOAD,NBYTES reload mode This bit is set and" "0,1" hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes The number of bytes to" bitfld.long 0x4 15. "NACK,NACK generation (slave mode) The bit is" "0,1" bitfld.long 0x4 14. "STOP,Stop generation (master mode) The bit is" "0,1" bitfld.long 0x4 13. "START,Start generation This bit is set by" "0,1" bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1" bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0,1" newline bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode) Note:" "0,1" bitfld.long 0x4 9. "SADD9,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 8. "SADD8,Slave address bit 9:8 (master mode) In" "?,?" bitfld.long 0x4 7. "SADD7,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 6. "SADD6,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 5. "SADD5,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 4. "SADD4,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 3. "SADD3,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 2. "SADD2,Slave address bit 7:1 (master mode) In" "?,?" newline bitfld.long 0x4 1. "SADD1,Slave address bit 7:1 (master mode) In" "?,?" bitfld.long 0x4 0. "SADD0,Slave address bit 0 (master mode) In" "0,1" line.long 0x8 "I2C_OAR1,Access: No wait states. except if a write" bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1" bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode Note: This bit" "0,1" hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address 7-bit addressing mode:" line.long 0xC "I2C_OAR2,Access: No wait states. except if a write" bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1" hexmask.long.byte 0xC 8.--11. 1. "OA2MSK,Own Address 2 masks Note: These bits can" hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address bits 7:1 of address" line.long 0x10 "I2C_TIMINGR,Access: No wait states" hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler This field is used to" hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time This field is used to" hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time This field is used to" hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode) This field" hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode) This field" line.long 0x14 "I2C_TIMEOUTR,Access: No wait states. except if a write" bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1" hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B This field is used to" bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1" bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection Note: This" "0,1" hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A This field is used to" line.long 0x18 "I2C_ISR,Access: No wait states" hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode) These" rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode) This" "0,1" rbitfld.long 0x18 15. "BUSY,Bus busy This flag indicates that a" "0,1" rbitfld.long 0x18 13. "ALERT,SMBus alert This flag is set by hardware" "?,?" rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag This flag" "?,?" rbitfld.long 0x18 11. "PECERR,PEC Error in reception This flag is set" "?,?" rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode) This flag" "0,1" rbitfld.long 0x18 9. "ARLO,Arbitration lost This flag is set by" "0,1" rbitfld.long 0x18 8. "BERR,Bus error This flag is set by hardware" "0,1" newline rbitfld.long 0x18 7. "TCR,Transfer Complete Reload This flag is" "0,1" rbitfld.long 0x18 6. "TC,Transfer Complete (master mode) This" "0,1" rbitfld.long 0x18 5. "STOPF,Stop detection flag This flag is set by" "0,1" rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag This flag" "0,1" rbitfld.long 0x18 3. "ADDR,Address matched (slave mode) This bit is" "0,1" rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1" bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1" bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "I2C_ICR,Access: No wait states" bitfld.long 0x0 13. "ALERTCF,Alert flag clear Writing 1 to this bit" "?,?" bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear Writing 1" "?,?" bitfld.long 0x0 11. "PECCF,PEC Error flag clear Writing 1 to this" "?,?" bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear Writing 1 to" "0,1" bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear Writing 1 to" "0,1" bitfld.long 0x0 8. "BERRCF,Bus error flag clear Writing 1 to this" "0,1" bitfld.long 0x0 5. "STOPCF,Stop detection flag clear Writing 1 to" "0,1" bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear Writing 1 to" "0,1" bitfld.long 0x0 3. "ADDRCF,Address matched flag clear Writing 1 to" "0,1" rgroup.long 0x20++0x7 line.long 0x0 "I2C_PECR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register This" line.long 0x4 "I2C_RXDR,Access: No wait states" hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data Data byte received" group.long 0x28++0x3 line.long 0x0 "I2C_TXDR,Access: No wait states" hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data Data byte to be" tree.end endif tree.end tree "IWDG (Independent Watchdog)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H742*")) tree "IWDG" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H743*")) tree "IWDG" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H750*")) tree "IWDG" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H753*")) tree "IWDG" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "IWDG1" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end tree "IWDG2" base ad:0x58004C00 wgroup.long 0x0++0x3 line.long 0x0 "KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H7A3*")) tree "IWDG" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" bitfld.long 0x0 0.--2. "PR,Prescaler divider These bits are write" "?,?,?,?,?,?,6: Register access,?" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H7B0*")) tree "IWDG" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider These bits are write" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif sif (cpuis("STM32H7B3*")) tree "IWDG" base ad:0x58004800 wgroup.long 0x0++0x3 line.long 0x0 "IWDG_KR,Key register" hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)" group.long 0x4++0x7 line.long 0x0 "IWDG_PR,Prescaler register" hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider These bits are write" line.long 0x4 "IWDG_RLR,Reload register" hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value These bits" rgroup.long 0xC++0x3 line.long 0x0 "IWDG_SR,Status register" bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1" bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1" bitfld.long 0x0 0. "PVU,Watchdog prescaler value update This bit" "0,1" group.long 0x10++0x3 line.long 0x0 "IWDG_WINR,Window register" hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value These bits" tree.end endif tree.end sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "JPEG (JPEG Codec)" base ad:0x52003000 sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) wgroup.long 0x0++0x3 line.long 0x0 "CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H750*")) wgroup.long 0x0++0x3 line.long 0x0 "JPEG_CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "JPEG_CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "JPEG_CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "JPEG_CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "JPEG_CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "JPEG_CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "JPEG_SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "JPEG_CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "JPEG_DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "JPEG_DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H753*")) wgroup.long 0x0++0x3 line.long 0x0 "CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H755??-CM4")) wgroup.long 0x0++0x3 line.long 0x0 "CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H755??-CM7")) wgroup.long 0x0++0x3 line.long 0x0 "CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H757??-CM4")) wgroup.long 0x0++0x3 line.long 0x0 "CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H757??-CM7")) wgroup.long 0x0++0x3 line.long 0x0 "CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H7A3*")) wgroup.long 0x0++0x3 line.long 0x0 "CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x0++0x3 line.long 0x0 "JPEG_CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "JPEG_CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "JPEG_CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "JPEG_CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "JPEG_CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "JPEG_CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "JPEG_SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "JPEG_CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "JPEG_DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "JPEG_DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif sif (cpuis("STM32H7B3*")) wgroup.long 0x0++0x3 line.long 0x0 "JPEG_CONFR0,JPEG codec control register" bitfld.long 0x0 0. "START,Start This bit start or stop the" "0,1" group.long 0x4++0x1B line.long 0x0 "JPEG_CONFR1,JPEG codec configuration register" hexmask.long.word 0x0 16.--31. 1. "YSIZE,Y Size This field defines the number of" bitfld.long 0x0 8. "HDR,Header Processing This bit enable the" "0,1" newline bitfld.long 0x0 6.--7. "NS,Number of components for Scan This field" "0,1,2,3" bitfld.long 0x0 4.--5. "COLORSPACE,Color Space This filed defines the" "0,1,2,3" newline bitfld.long 0x0 3. "DE,Decoding Enable This bit selects the" "0,1" bitfld.long 0x0 0.--1. "NF,Number of color components This field" "0,1,2,3" line.long 0x4 "JPEG_CONFR2,JPEG codec configuration register" hexmask.long 0x4 0.--25. 1. "NMCU,Number of MCU For encoding: this field" line.long 0x8 "JPEG_CONFR3,JPEG codec configuration register" hexmask.long.word 0x8 16.--31. 1. "XSIZE,X size This field defines the number of" line.long 0xC "JPEG_CONFRN1,JPEG codec configuration register" hexmask.long.byte 0xC 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0xC 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0xC 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0xC 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0xC 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0xC 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x10 "JPEG_CONFRN2,JPEG codec configuration register" hexmask.long.byte 0x10 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x10 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x10 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x10 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x10 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x10 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x14 "JPEG_CONFRN3,JPEG codec configuration register" hexmask.long.byte 0x14 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x14 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x14 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x14 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x14 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x14 0. "HD,Huffman DC Selects the Huffman table for" "0,1" line.long 0x18 "JPEG_CONFRN4,JPEG codec configuration register" hexmask.long.byte 0x18 12.--15. 1. "HSF,Horizontal Sampling Factor Horizontal" hexmask.long.byte 0x18 8.--11. 1. "VSF,Vertical Sampling Factor Vertical" newline hexmask.long.byte 0x18 4.--7. 1. "NB,Number of Block Number of data units" bitfld.long 0x18 2.--3. "QT,Quantization Table Selects quantization" "0,1,2,3" newline bitfld.long 0x18 1. "HA,Huffman AC Selects the Huffman table for" "0,1" bitfld.long 0x18 0. "HD,Huffman DC Selects the Huffman table for" "0,1" group.long 0x30++0x3 line.long 0x0 "JPEG_CR,JPEG control register" bitfld.long 0x0 14. "OFF,Output FIFO Flush This bit flush the" "0,1" bitfld.long 0x0 13. "IFF,Input FIFO Flush This bit flush the" "0,1" newline bitfld.long 0x0 12. "ODMAEN,Output DMA Enable Enable the DMA request" "0,1" bitfld.long 0x0 11. "IDMAEN,Input DMA Enable Enable the DMA request" "0,1" newline bitfld.long 0x0 6. "HPDIE,Header Parsing Done Interrupt Enable" "0,1" bitfld.long 0x0 5. "EOCIE,End of Conversion Interrupt Enable This" "0,1" newline bitfld.long 0x0 4. "OFNEIE,Output FIFO Not Empty Interrupt Enable" "0,1" bitfld.long 0x0 3. "OFTIE,Output FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 2. "IFNFIE,Input FIFO Not Full Interrupt Enable" "0,1" bitfld.long 0x0 1. "IFTIE,Input FIFO Threshold Interrupt Enable" "0,1" newline bitfld.long 0x0 0. "JCEN,JPEG Core Enable Enable the JPEG codec" "0,1" rgroup.long 0x34++0x3 line.long 0x0 "JPEG_SR,JPEG status register" bitfld.long 0x0 7. "COF,Codec Operation Flag This bit is set" "0,1" bitfld.long 0x0 6. "HPDF,Header Parsing Done Flag This bit is set" "0,1" newline bitfld.long 0x0 5. "EOCF,End of Conversion Flag This bit is set" "0,1" bitfld.long 0x0 4. "OFNEF,Output FIFO Not Empty Flag This bit is" "0,1" newline bitfld.long 0x0 3. "OFTF,Output FIFO Threshold Flag This bit is" "0,1" bitfld.long 0x0 2. "IFNFF,Input FIFO Not Full Flag This bit is set" "0,1" newline bitfld.long 0x0 1. "IFTF,Input FIFO Threshold Flag This bit is" "0,1" group.long 0x38++0x3 line.long 0x0 "JPEG_CFR,JPEG clear flag register" bitfld.long 0x0 6. "CHPDF,Clear Header Parsing Done Flag Writing 1" "0,1" bitfld.long 0x0 5. "CEOCF,Clear End of Conversion Flag Writing 1" "0,1" wgroup.long 0x40++0x3 line.long 0x0 "JPEG_DIR,JPEG data input register" hexmask.long 0x0 0.--31. 1. "DATAIN,Data Input FIFO Input FIFO data" rgroup.long 0x44++0x3 line.long 0x0 "JPEG_DOR,JPEG data output register" hexmask.long 0x0 0.--31. 1. "DATAOUT,Data Output FIFO Output FIFO data" endif tree.end endif tree "LPTIM (Low Power Timer)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif sif (cpuis("STM32H750*")) group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif sif (cpuis("STM32H750*")) group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif sif (cpuis("STM32H750*")) group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "LPTIM4" base ad:0x58002C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif sif (cpuis("STM32H750*")) group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) tree "LPTIM5" base ad:0x58003000 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif sif (cpuis("STM32H750*")) group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" endif tree.end endif sif (cpuis("STM32H753*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM4" base ad:0x58002C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM5" base ad:0x58003000 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM4" base ad:0x58002C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM5" base ad:0x58003000 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM4" base ad:0x58002C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM5" base ad:0x58003000 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM4" base ad:0x58002C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM5" base ad:0x58003000 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM4" base ad:0x58002C00 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM5" base ad:0x58003000 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H7A3*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7" bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H7B0*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" hexmask.long.byte 0x4 13.--16. 1. "TRIGSEL,Trigger selector" hexmask.long.byte 0x4 9.--12. 1. "PRESC,Clock prescaler" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" hexmask.long.byte 0x4 13.--16. 1. "TRIGSEL,Trigger selector" hexmask.long.byte 0x4 9.--12. 1. "PRESC,Clock prescaler" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" hexmask.long.byte 0x4 13.--16. 1. "TRIGSEL,Trigger selector" hexmask.long.byte 0x4 9.--12. 1. "PRESC,Clock prescaler" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif sif (cpuis("STM32H7B3*")) tree "LPTIM1" base ad:0x40002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" hexmask.long.byte 0x4 13.--16. 1. "TRIGSEL,Trigger selector" hexmask.long.byte 0x4 9.--12. 1. "PRESC,Clock prescaler" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM2" base ad:0x58002400 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" hexmask.long.byte 0x4 13.--16. 1. "TRIGSEL,Trigger selector" hexmask.long.byte 0x4 9.--12. 1. "PRESC,Clock prescaler" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 4.--5. "IN2SEL,LPTIM Input 2 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end tree "LPTIM3" base ad:0x58002800 rgroup.long 0x0++0x3 line.long 0x0 "ISR,Interrupt and Status Register" bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1" bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1" bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1" bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1" bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1" bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1" bitfld.long 0x0 0. "CMPM,Compare match" "0,1" wgroup.long 0x4++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1" bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1" bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1" bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1" bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1" bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1" bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1" group.long 0x8++0x13 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1" bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1" bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1" bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1" bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1" bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1" bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1" line.long 0x4 "CFGR,Configuration Register" bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1" bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1" bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1" bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1" bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1" bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1" bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3" hexmask.long.byte 0x4 13.--16. 1. "TRIGSEL,Trigger selector" hexmask.long.byte 0x4 9.--12. 1. "PRESC,Clock prescaler" bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3" newline bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3" bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3" bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1" line.long 0x8 "CR,Control Register" bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1" bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1" bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1" bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1" bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1" line.long 0xC "CMP,Compare Register" hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value" line.long 0x10 "ARR,Autoreload Register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value" rgroup.long 0x1C++0x3 line.long 0x0 "CNT,Counter Register" hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value" group.long 0x24++0x3 line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2" bitfld.long 0x0 0.--1. "IN1SEL,LPTIM Input 1 selection" "0,1,2,3" tree.end endif tree.end tree "LPUART (Low-power Universal Asynchronous Receiver Transmitter)" base ad:0x58000C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion" hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" newline bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" newline bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" newline bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" bitfld.long 0x0 18. "SBKF,SBKF" "0,1" newline bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" newline bitfld.long 0x0 2. "NE,NE" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,Prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "LTDC (LCD-TFT Controller)" base ad:0x50001000 group.long 0x8++0x13 line.long 0x0 "SSCR,Synchronization Size Configuration" hexmask.long.word 0x0 16.--25. 1. "HSW,Horizontal Synchronization Width (in" hexmask.long.word 0x0 0.--10. 1. "VSH,Vertical Synchronization Height (in" line.long 0x4 "BPCR,Back Porch Configuration" hexmask.long.word 0x4 16.--27. 1. "AHBP,Accumulated Horizontal back porch (in" hexmask.long.word 0x4 0.--10. 1. "AVBP,Accumulated Vertical back porch (in" line.long 0x8 "AWCR,Active Width Configuration" hexmask.long.word 0x8 16.--27. 1. "AAV,AAV" hexmask.long.word 0x8 0.--10. 1. "AAH,Accumulated Active Height (in units of" line.long 0xC "TWCR,Total Width Configuration" hexmask.long.word 0xC 16.--27. 1. "TOTALW,Total Width (in units of pixel clock" hexmask.long.word 0xC 0.--10. 1. "TOTALH,Total Height (in units of horizontal" line.long 0x10 "GCR,Global Control Register" bitfld.long 0x10 31. "HSPOL,Horizontal Synchronization" "0,1" bitfld.long 0x10 30. "VSPOL,Vertical Synchronization" "0,1" bitfld.long 0x10 29. "DEPOL,Data Enable Polarity" "0,1" bitfld.long 0x10 28. "PCPOL,Pixel Clock Polarity" "0,1" bitfld.long 0x10 16. "DEN,Dither Enable" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x10 12.--15. 1. "DRW,Dither Red Width" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x10 12.--15. 1. "DRW,Dither Red Width" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) rbitfld.long 0x10 12.--14. "DRW,Dither Red Width" "0,1,2,3,4,5,6,7" rbitfld.long 0x10 8.--10. "DGW,Dither Green Width" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 4.--6. "DBW,Dither Blue Width" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x10 8.--11. 1. "DGW,Dither Green Width" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x10 8.--11. 1. "DGW,Dither Green Width" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x10 4.--7. 1. "DBW,Dither Blue Width" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x10 4.--7. 1. "DBW,Dither Blue Width" endif bitfld.long 0x10 0. "LTDCEN,LCD-TFT controller enable" "0,1" group.long 0x24++0x3 line.long 0x0 "SRCR,Shadow Reload Configuration" bitfld.long 0x0 1. "VBR,Vertical Blanking Reload" "0,1" bitfld.long 0x0 0. "IMR,Immediate Reload" "0,1" group.long 0x2C++0x3 line.long 0x0 "BCCR,Background Color Configuration" hexmask.long.byte 0x0 16.--23. 1. "BCRED,Background Color Red value" hexmask.long.byte 0x0 8.--15. 1. "BCGREEN,Background Color Green" hexmask.long.byte 0x0 0.--7. 1. "BCBLUE,Background Color Blue" group.long 0x34++0x3 line.long 0x0 "IER,Interrupt Enable Register" bitfld.long 0x0 3. "RRIE,Register Reload interrupt" "0,1" bitfld.long 0x0 2. "TERRIE,Transfer Error Interrupt" "0,1" bitfld.long 0x0 1. "FUIE,FIFO Underrun Interrupt" "0,1" bitfld.long 0x0 0. "LIE,Line Interrupt Enable" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "ISR,Interrupt Status Register" bitfld.long 0x0 3. "RRIF,Register Reload Interrupt" "0,1" bitfld.long 0x0 2. "TERRIF,Transfer Error interrupt" "0,1" bitfld.long 0x0 1. "FUIF,FIFO Underrun Interrupt" "0,1" bitfld.long 0x0 0. "LIF,Line Interrupt flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "ICR,Interrupt Clear Register" bitfld.long 0x0 3. "CRRIF,Clears Register Reload Interrupt" "0,1" bitfld.long 0x0 2. "CTERRIF,Clears the Transfer Error Interrupt" "0,1" bitfld.long 0x0 1. "CFUIF,Clears the FIFO Underrun Interrupt" "0,1" bitfld.long 0x0 0. "CLIF,Clears the Line Interrupt" "0,1" group.long 0x40++0x3 line.long 0x0 "LIPCR,Line Interrupt Position Configuration" hexmask.long.word 0x0 0.--10. 1. "LIPOS,Line Interrupt Position" rgroup.long 0x44++0x7 line.long 0x0 "CPSR,Current Position Status" hexmask.long.word 0x0 16.--31. 1. "CXPOS,Current X Position" hexmask.long.word 0x0 0.--15. 1. "CYPOS,Current Y Position" line.long 0x4 "CDSR,Current Display Status" bitfld.long 0x4 3. "HSYNCS,Horizontal Synchronization display" "0,1" bitfld.long 0x4 2. "VSYNCS,Vertical Synchronization display" "0,1" bitfld.long 0x4 1. "HDES,Horizontal Data Enable display" "0,1" bitfld.long 0x4 0. "VDES,Vertical Data Enable display" "0,1" group.long 0x84++0x1F line.long 0x0 "L1CR,Layerx Control Register" bitfld.long 0x0 4. "CLUTEN,Color Look-Up Table Enable" "0,1" bitfld.long 0x0 1. "COLKEN,Color Keying Enable" "0,1" bitfld.long 0x0 0. "LEN,Layer Enable" "0,1" line.long 0x4 "L1WHPCR,Layerx Window Horizontal Position" hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,Window Horizontal Stop" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,Window Horizontal Start" line.long 0x8 "L1WVPCR,Layerx Window Vertical Position" hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,Window Vertical Stop" hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,Window Vertical Start" line.long 0xC "L1CKCR,Layerx Color Keying Configuration" hexmask.long.byte 0xC 16.--23. 1. "CKRED,Color Key Red value" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,Color Key Green value" hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,Color Key Blue value" line.long 0x10 "L1PFCR,Layerx Pixel Format Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x10 0.--2. "PF,Pixel Format" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x10 0.--3. 1. "PF,Pixel Format" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x10 0.--3. 1. "PF,Pixel Format" endif line.long 0x14 "L1CACR,Layerx Constant Alpha Configuration" hexmask.long.byte 0x14 0.--7. 1. "CONSTA,Constant Alpha" line.long 0x18 "L1DCCR,Layerx Default Color Configuration" hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,Default Color Alpha" hexmask.long.byte 0x18 16.--23. 1. "DCRED,Default Color Red" hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,Default Color Green" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,Default Color Blue" line.long 0x1C "L1BFCR,Layerx Blending Factors Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x1C 8.--10. "BF1,Blending Factor 1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,Blending Factor 2" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x1C 8.--11. 1. "BF1,Blending Factor 1" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x1C 8.--11. 1. "BF1,Blending Factor 1" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x1C 0.--3. 1. "BF2,Blending Factor 2" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x1C 0.--3. 1. "BF2,Blending Factor 2" endif group.long 0xAC++0xB line.long 0x0 "L1CFBAR,Layerx Color Frame Buffer Address" hexmask.long 0x0 0.--31. 1. "CFBADD,Color Frame Buffer Start" line.long 0x4 "L1CFBLR,Layerx Color Frame Buffer Length" hexmask.long.word 0x4 16.--28. 1. "CFBP,Color Frame Buffer Pitch in" hexmask.long.word 0x4 0.--12. 1. "CFBLL,Color Frame Buffer Line" line.long 0x8 "L1CFBLNR,Layerx ColorFrame Buffer Line Number" hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,Frame Buffer Line Number" wgroup.long 0xC4++0x3 line.long 0x0 "L1CLUTWR,Layerx CLUT Write Register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT Address" hexmask.long.byte 0x0 16.--23. 1. "RED,Red value" hexmask.long.byte 0x0 8.--15. 1. "GREEN,Green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,Blue value" group.long 0x104++0x1F line.long 0x0 "L2CR,Layerx Control Register" bitfld.long 0x0 4. "CLUTEN,Color Look-Up Table Enable" "0,1" bitfld.long 0x0 1. "COLKEN,Color Keying Enable" "0,1" bitfld.long 0x0 0. "LEN,Layer Enable" "0,1" line.long 0x4 "L2WHPCR,Layerx Window Horizontal Position" hexmask.long.word 0x4 16.--27. 1. "WHSPPOS,Window Horizontal Stop" hexmask.long.word 0x4 0.--11. 1. "WHSTPOS,Window Horizontal Start" line.long 0x8 "L2WVPCR,Layerx Window Vertical Position" hexmask.long.word 0x8 16.--26. 1. "WVSPPOS,Window Vertical Stop" hexmask.long.word 0x8 0.--10. 1. "WVSTPOS,Window Vertical Start" line.long 0xC "L2CKCR,Layerx Color Keying Configuration" hexmask.long.byte 0xC 16.--23. 1. "CKRED,Color Key Red value" hexmask.long.byte 0xC 8.--15. 1. "CKGREEN,Color Key Green value" hexmask.long.byte 0xC 0.--7. 1. "CKBLUE,Color Key Blue value" line.long 0x10 "L2PFCR,Layerx Pixel Format Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x10 0.--2. "PF,Pixel Format" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x10 0.--3. 1. "PF,Pixel Format" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x10 0.--3. 1. "PF,Pixel Format" endif line.long 0x14 "L2CACR,Layerx Constant Alpha Configuration" hexmask.long.byte 0x14 0.--7. 1. "CONSTA,Constant Alpha" line.long 0x18 "L2DCCR,Layerx Default Color Configuration" hexmask.long.byte 0x18 24.--31. 1. "DCALPHA,Default Color Alpha" hexmask.long.byte 0x18 16.--23. 1. "DCRED,Default Color Red" hexmask.long.byte 0x18 8.--15. 1. "DCGREEN,Default Color Green" hexmask.long.byte 0x18 0.--7. 1. "DCBLUE,Default Color Blue" line.long 0x1C "L2BFCR,Layerx Blending Factors Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x1C 8.--10. "BF1,Blending Factor 1" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0.--2. "BF2,Blending Factor 2" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x1C 8.--11. 1. "BF1,Blending Factor 1" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x1C 8.--11. 1. "BF1,Blending Factor 1" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x1C 0.--3. 1. "BF2,Blending Factor 2" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x1C 0.--3. 1. "BF2,Blending Factor 2" endif group.long 0x12C++0xB line.long 0x0 "L2CFBAR,Layerx Color Frame Buffer Address" hexmask.long 0x0 0.--31. 1. "CFBADD,Color Frame Buffer Start" line.long 0x4 "L2CFBLR,Layerx Color Frame Buffer Length" hexmask.long.word 0x4 16.--28. 1. "CFBP,Color Frame Buffer Pitch in" hexmask.long.word 0x4 0.--12. 1. "CFBLL,Color Frame Buffer Line" line.long 0x8 "L2CFBLNR,Layerx ColorFrame Buffer Line Number" hexmask.long.word 0x8 0.--10. 1. "CFBLNBR,Frame Buffer Line Number" wgroup.long 0x144++0x3 line.long 0x0 "L2CLUTWR,Layerx CLUT Write Register" hexmask.long.byte 0x0 24.--31. 1. "CLUTADD,CLUT Address" hexmask.long.byte 0x0 16.--23. 1. "RED,Red value" hexmask.long.byte 0x0 8.--15. 1. "GREEN,Green value" hexmask.long.byte 0x0 0.--7. 1. "BLUE,Blue value" tree.end tree "MDIOS (Management Data Input/Output Slave)" base ad:0x40009400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H742*")) group.long 0x0++0x3 line.long 0x0 "CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H743*")) group.long 0x0++0x3 line.long 0x0 "CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H745??-CM4")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H745??-CM7")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H747??-CM4")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H747??-CM7")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H750*")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H753*")) group.long 0x0++0x3 line.long 0x0 "CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x3 line.long 0x0 "MDIOS_CR,MDIOS configuration register" hexmask.long.byte 0x0 8.--12. 1. "PORT_ADDRESS,Slaves's address" bitfld.long 0x0 7. "DPC,Disable Preamble Check" "0,1" newline bitfld.long 0x0 3. "EIE,Error interrupt enable" "0,1" bitfld.long 0x0 2. "RDIE,Register Read Interrupt" "0,1" newline bitfld.long 0x0 1. "WRIE,Register write interrupt" "0,1" bitfld.long 0x0 0. "EN,Peripheral enable" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "MDIOS_WRFR,MDIOS write flag register" hexmask.long 0x0 0.--31. 1. "WRF,Write flags for MDIO registers 0 to" group.long 0x8++0x3 line.long 0x0 "MDIOS_CWRFR,MDIOS clear write flag" hexmask.long 0x0 0.--31. 1. "CWRF,Clear the write flag" rgroup.long 0xC++0x3 line.long 0x0 "MDIOS_RDFR,MDIOS read flag register" hexmask.long 0x0 0.--31. 1. "RDF,Read flags for MDIO registers 0 to" group.long 0x10++0x3 line.long 0x0 "MDIOS_CRDFR,MDIOS clear read flag register" hexmask.long 0x0 0.--31. 1. "CRDF,Clear the read flag" rgroup.long 0x14++0x3 line.long 0x0 "MDIOS_SR,MDIOS status register" bitfld.long 0x0 2. "TERF,Turnaround error flag" "0,1" bitfld.long 0x0 1. "SERF,Start error flag" "0,1" newline bitfld.long 0x0 0. "PERF,Preamble error flag" "0,1" group.long 0x18++0x3 line.long 0x0 "MDIOS_CLRFR,MDIOS clear flag register" bitfld.long 0x0 2. "CTERF,Clear the turnaround error" "0,1" bitfld.long 0x0 1. "CSERF,Clear the start error flag" "0,1" newline bitfld.long 0x0 0. "CPERF,Clear the preamble error" "0,1" rgroup.long 0x1C++0x7F line.long 0x0 "MDIOS_DINR0,MDIOS input data register 0" hexmask.long.word 0x0 0.--15. 1. "DIN0,Input data received from MDIO Master" line.long 0x4 "MDIOS_DINR1,MDIOS input data register 1" hexmask.long.word 0x4 0.--15. 1. "DIN1,Input data received from MDIO Master" line.long 0x8 "MDIOS_DINR2,MDIOS input data register 2" hexmask.long.word 0x8 0.--15. 1. "DIN2,Input data received from MDIO Master" line.long 0xC "MDIOS_DINR3,MDIOS input data register 3" hexmask.long.word 0xC 0.--15. 1. "DIN3,Input data received from MDIO Master" line.long 0x10 "MDIOS_DINR4,MDIOS input data register 4" hexmask.long.word 0x10 0.--15. 1. "DIN4,Input data received from MDIO Master" line.long 0x14 "MDIOS_DINR5,MDIOS input data register 5" hexmask.long.word 0x14 0.--15. 1. "DIN5,Input data received from MDIO Master" line.long 0x18 "MDIOS_DINR6,MDIOS input data register 6" hexmask.long.word 0x18 0.--15. 1. "DIN6,Input data received from MDIO Master" line.long 0x1C "MDIOS_DINR7,MDIOS input data register 7" hexmask.long.word 0x1C 0.--15. 1. "DIN7,Input data received from MDIO Master" line.long 0x20 "MDIOS_DINR8,MDIOS input data register 8" hexmask.long.word 0x20 0.--15. 1. "DIN8,Input data received from MDIO Master" line.long 0x24 "MDIOS_DINR9,MDIOS input data register 9" hexmask.long.word 0x24 0.--15. 1. "DIN9,Input data received from MDIO Master" line.long 0x28 "MDIOS_DINR10,MDIOS input data register 10" hexmask.long.word 0x28 0.--15. 1. "DIN10,Input data received from MDIO Master" line.long 0x2C "MDIOS_DINR11,MDIOS input data register 11" hexmask.long.word 0x2C 0.--15. 1. "DIN11,Input data received from MDIO Master" line.long 0x30 "MDIOS_DINR12,MDIOS input data register 12" hexmask.long.word 0x30 0.--15. 1. "DIN12,Input data received from MDIO Master" line.long 0x34 "MDIOS_DINR13,MDIOS input data register 13" hexmask.long.word 0x34 0.--15. 1. "DIN13,Input data received from MDIO Master" line.long 0x38 "MDIOS_DINR14,MDIOS input data register 14" hexmask.long.word 0x38 0.--15. 1. "DIN14,Input data received from MDIO Master" line.long 0x3C "MDIOS_DINR15,MDIOS input data register 15" hexmask.long.word 0x3C 0.--15. 1. "DIN15,Input data received from MDIO Master" line.long 0x40 "MDIOS_DINR16,MDIOS input data register 16" hexmask.long.word 0x40 0.--15. 1. "DIN16,Input data received from MDIO Master" line.long 0x44 "MDIOS_DINR17,MDIOS input data register 17" hexmask.long.word 0x44 0.--15. 1. "DIN17,Input data received from MDIO Master" line.long 0x48 "MDIOS_DINR18,MDIOS input data register 18" hexmask.long.word 0x48 0.--15. 1. "DIN18,Input data received from MDIO Master" line.long 0x4C "MDIOS_DINR19,MDIOS input data register 19" hexmask.long.word 0x4C 0.--15. 1. "DIN19,Input data received from MDIO Master" line.long 0x50 "MDIOS_DINR20,MDIOS input data register 20" hexmask.long.word 0x50 0.--15. 1. "DIN20,Input data received from MDIO Master" line.long 0x54 "MDIOS_DINR21,MDIOS input data register 21" hexmask.long.word 0x54 0.--15. 1. "DIN21,Input data received from MDIO Master" line.long 0x58 "MDIOS_DINR22,MDIOS input data register 22" hexmask.long.word 0x58 0.--15. 1. "DIN22,Input data received from MDIO Master" line.long 0x5C "MDIOS_DINR23,MDIOS input data register 23" hexmask.long.word 0x5C 0.--15. 1. "DIN23,Input data received from MDIO Master" line.long 0x60 "MDIOS_DINR24,MDIOS input data register 24" hexmask.long.word 0x60 0.--15. 1. "DIN24,Input data received from MDIO Master" line.long 0x64 "MDIOS_DINR25,MDIOS input data register 25" hexmask.long.word 0x64 0.--15. 1. "DIN25,Input data received from MDIO Master" line.long 0x68 "MDIOS_DINR26,MDIOS input data register 26" hexmask.long.word 0x68 0.--15. 1. "DIN26,Input data received from MDIO Master" line.long 0x6C "MDIOS_DINR27,MDIOS input data register 27" hexmask.long.word 0x6C 0.--15. 1. "DIN27,Input data received from MDIO Master" line.long 0x70 "MDIOS_DINR28,MDIOS input data register 28" hexmask.long.word 0x70 0.--15. 1. "DIN28,Input data received from MDIO Master" line.long 0x74 "MDIOS_DINR29,MDIOS input data register 29" hexmask.long.word 0x74 0.--15. 1. "DIN29,Input data received from MDIO Master" line.long 0x78 "MDIOS_DINR30,MDIOS input data register 30" hexmask.long.word 0x78 0.--15. 1. "DIN30,Input data received from MDIO Master" line.long 0x7C "MDIOS_DINR31,MDIOS input data register 31" hexmask.long.word 0x7C 0.--15. 1. "DIN31,Input data received from MDIO Master" group.long 0x9C++0x7F line.long 0x0 "MDIOS_DOUTR0,MDIOS output data register 0" hexmask.long.word 0x0 0.--15. 1. "DOUT0,Output data sent to MDIO Master during" line.long 0x4 "MDIOS_DOUTR1,MDIOS output data register 1" hexmask.long.word 0x4 0.--15. 1. "DOUT1,Output data sent to MDIO Master during" line.long 0x8 "MDIOS_DOUTR2,MDIOS output data register 2" hexmask.long.word 0x8 0.--15. 1. "DOUT2,Output data sent to MDIO Master during" line.long 0xC "MDIOS_DOUTR3,MDIOS output data register 3" hexmask.long.word 0xC 0.--15. 1. "DOUT3,Output data sent to MDIO Master during" line.long 0x10 "MDIOS_DOUTR4,MDIOS output data register 4" hexmask.long.word 0x10 0.--15. 1. "DOUT4,Output data sent to MDIO Master during" line.long 0x14 "MDIOS_DOUTR5,MDIOS output data register 5" hexmask.long.word 0x14 0.--15. 1. "DOUT5,Output data sent to MDIO Master during" line.long 0x18 "MDIOS_DOUTR6,MDIOS output data register 6" hexmask.long.word 0x18 0.--15. 1. "DOUT6,Output data sent to MDIO Master during" line.long 0x1C "MDIOS_DOUTR7,MDIOS output data register 7" hexmask.long.word 0x1C 0.--15. 1. "DOUT7,Output data sent to MDIO Master during" line.long 0x20 "MDIOS_DOUTR8,MDIOS output data register 8" hexmask.long.word 0x20 0.--15. 1. "DOUT8,Output data sent to MDIO Master during" line.long 0x24 "MDIOS_DOUTR9,MDIOS output data register 9" hexmask.long.word 0x24 0.--15. 1. "DOUT9,Output data sent to MDIO Master during" line.long 0x28 "MDIOS_DOUTR10,MDIOS output data register 10" hexmask.long.word 0x28 0.--15. 1. "DOUT10,Output data sent to MDIO Master during" line.long 0x2C "MDIOS_DOUTR11,MDIOS output data register 11" hexmask.long.word 0x2C 0.--15. 1. "DOUT11,Output data sent to MDIO Master during" line.long 0x30 "MDIOS_DOUTR12,MDIOS output data register 12" hexmask.long.word 0x30 0.--15. 1. "DOUT12,Output data sent to MDIO Master during" line.long 0x34 "MDIOS_DOUTR13,MDIOS output data register 13" hexmask.long.word 0x34 0.--15. 1. "DOUT13,Output data sent to MDIO Master during" line.long 0x38 "MDIOS_DOUTR14,MDIOS output data register 14" hexmask.long.word 0x38 0.--15. 1. "DOUT14,Output data sent to MDIO Master during" line.long 0x3C "MDIOS_DOUTR15,MDIOS output data register 15" hexmask.long.word 0x3C 0.--15. 1. "DOUT15,Output data sent to MDIO Master during" line.long 0x40 "MDIOS_DOUTR16,MDIOS output data register 16" hexmask.long.word 0x40 0.--15. 1. "DOUT16,Output data sent to MDIO Master during" line.long 0x44 "MDIOS_DOUTR17,MDIOS output data register 17" hexmask.long.word 0x44 0.--15. 1. "DOUT17,Output data sent to MDIO Master during" line.long 0x48 "MDIOS_DOUTR18,MDIOS output data register 18" hexmask.long.word 0x48 0.--15. 1. "DOUT18,Output data sent to MDIO Master during" line.long 0x4C "MDIOS_DOUTR19,MDIOS output data register 19" hexmask.long.word 0x4C 0.--15. 1. "DOUT19,Output data sent to MDIO Master during" line.long 0x50 "MDIOS_DOUTR20,MDIOS output data register 20" hexmask.long.word 0x50 0.--15. 1. "DOUT20,Output data sent to MDIO Master during" line.long 0x54 "MDIOS_DOUTR21,MDIOS output data register 21" hexmask.long.word 0x54 0.--15. 1. "DOUT21,Output data sent to MDIO Master during" line.long 0x58 "MDIOS_DOUTR22,MDIOS output data register 22" hexmask.long.word 0x58 0.--15. 1. "DOUT22,Output data sent to MDIO Master during" line.long 0x5C "MDIOS_DOUTR23,MDIOS output data register 23" hexmask.long.word 0x5C 0.--15. 1. "DOUT23,Output data sent to MDIO Master during" line.long 0x60 "MDIOS_DOUTR24,MDIOS output data register 24" hexmask.long.word 0x60 0.--15. 1. "DOUT24,Output data sent to MDIO Master during" line.long 0x64 "MDIOS_DOUTR25,MDIOS output data register 25" hexmask.long.word 0x64 0.--15. 1. "DOUT25,Output data sent to MDIO Master during" line.long 0x68 "MDIOS_DOUTR26,MDIOS output data register 26" hexmask.long.word 0x68 0.--15. 1. "DOUT26,Output data sent to MDIO Master during" line.long 0x6C "MDIOS_DOUTR27,MDIOS output data register 27" hexmask.long.word 0x6C 0.--15. 1. "DOUT27,Output data sent to MDIO Master during" line.long 0x70 "MDIOS_DOUTR28,MDIOS output data register 28" hexmask.long.word 0x70 0.--15. 1. "DOUT28,Output data sent to MDIO Master during" line.long 0x74 "MDIOS_DOUTR29,MDIOS output data register 29" hexmask.long.word 0x74 0.--15. 1. "DOUT29,Output data sent to MDIO Master during" line.long 0x78 "MDIOS_DOUTR30,MDIOS output data register 30" hexmask.long.word 0x78 0.--15. 1. "DOUT30,Output data sent to MDIO Master during" line.long 0x7C "MDIOS_DOUTR31,MDIOS output data register 31" hexmask.long.word 0x7C 0.--15. 1. "DOUT31,Output data sent to MDIO Master during" endif tree.end tree "MDMA (Master Direct Memory Access)" base ad:0x52000000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) rgroup.long 0x0++0x3 line.long 0x0 "MDMA_GISR0,MDMA Global Interrupt/Status" bitfld.long 0x0 15. "GIF15,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 14. "GIF14,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 13. "GIF13,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 12. "GIF12,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 11. "GIF11,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 10. "GIF10,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 9. "GIF9,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 8. "GIF8,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 7. "GIF7,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 6. "GIF6,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 5. "GIF5,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 4. "GIF4,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 3. "GIF3,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 2. "GIF2,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 1. "GIF1,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 0. "GIF0,Channel x global interrupt flag (x=...)" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MDMA_C0ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA0,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF0,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF0,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF0,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF0,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF0,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x44++0x3 line.long 0x0 "MDMA_C0IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF0,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF0,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF0,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF0,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF0,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "MDMA_C0ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x4C++0x1F line.long 0x0 "MDMA_C0CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C0TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C0BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C0SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C0DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C0BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C0LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C0TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x70++0x7 line.long 0x0 "MDMA_C0MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C0MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x80++0x3 line.long 0x0 "MDMA_C1ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA1,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF1,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF1,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF1,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF1,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x84++0x3 line.long 0x0 "MDMA_C1IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF1,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF1,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF1,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF1,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF1,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x88++0x3 line.long 0x0 "MDMA_C1ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x8C++0x1F line.long 0x0 "MDMA_C1CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C1TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C1BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C1SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C1DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C1BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C1LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C1TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xB0++0x7 line.long 0x0 "MDMA_C1MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C1MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0xC0++0x3 line.long 0x0 "MDMA_C2ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA2,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF2,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF2,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF2,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF2,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF2,Channel x transfer error interrupt flag" "0,1" wgroup.long 0xC4++0x3 line.long 0x0 "MDMA_C2IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF2,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF2,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF2,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF2,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF2,Channel x clear transfer error interrupt" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "MDMA_C2ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0xCC++0x1F line.long 0x0 "MDMA_C2CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C2TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C2BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C2SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C2DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C2BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C2LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C2TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xF0++0x7 line.long 0x0 "MDMA_C2MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C2MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x100++0x3 line.long 0x0 "MDMA_C3ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA3,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF3,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF3,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF3,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF3,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF3,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x104++0x3 line.long 0x0 "MDMA_C3IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF3,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF3,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF3,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF3,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF3,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "MDMA_C3ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x10C++0x1F line.long 0x0 "MDMA_C3CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C3TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C3BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C3SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C3DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C3BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C3LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C3TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x130++0x7 line.long 0x0 "MDMA_C3MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C3MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x140++0x3 line.long 0x0 "MDMA_C4ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA4,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF4,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF4,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF4,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF4,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF4,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "MDMA_C4IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF4,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF4,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF4,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF4,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF4,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "MDMA_C4ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x14C++0x1F line.long 0x0 "MDMA_C4CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C4TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C4BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C4SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C4DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C4BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C4LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C4TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x170++0x7 line.long 0x0 "MDMA_C4MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C4MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x180++0x3 line.long 0x0 "MDMA_C5ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA5,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF5,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF5,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF5,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF5,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF5,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x184++0x3 line.long 0x0 "MDMA_C5IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF5,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF5,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF5,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF5,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF5,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "MDMA_C5ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x18C++0x1F line.long 0x0 "MDMA_C5CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C5TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C5BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C5SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C5DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C5BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C5LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C5TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1B0++0x7 line.long 0x0 "MDMA_C5MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C5MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x1C0++0x3 line.long 0x0 "MDMA_C6ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA6,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF6,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF6,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF6,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF6,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF6,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x1C4++0x3 line.long 0x0 "MDMA_C6IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF6,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF6,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF6,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF6,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF6,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x1C8++0x3 line.long 0x0 "MDMA_C6ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x1CC++0x1F line.long 0x0 "MDMA_C6CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C6TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C6BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C6SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C6DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C6BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C6LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C6TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1F0++0x7 line.long 0x0 "MDMA_C6MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C6MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x200++0x3 line.long 0x0 "MDMA_C7ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA7,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF7,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF7,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF7,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF7,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF7,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x204++0x3 line.long 0x0 "MDMA_C7IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF7,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF7,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF7,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF7,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF7,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "MDMA_C7ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x20C++0x1F line.long 0x0 "MDMA_C7CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C7TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C7BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C7SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C7DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C7BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C7LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C7TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x230++0x7 line.long 0x0 "MDMA_C7MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C7MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x240++0x3 line.long 0x0 "MDMA_C8ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA8,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF8,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF8,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF8,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF8,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF8,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x244++0x3 line.long 0x0 "MDMA_C8IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF8,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF8,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF8,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF8,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF8,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "MDMA_C8ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x24C++0x1F line.long 0x0 "MDMA_C8CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C8TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C8BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C8SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C8DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C8BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C8LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C8TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x270++0x7 line.long 0x0 "MDMA_C8MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C8MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x280++0x3 line.long 0x0 "MDMA_C9ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA9,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF9,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF9,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF9,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF9,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF9,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x284++0x3 line.long 0x0 "MDMA_C9IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF9,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF9,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF9,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF9,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF9,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "MDMA_C9ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x28C++0x1F line.long 0x0 "MDMA_C9CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C9TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C9BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C9SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C9DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C9BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C9LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C9TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2B0++0x7 line.long 0x0 "MDMA_C9MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C9MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x2C0++0x3 line.long 0x0 "MDMA_C10ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA10,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF10,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF10,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF10,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF10,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF10,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x2C4++0x3 line.long 0x0 "MDMA_C10IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF10,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF10,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF10,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF10,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF10,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x2C8++0x3 line.long 0x0 "MDMA_C10ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x2CC++0x1F line.long 0x0 "MDMA_C10CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C10TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C10BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C10SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C10DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C10BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C10LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C10TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2F0++0x7 line.long 0x0 "MDMA_C10MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C10MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x300++0x3 line.long 0x0 "MDMA_C11ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA11,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF11,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF11,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF11,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF11,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF11,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x304++0x3 line.long 0x0 "MDMA_C11IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF11,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF11,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF11,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF11,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF11,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x308++0x3 line.long 0x0 "MDMA_C11ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x30C++0x1F line.long 0x0 "MDMA_C11CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C11TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C11BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C11SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C11DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C11BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C11LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C11TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x330++0x7 line.long 0x0 "MDMA_C11MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C11MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x340++0x3 line.long 0x0 "MDMA_C12ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA12,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF12,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF12,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF12,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF12,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF12,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x344++0x3 line.long 0x0 "MDMA_C12IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF12,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF12,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF12,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF12,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF12,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x348++0x3 line.long 0x0 "MDMA_C12ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x34C++0x1F line.long 0x0 "MDMA_C12CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C12TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C12BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C12SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C12DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C12BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C12LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C12TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x370++0x7 line.long 0x0 "MDMA_C12MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C12MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x380++0x3 line.long 0x0 "MDMA_C13ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA13,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF13,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF13,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF13,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF13,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF13,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x384++0x3 line.long 0x0 "MDMA_C13IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF13,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF13,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF13,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF13,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF13,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x388++0x3 line.long 0x0 "MDMA_C13ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x38C++0x1F line.long 0x0 "MDMA_C13CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C13TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C13BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C13SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C13DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C13BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C13LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C13TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3B0++0x7 line.long 0x0 "MDMA_C13MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C13MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x3C0++0x3 line.long 0x0 "MDMA_C14ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA14,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF14,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF14,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF14,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF14,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF14,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x3C4++0x3 line.long 0x0 "MDMA_C14IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF14,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF14,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF14,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF14,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF14,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x3C8++0x3 line.long 0x0 "MDMA_C14ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x3CC++0x1F line.long 0x0 "MDMA_C14CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C14TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C14BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C14SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C14DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C14BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C14LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C14TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3F0++0x7 line.long 0x0 "MDMA_C14MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C14MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x400++0x3 line.long 0x0 "MDMA_C15ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA15,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF15,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF15,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF15,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF15,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF15,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x404++0x3 line.long 0x0 "MDMA_C15IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF15,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF15,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF15,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF15,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF15,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x408++0x3 line.long 0x0 "MDMA_C15ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x40C++0x1F line.long 0x0 "MDMA_C15CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C15TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C15BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C15SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C15DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C15BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C15LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C15TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x430++0x7 line.long 0x0 "MDMA_C15MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C15MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x0++0x3 line.long 0x0 "GISR0,MDMA Global Interrupt/Status" bitfld.long 0x0 15. "GIF15,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 14. "GIF14,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 13. "GIF13,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 12. "GIF12,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 11. "GIF11,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 10. "GIF10,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 9. "GIF9,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 8. "GIF8,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 7. "GIF7,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 6. "GIF6,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 5. "GIF5,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 4. "GIF4,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 3. "GIF3,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 2. "GIF2,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 1. "GIF1,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 0. "GIF0,Channel x global interrupt flag (x=...)" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "C0ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA0,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF0,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF0,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF0,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF0,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF0,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x44++0x3 line.long 0x0 "C0IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF0,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF0,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF0,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF0,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF0,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "C0ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x4C++0x1F line.long 0x0 "C0CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C0TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C0BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C0SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C0DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C0BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C0LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C0TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x70++0x7 line.long 0x0 "C0MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C0MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x80++0x3 line.long 0x0 "C1ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA1,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF1,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF1,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF1,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF1,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x84++0x3 line.long 0x0 "C1IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF1,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF1,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF1,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF1,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF1,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x88++0x3 line.long 0x0 "C1ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x8C++0x1F line.long 0x0 "C1CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C1TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C1BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C1SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C1DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C1BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C1LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C1TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xB0++0x7 line.long 0x0 "C1MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C1MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0xC0++0x3 line.long 0x0 "C2ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA2,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF2,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF2,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF2,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF2,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF2,Channel x transfer error interrupt flag" "0,1" wgroup.long 0xC4++0x3 line.long 0x0 "C2IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF2,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF2,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF2,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF2,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF2,Channel x clear transfer error interrupt" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "C2ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0xCC++0x1F line.long 0x0 "C2CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C2TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C2BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C2SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C2DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C2BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C2LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C2TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xF0++0x7 line.long 0x0 "C2MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C2MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x100++0x3 line.long 0x0 "C3ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA3,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF3,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF3,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF3,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF3,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF3,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x104++0x3 line.long 0x0 "C3IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF3,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF3,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF3,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF3,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF3,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "C3ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x10C++0x1F line.long 0x0 "C3CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C3TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C3BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C3SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C3DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C3BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C3LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C3TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x130++0x7 line.long 0x0 "C3MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C3MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x140++0x3 line.long 0x0 "C4ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA4,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF4,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF4,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF4,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF4,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF4,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "C4IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF4,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF4,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF4,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF4,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF4,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "C4ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x14C++0x1F line.long 0x0 "C4CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C4TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C4BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C4SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C4DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C4BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C4LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C4TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x170++0x7 line.long 0x0 "C4MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C4MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x180++0x3 line.long 0x0 "C5ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA5,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF5,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF5,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF5,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF5,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF5,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x184++0x3 line.long 0x0 "C5IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF5,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF5,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF5,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF5,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF5,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "C5ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x18C++0x1F line.long 0x0 "C5CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C5TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C5BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C5SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C5DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C5BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C5LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C5TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1B0++0x7 line.long 0x0 "C5MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C5MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x1C0++0x3 line.long 0x0 "C6ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA6,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF6,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF6,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF6,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF6,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF6,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x1C4++0x3 line.long 0x0 "C6IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF6,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF6,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF6,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF6,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF6,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x1C8++0x3 line.long 0x0 "C6ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x1CC++0x1F line.long 0x0 "C6CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C6TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C6BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C6SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C6DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C6BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C6LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C6TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1F0++0x7 line.long 0x0 "C6MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C6MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x200++0x3 line.long 0x0 "C7ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA7,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF7,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF7,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF7,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF7,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF7,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x204++0x3 line.long 0x0 "C7IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF7,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF7,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF7,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF7,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF7,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "C7ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x20C++0x1F line.long 0x0 "C7CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C7TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C7BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C7SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C7DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C7BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C7LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C7TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x230++0x7 line.long 0x0 "C7MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C7MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x240++0x3 line.long 0x0 "C8ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA8,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF8,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF8,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF8,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF8,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF8,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x244++0x3 line.long 0x0 "C8IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF8,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF8,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF8,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF8,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF8,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "C8ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x24C++0x1F line.long 0x0 "C8CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C8TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C8BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C8SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C8DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C8BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C8LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C8TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x270++0x7 line.long 0x0 "C8MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C8MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x280++0x3 line.long 0x0 "C9ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA9,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF9,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF9,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF9,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF9,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF9,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x284++0x3 line.long 0x0 "C9IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF9,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF9,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF9,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF9,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF9,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "C9ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x28C++0x1F line.long 0x0 "C9CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C9TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C9BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C9SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C9DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C9BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C9LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C9TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2B0++0x7 line.long 0x0 "C9MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C9MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x2C0++0x3 line.long 0x0 "C10ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA10,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF10,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF10,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF10,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF10,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF10,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x2C4++0x3 line.long 0x0 "C10IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF10,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF10,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF10,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF10,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF10,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x2C8++0x3 line.long 0x0 "C10ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x2CC++0x1F line.long 0x0 "C10CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C10TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C10BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C10SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C10DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C10BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C10LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C10TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2F0++0x7 line.long 0x0 "C10MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C10MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x300++0x3 line.long 0x0 "C11ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA11,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF11,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF11,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF11,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF11,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF11,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x304++0x3 line.long 0x0 "C11IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF11,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF11,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF11,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF11,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF11,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x308++0x3 line.long 0x0 "C11ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x30C++0x1F line.long 0x0 "C11CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C11TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C11BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C11SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C11DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C11BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C11LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C11TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x330++0x7 line.long 0x0 "C11MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C11MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x340++0x3 line.long 0x0 "C12ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA12,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF12,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF12,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF12,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF12,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF12,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x344++0x3 line.long 0x0 "C12IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF12,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF12,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF12,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF12,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF12,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x348++0x3 line.long 0x0 "C12ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x34C++0x1F line.long 0x0 "C12CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C12TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C12BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C12SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C12DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C12BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C12LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C12TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x370++0x7 line.long 0x0 "C12MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C12MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x380++0x3 line.long 0x0 "C13ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA13,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF13,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF13,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF13,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF13,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF13,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x384++0x3 line.long 0x0 "C13IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF13,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF13,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF13,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF13,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF13,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x388++0x3 line.long 0x0 "C13ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x38C++0x1F line.long 0x0 "C13CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C13TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C13BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C13SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C13DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C13BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C13LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C13TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3B0++0x7 line.long 0x0 "C13MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C13MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x3C0++0x3 line.long 0x0 "C14ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA14,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF14,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF14,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF14,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF14,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF14,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x3C4++0x3 line.long 0x0 "C14IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF14,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF14,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF14,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF14,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF14,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x3C8++0x3 line.long 0x0 "C14ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x3CC++0x1F line.long 0x0 "C14CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C14TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C14BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C14SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C14DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C14BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C14LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C14TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3F0++0x7 line.long 0x0 "C14MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C14MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x400++0x3 line.long 0x0 "C15ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA15,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF15,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF15,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF15,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF15,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF15,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x404++0x3 line.long 0x0 "C15IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF15,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF15,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF15,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF15,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF15,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x408++0x3 line.long 0x0 "C15ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x40C++0x1F line.long 0x0 "C15CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "C15TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline bitfld.long 0x4 15.--17. "DBURST,Destination burst transfer" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SBURST,source burst transfer" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "C15BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "C15SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "C15DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "C15BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "C15LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "C15TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x430++0x7 line.long 0x0 "C15MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "C15MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" endif sif (cpuis("STM32H7B0*")) rgroup.long 0x0++0x3 line.long 0x0 "MDMA_GISR0,MDMA Global Interrupt/Status" bitfld.long 0x0 15. "GIF15,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 14. "GIF14,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 13. "GIF13,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 12. "GIF12,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 11. "GIF11,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 10. "GIF10,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 9. "GIF9,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 8. "GIF8,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 7. "GIF7,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 6. "GIF6,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 5. "GIF5,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 4. "GIF4,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 3. "GIF3,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 2. "GIF2,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 1. "GIF1,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 0. "GIF0,Channel x global interrupt flag (x=...)" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MDMA_C0ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA0,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF0,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF0,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF0,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF0,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF0,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x44++0x3 line.long 0x0 "MDMA_C0IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF0,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF0,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF0,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF0,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF0,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "MDMA_C0ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x4C++0x1F line.long 0x0 "MDMA_C0CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C0TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C0BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C0SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C0DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C0BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C0LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C0TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x70++0x7 line.long 0x0 "MDMA_C0MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C0MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x80++0x3 line.long 0x0 "MDMA_C1ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA1,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF1,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF1,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF1,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF1,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x84++0x3 line.long 0x0 "MDMA_C1IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF1,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF1,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF1,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF1,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF1,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x88++0x3 line.long 0x0 "MDMA_C1ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x8C++0x1F line.long 0x0 "MDMA_C1CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C1TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C1BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C1SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C1DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C1BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C1LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C1TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xB0++0x7 line.long 0x0 "MDMA_C1MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C1MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0xC0++0x3 line.long 0x0 "MDMA_C2ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA2,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF2,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF2,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF2,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF2,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF2,Channel x transfer error interrupt flag" "0,1" wgroup.long 0xC4++0x3 line.long 0x0 "MDMA_C2IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF2,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF2,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF2,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF2,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF2,Channel x clear transfer error interrupt" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "MDMA_C2ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0xCC++0x1F line.long 0x0 "MDMA_C2CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C2TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C2BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C2SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C2DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C2BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C2LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C2TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xF0++0x7 line.long 0x0 "MDMA_C2MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C2MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x100++0x3 line.long 0x0 "MDMA_C3ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA3,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF3,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF3,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF3,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF3,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF3,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x104++0x3 line.long 0x0 "MDMA_C3IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF3,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF3,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF3,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF3,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF3,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "MDMA_C3ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x10C++0x1F line.long 0x0 "MDMA_C3CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C3TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C3BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C3SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C3DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C3BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C3LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C3TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x130++0x7 line.long 0x0 "MDMA_C3MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C3MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x140++0x3 line.long 0x0 "MDMA_C4ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA4,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF4,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF4,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF4,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF4,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF4,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "MDMA_C4IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF4,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF4,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF4,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF4,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF4,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "MDMA_C4ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x14C++0x1F line.long 0x0 "MDMA_C4CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C4TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C4BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C4SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C4DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C4BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C4LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C4TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x170++0x7 line.long 0x0 "MDMA_C4MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C4MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x180++0x3 line.long 0x0 "MDMA_C5ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA5,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF5,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF5,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF5,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF5,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF5,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x184++0x3 line.long 0x0 "MDMA_C5IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF5,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF5,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF5,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF5,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF5,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "MDMA_C5ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x18C++0x1F line.long 0x0 "MDMA_C5CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C5TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C5BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C5SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C5DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C5BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C5LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C5TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1B0++0x7 line.long 0x0 "MDMA_C5MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C5MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x1C0++0x3 line.long 0x0 "MDMA_C6ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA6,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF6,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF6,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF6,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF6,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF6,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x1C4++0x3 line.long 0x0 "MDMA_C6IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF6,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF6,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF6,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF6,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF6,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x1C8++0x3 line.long 0x0 "MDMA_C6ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x1CC++0x1F line.long 0x0 "MDMA_C6CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C6TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C6BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C6SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C6DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C6BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C6LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C6TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1F0++0x7 line.long 0x0 "MDMA_C6MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C6MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x200++0x3 line.long 0x0 "MDMA_C7ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA7,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF7,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF7,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF7,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF7,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF7,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x204++0x3 line.long 0x0 "MDMA_C7IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF7,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF7,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF7,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF7,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF7,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "MDMA_C7ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x20C++0x1F line.long 0x0 "MDMA_C7CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C7TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C7BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C7SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C7DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C7BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C7LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C7TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x230++0x7 line.long 0x0 "MDMA_C7MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C7MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x240++0x3 line.long 0x0 "MDMA_C8ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA8,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF8,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF8,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF8,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF8,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF8,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x244++0x3 line.long 0x0 "MDMA_C8IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF8,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF8,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF8,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF8,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF8,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "MDMA_C8ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x24C++0x1F line.long 0x0 "MDMA_C8CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C8TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C8BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C8SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C8DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C8BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C8LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C8TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x270++0x7 line.long 0x0 "MDMA_C8MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C8MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x280++0x3 line.long 0x0 "MDMA_C9ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA9,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF9,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF9,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF9,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF9,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF9,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x284++0x3 line.long 0x0 "MDMA_C9IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF9,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF9,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF9,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF9,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF9,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "MDMA_C9ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x28C++0x1F line.long 0x0 "MDMA_C9CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C9TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C9BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C9SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C9DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C9BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C9LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C9TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2B0++0x7 line.long 0x0 "MDMA_C9MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C9MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x2C0++0x3 line.long 0x0 "MDMA_C10ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA10,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF10,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF10,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF10,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF10,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF10,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x2C4++0x3 line.long 0x0 "MDMA_C10IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF10,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF10,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF10,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF10,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF10,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x2C8++0x3 line.long 0x0 "MDMA_C10ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x2CC++0x1F line.long 0x0 "MDMA_C10CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C10TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C10BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C10SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C10DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C10BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C10LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C10TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2F0++0x7 line.long 0x0 "MDMA_C10MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C10MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x300++0x3 line.long 0x0 "MDMA_C11ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA11,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF11,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF11,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF11,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF11,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF11,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x304++0x3 line.long 0x0 "MDMA_C11IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF11,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF11,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF11,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF11,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF11,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x308++0x3 line.long 0x0 "MDMA_C11ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x30C++0x1F line.long 0x0 "MDMA_C11CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C11TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C11BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C11SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C11DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C11BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C11LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C11TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x330++0x7 line.long 0x0 "MDMA_C11MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C11MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x340++0x3 line.long 0x0 "MDMA_C12ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA12,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF12,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF12,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF12,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF12,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF12,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x344++0x3 line.long 0x0 "MDMA_C12IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF12,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF12,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF12,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF12,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF12,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x348++0x3 line.long 0x0 "MDMA_C12ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x34C++0x1F line.long 0x0 "MDMA_C12CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C12TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C12BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C12SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C12DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C12BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C12LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C12TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x370++0x7 line.long 0x0 "MDMA_C12MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C12MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x380++0x3 line.long 0x0 "MDMA_C13ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA13,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF13,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF13,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF13,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF13,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF13,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x384++0x3 line.long 0x0 "MDMA_C13IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF13,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF13,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF13,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF13,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF13,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x388++0x3 line.long 0x0 "MDMA_C13ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x38C++0x1F line.long 0x0 "MDMA_C13CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C13TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C13BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C13SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C13DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C13BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C13LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C13TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3B0++0x7 line.long 0x0 "MDMA_C13MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C13MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x3C0++0x3 line.long 0x0 "MDMA_C14ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA14,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF14,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF14,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF14,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF14,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF14,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x3C4++0x3 line.long 0x0 "MDMA_C14IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF14,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF14,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF14,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF14,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF14,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x3C8++0x3 line.long 0x0 "MDMA_C14ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x3CC++0x1F line.long 0x0 "MDMA_C14CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C14TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C14BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C14SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C14DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C14BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C14LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C14TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3F0++0x7 line.long 0x0 "MDMA_C14MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C14MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x400++0x3 line.long 0x0 "MDMA_C15ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA15,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF15,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF15,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF15,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF15,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF15,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x404++0x3 line.long 0x0 "MDMA_C15IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF15,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF15,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF15,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF15,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF15,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x408++0x3 line.long 0x0 "MDMA_C15ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x40C++0x1F line.long 0x0 "MDMA_C15CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C15TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C15BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C15SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C15DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C15BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C15LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C15TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x430++0x7 line.long 0x0 "MDMA_C15MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C15MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" endif sif (cpuis("STM32H7B3*")) rgroup.long 0x0++0x3 line.long 0x0 "MDMA_GISR0,MDMA Global Interrupt/Status" bitfld.long 0x0 15. "GIF15,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 14. "GIF14,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 13. "GIF13,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 12. "GIF12,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 11. "GIF11,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 10. "GIF10,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 9. "GIF9,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 8. "GIF8,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 7. "GIF7,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 6. "GIF6,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 5. "GIF5,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 4. "GIF4,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 3. "GIF3,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 2. "GIF2,Channel x global interrupt flag (x=...)" "0,1" newline bitfld.long 0x0 1. "GIF1,Channel x global interrupt flag (x=...)" "0,1" bitfld.long 0x0 0. "GIF0,Channel x global interrupt flag (x=...)" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MDMA_C0ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA0,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF0,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF0,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF0,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF0,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF0,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x44++0x3 line.long 0x0 "MDMA_C0IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF0,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF0,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF0,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF0,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF0,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x48++0x3 line.long 0x0 "MDMA_C0ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x4C++0x1F line.long 0x0 "MDMA_C0CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C0TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C0BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C0SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C0DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C0BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C0LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C0TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x70++0x7 line.long 0x0 "MDMA_C0MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C0MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x80++0x3 line.long 0x0 "MDMA_C1ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA1,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF1,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF1,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF1,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF1,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF1,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x84++0x3 line.long 0x0 "MDMA_C1IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF1,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF1,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF1,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF1,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF1,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x88++0x3 line.long 0x0 "MDMA_C1ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x8C++0x1F line.long 0x0 "MDMA_C1CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C1TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C1BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C1SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C1DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C1BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C1LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C1TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xB0++0x7 line.long 0x0 "MDMA_C1MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C1MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0xC0++0x3 line.long 0x0 "MDMA_C2ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA2,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF2,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF2,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF2,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF2,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF2,Channel x transfer error interrupt flag" "0,1" wgroup.long 0xC4++0x3 line.long 0x0 "MDMA_C2IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF2,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF2,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF2,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF2,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF2,Channel x clear transfer error interrupt" "0,1" rgroup.long 0xC8++0x3 line.long 0x0 "MDMA_C2ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0xCC++0x1F line.long 0x0 "MDMA_C2CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C2TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C2BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C2SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C2DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C2BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C2LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C2TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0xF0++0x7 line.long 0x0 "MDMA_C2MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C2MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x100++0x3 line.long 0x0 "MDMA_C3ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA3,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF3,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF3,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF3,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF3,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF3,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x104++0x3 line.long 0x0 "MDMA_C3IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF3,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF3,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF3,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF3,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF3,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x108++0x3 line.long 0x0 "MDMA_C3ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x10C++0x1F line.long 0x0 "MDMA_C3CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C3TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C3BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C3SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C3DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C3BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C3LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C3TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x130++0x7 line.long 0x0 "MDMA_C3MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C3MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x140++0x3 line.long 0x0 "MDMA_C4ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA4,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF4,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF4,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF4,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF4,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF4,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x144++0x3 line.long 0x0 "MDMA_C4IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF4,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF4,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF4,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF4,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF4,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x148++0x3 line.long 0x0 "MDMA_C4ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x14C++0x1F line.long 0x0 "MDMA_C4CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C4TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C4BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C4SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C4DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C4BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C4LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C4TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x170++0x7 line.long 0x0 "MDMA_C4MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C4MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x180++0x3 line.long 0x0 "MDMA_C5ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA5,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF5,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF5,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF5,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF5,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF5,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x184++0x3 line.long 0x0 "MDMA_C5IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF5,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF5,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF5,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF5,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF5,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x188++0x3 line.long 0x0 "MDMA_C5ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x18C++0x1F line.long 0x0 "MDMA_C5CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C5TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C5BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C5SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C5DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C5BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C5LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C5TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1B0++0x7 line.long 0x0 "MDMA_C5MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C5MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x1C0++0x3 line.long 0x0 "MDMA_C6ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA6,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF6,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF6,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF6,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF6,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF6,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x1C4++0x3 line.long 0x0 "MDMA_C6IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF6,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF6,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF6,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF6,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF6,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x1C8++0x3 line.long 0x0 "MDMA_C6ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x1CC++0x1F line.long 0x0 "MDMA_C6CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C6TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C6BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C6SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C6DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C6BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C6LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C6TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x1F0++0x7 line.long 0x0 "MDMA_C6MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C6MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x200++0x3 line.long 0x0 "MDMA_C7ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA7,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF7,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF7,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF7,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF7,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF7,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x204++0x3 line.long 0x0 "MDMA_C7IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF7,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF7,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF7,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF7,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF7,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x208++0x3 line.long 0x0 "MDMA_C7ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x20C++0x1F line.long 0x0 "MDMA_C7CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C7TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C7BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C7SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C7DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C7BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C7LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C7TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x230++0x7 line.long 0x0 "MDMA_C7MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C7MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x240++0x3 line.long 0x0 "MDMA_C8ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA8,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF8,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF8,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF8,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF8,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF8,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x244++0x3 line.long 0x0 "MDMA_C8IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF8,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF8,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF8,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF8,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF8,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x248++0x3 line.long 0x0 "MDMA_C8ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x24C++0x1F line.long 0x0 "MDMA_C8CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C8TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C8BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C8SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C8DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C8BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C8LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C8TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x270++0x7 line.long 0x0 "MDMA_C8MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C8MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x280++0x3 line.long 0x0 "MDMA_C9ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA9,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF9,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF9,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF9,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF9,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF9,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x284++0x3 line.long 0x0 "MDMA_C9IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF9,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF9,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF9,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF9,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF9,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x288++0x3 line.long 0x0 "MDMA_C9ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x28C++0x1F line.long 0x0 "MDMA_C9CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C9TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C9BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C9SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C9DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C9BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C9LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C9TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2B0++0x7 line.long 0x0 "MDMA_C9MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C9MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x2C0++0x3 line.long 0x0 "MDMA_C10ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA10,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF10,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF10,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF10,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF10,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF10,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x2C4++0x3 line.long 0x0 "MDMA_C10IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF10,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF10,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF10,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF10,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF10,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x2C8++0x3 line.long 0x0 "MDMA_C10ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x2CC++0x1F line.long 0x0 "MDMA_C10CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C10TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C10BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C10SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C10DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C10BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C10LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C10TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x2F0++0x7 line.long 0x0 "MDMA_C10MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C10MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x300++0x3 line.long 0x0 "MDMA_C11ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA11,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF11,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF11,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF11,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF11,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF11,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x304++0x3 line.long 0x0 "MDMA_C11IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF11,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF11,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF11,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF11,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF11,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x308++0x3 line.long 0x0 "MDMA_C11ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x30C++0x1F line.long 0x0 "MDMA_C11CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C11TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C11BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C11SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C11DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C11BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C11LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C11TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x330++0x7 line.long 0x0 "MDMA_C11MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C11MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x340++0x3 line.long 0x0 "MDMA_C12ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA12,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF12,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF12,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF12,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF12,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF12,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x344++0x3 line.long 0x0 "MDMA_C12IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF12,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF12,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF12,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF12,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF12,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x348++0x3 line.long 0x0 "MDMA_C12ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x34C++0x1F line.long 0x0 "MDMA_C12CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C12TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C12BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C12SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C12DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C12BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C12LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C12TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x370++0x7 line.long 0x0 "MDMA_C12MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C12MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x380++0x3 line.long 0x0 "MDMA_C13ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA13,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF13,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF13,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF13,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF13,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF13,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x384++0x3 line.long 0x0 "MDMA_C13IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF13,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF13,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF13,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF13,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF13,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x388++0x3 line.long 0x0 "MDMA_C13ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x38C++0x1F line.long 0x0 "MDMA_C13CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C13TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C13BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C13SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C13DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C13BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C13LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C13TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3B0++0x7 line.long 0x0 "MDMA_C13MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C13MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x3C0++0x3 line.long 0x0 "MDMA_C14ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA14,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF14,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF14,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF14,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF14,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF14,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x3C4++0x3 line.long 0x0 "MDMA_C14IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF14,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF14,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF14,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF14,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF14,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x3C8++0x3 line.long 0x0 "MDMA_C14ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x3CC++0x1F line.long 0x0 "MDMA_C14CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C14TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C14BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C14SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C14DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C14BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C14LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C14TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x3F0++0x7 line.long 0x0 "MDMA_C14MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C14MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" rgroup.long 0x400++0x3 line.long 0x0 "MDMA_C15ISR,MDMA channel x interrupt/status" bitfld.long 0x0 16. "CRQA15,channel x request active" "0,1" bitfld.long 0x0 4. "TCIF15,channel x buffer transfer" "0,1" newline bitfld.long 0x0 3. "BTIF15,Channel x block transfer complete" "0,1" bitfld.long 0x0 2. "BRTIF15,Channel x block repeat transfer complete" "0,1" newline bitfld.long 0x0 1. "CTCIF15,Channel x Channel Transfer Complete" "0,1" bitfld.long 0x0 0. "TEIF15,Channel x transfer error interrupt flag" "0,1" wgroup.long 0x404++0x3 line.long 0x0 "MDMA_C15IFCR,MDMA channel x interrupt flag clear" bitfld.long 0x0 4. "CLTCIF15,CLear buffer Transfer Complete Interrupt" "0,1" bitfld.long 0x0 3. "CBTIF15,Channel x Clear block transfer complete" "0,1" newline bitfld.long 0x0 2. "CBRTIF15,Channel x clear block repeat transfer" "0,1" bitfld.long 0x0 1. "CCTCIF15,Clear Channel transfer complete" "0,1" newline bitfld.long 0x0 0. "CTEIF15,Channel x clear transfer error interrupt" "0,1" rgroup.long 0x408++0x3 line.long 0x0 "MDMA_C15ESR,MDMA Channel x error status" bitfld.long 0x0 11. "BSE,Block Size Error These bit is set by HW " "0,1" bitfld.long 0x0 10. "ASE,Address/Size Error These bit is set by" "0,1" newline bitfld.long 0x0 9. "TEMD,Transfer Error Mask Data These bit is" "0,1" bitfld.long 0x0 8. "TELD,Transfer Error Link Data These bit is" "0,1" newline bitfld.long 0x0 7. "TED,Transfer Error Direction These bit is" "0,1" hexmask.long.byte 0x0 0.--6. 1. "TEA,Transfer Error Address These bits are" group.long 0x40C++0x1F line.long 0x0 "MDMA_C15CR,This register is used to control the" bitfld.long 0x0 16. "SWRQ,SW ReQuest Writing a 1 into this bit" "0,1" bitfld.long 0x0 14. "WEX,Word Endianness exchange" "0,1" newline bitfld.long 0x0 13. "HEX,Half word Endianes" "0,1" bitfld.long 0x0 12. "BEX,byte Endianness exchange" "0,1" newline bitfld.long 0x0 6.--7. "PL,Priority level These bits are set and" "0,1,2,3" bitfld.long 0x0 5. "TCIE,buffer Transfer Complete interrupt" "0,1" newline bitfld.long 0x0 4. "BTIE,Block Transfer interrupt enable This bit" "0,1" bitfld.long 0x0 3. "BRTIE,Block Repeat transfer interrupt enable" "0,1" newline bitfld.long 0x0 2. "CTCIE,Channel Transfer Complete interrupt" "0,1" bitfld.long 0x0 1. "TEIE,Transfer error interrupt enable This bit" "0,1" newline bitfld.long 0x0 0. "EN,channel enable" "0,1" line.long 0x4 "MDMA_C15TCR,This register is used to configure the" bitfld.long 0x4 31. "BWM,Bufferable Write Mode This bit is set" "0,1" bitfld.long 0x4 30. "SWRM,SW Request Mode This bit is set and" "0,1" newline bitfld.long 0x4 28.--29. "TRGM,Trigger Mode These bits are set and" "0,1,2,3" bitfld.long 0x4 26.--27. "PAM,Padding/Alignement Mode These bits are" "?,1: Source data size,2: Source data size larger than,?" newline bitfld.long 0x4 25. "PKE,PacK Enable These bit is set and cleared" "0,1" hexmask.long.byte 0x4 18.--24. 1. "TLEN,buffer transfer lengh" newline hexmask.long.byte 0x4 15.--18. 1. "DBURST,Destination burst transfer" hexmask.long.byte 0x4 12.--15. 1. "SBURST,source burst transfer" newline bitfld.long 0x4 10.--11. "DINCOS,Destination increment" "0,1,2,3" bitfld.long 0x4 8.--9. "SINCOS,source increment offset" "0,1,2,3" newline bitfld.long 0x4 6.--7. "DSIZE,Destination data size These bits are set" "0,1,2,3" bitfld.long 0x4 4.--5. "SSIZE,Source data size These bits are set and" "0,1,2,3" newline bitfld.long 0x4 2.--3. "DINC,Destination increment mode These bits" "0,1,2,3" bitfld.long 0x4 0.--1. "SINC,Source increment mode These bits are set" "0,1,2,3" line.long 0x8 "MDMA_C15BNDTR,MDMA Channel x block number of data" hexmask.long.word 0x8 20.--31. 1. "BRC,Block Repeat Count This field contains" bitfld.long 0x8 19. "BRDUM,Block Repeat Destination address Update" "0,1" newline bitfld.long 0x8 18. "BRSUM,Block Repeat Source address Update Mode" "0,1" hexmask.long.tbyte 0x8 0.--16. 1. "BNDT,block number of data to" line.long 0xC "MDMA_C15SAR,MDMA channel x source address" hexmask.long 0xC 0.--31. 1. "SAR,source adr base" line.long 0x10 "MDMA_C15DAR,MDMA channel x destination address" hexmask.long 0x10 0.--31. 1. "DAR,Destination adr base" line.long 0x14 "MDMA_C15BRUR,MDMA channel x Block Repeat address Update" hexmask.long.word 0x14 16.--31. 1. "DUV,destination address update" hexmask.long.word 0x14 0.--15. 1. "SUV,source adresse update" line.long 0x18 "MDMA_C15LAR,MDMA channel x Link Address" hexmask.long 0x18 0.--31. 1. "LAR,Link address register" line.long 0x1C "MDMA_C15TBR,MDMA channel x Trigger and Bus selection" bitfld.long 0x1C 17. "DBUS,Destination BUS slect This bit is" "0,1" bitfld.long 0x1C 16. "SBUS,Source BUS select This bit is protected" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "TSEL,Trigger selection" group.long 0x430++0x7 line.long 0x0 "MDMA_C15MAR,MDMA channel x Mask address" hexmask.long 0x0 0.--31. 1. "MAR,Mask address" line.long 0x4 "MDMA_C15MDR,MDMA channel x Mask Data" hexmask.long 0x4 0.--31. 1. "MDR,Mask data" endif tree.end sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "OCTOSPI (Octo-SPI Interface)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7A3*")) tree "OCTOSPI1" base ad:0x52005000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 24.--25. "MTYP,Memory type" "0,1,2,3" endif hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" sif (cpuis("STM32H7A3*")) bitfld.long 0x0 8.--10. "CSHT,Chip-select high time" "0,1,2,3,4,5,6,7" endif bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" endif sif (cpuis("STM32H7A3*")) hexmask.long.word 0xC 0.--15. 1. "REFRESH,Refresh rate" endif rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" bitfld.long 0x0 4. "TOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Clear status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "TEF,Clear transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADRESS,Adress" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Match" group.long 0x90++0x3 line.long 0x0 "PIR,OCTOSPI polling interval" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,polling interval register" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,communication configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,timing configuration register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,instruction register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,alternate bytes register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,low-power timeout register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration" bitfld.long 0x0 29. "DQSE,DQSE" "0,1" bitfld.long 0x0 27. "DDTR,DDTR" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 3. "ISIZE,Instruction size" "0,1" bitfld.long 0x0 2. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--1. "IMODE,Instruction mode" "0,1,2,3" endif group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration" hexmask.long.byte 0x0 0.--4. 1. "DCYC,DCYC" group.long 0x190++0x3 line.long 0x0 "WIR,OCTOSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBusTM latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7A3*")) tree "OCTOSPI2" base ad:0x5200A000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 24.--26. "MTYP,Memory type" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--13. 1. "CSHT,Chip-select high time" bitfld.long 0x0 3. "DLYBYP,Delay block bypass" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 24.--25. "MTYP,Memory type" "0,1,2,3" endif hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" sif (cpuis("STM32H7A3*")) bitfld.long 0x0 8.--10. "CSHT,Chip-select high time" "0,1,2,3,4,5,6,7" endif bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register" bitfld.long 0x4 16.--18. "WRAPSIZE,Wrap size" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) hexmask.long 0xC 0.--31. 1. "REFRESH,Refresh rate" endif sif (cpuis("STM32H7A3*")) hexmask.long.word 0xC 0.--15. 1. "REFRESH,Refresh rate" endif rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" bitfld.long 0x0 4. "TOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Clear status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "TEF,Clear transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADRESS,Adress" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Match" group.long 0x90++0x3 line.long 0x0 "PIR,OCTOSPI polling interval" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval" group.long 0x100++0x3 line.long 0x0 "CCR,polling interval register" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x108++0x3 line.long 0x0 "TCR,communication configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,timing configuration register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,instruction register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,alternate bytes register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,low-power timeout register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration" bitfld.long 0x0 29. "DQSE,DQSE" "0,1" bitfld.long 0x0 27. "DDTR,DDTR" "0,1" bitfld.long 0x0 24.--26. "DMODE,Data mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" bitfld.long 0x0 16.--18. "ABMODE,Alternate-byte mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline bitfld.long 0x0 8.--10. "ADMODE,Address mode" "0,1,2,3,4,5,6,7" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--2. "IMODE,Instruction mode" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 3. "ISIZE,Instruction size" "0,1" bitfld.long 0x0 2. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--1. "IMODE,Instruction mode" "0,1,2,3" endif group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration" hexmask.long.byte 0x0 0.--4. 1. "DCYC,DCYC" group.long 0x190++0x3 line.long 0x0 "WIR,OCTOSPI write instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,Instruction" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBusTM latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" tree.end endif sif (cpuis("STM32H7B0*")) tree "OCTOSPI2" base ad:0x5200A000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register" bitfld.long 0x0 24.--25. "MTYP,Memory type" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--11. 1. "CSHT,Chip-select high time" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register" hexmask.long.byte 0x4 16.--19. 1. "WRAPSIZE,Wrap size" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long.word 0xC 0.--15. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADRESS,Adress" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Match" group.long 0x100++0x3 line.long 0x0 "CCR,polling interval register" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x108++0x3 line.long 0x0 "TCR,communication configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,timing configuration register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,instruction register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,alternate bytes register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,low-power timeout register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration" bitfld.long 0x0 29. "DQSE,DQSE" "0,1" bitfld.long 0x0 27. "DDTR,DDTR" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate-byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 3. "ISIZE,Instruction size" "0,1" bitfld.long 0x0 2. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--1. "IMODE,Instruction mode" "0,1,2,3" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration" hexmask.long.byte 0x0 0.--4. 1. "DCYC,DCYC" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBusTM latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" group.long 0x90++0x3 line.long 0x0 "PIR,OCTOSPI polling interval" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval" group.long 0x190++0x3 line.long 0x0 "WIR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" tree.end endif sif (cpuis("STM32H7B0*")) tree "OCTOSPI1" base ad:0x52005000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register" bitfld.long 0x0 24.--25. "MTYP,Memory type" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--11. 1. "CSHT,Chip-select high time" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register" hexmask.long.byte 0x4 16.--19. 1. "WRAPSIZE,Wrap size" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long.word 0xC 0.--15. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADRESS,Adress" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Match" group.long 0x100++0x3 line.long 0x0 "CCR,polling interval register" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x108++0x3 line.long 0x0 "TCR,communication configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,timing configuration register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,instruction register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,alternate bytes register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,low-power timeout register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration" bitfld.long 0x0 29. "DQSE,DQSE" "0,1" bitfld.long 0x0 27. "DDTR,DDTR" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate-byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 3. "ISIZE,Instruction size" "0,1" bitfld.long 0x0 2. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--1. "IMODE,Instruction mode" "0,1,2,3" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration" hexmask.long.byte 0x0 0.--4. 1. "DCYC,DCYC" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBusTM latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" group.long 0x90++0x3 line.long 0x0 "PIR,OCTOSPI polling interval" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval" group.long 0x190++0x3 line.long 0x0 "WIR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" tree.end endif sif (cpuis("STM32H7B3*")) tree "OCTOSPI2" base ad:0x5200A000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register" bitfld.long 0x0 24.--25. "MTYP,Memory type" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--11. 1. "CSHT,Chip-select high time" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register" hexmask.long.byte 0x4 16.--19. 1. "WRAPSIZE,Wrap size" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long.word 0xC 0.--15. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADRESS,Adress" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Match" group.long 0x100++0x3 line.long 0x0 "CCR,polling interval register" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x108++0x3 line.long 0x0 "TCR,communication configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,timing configuration register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,instruction register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,alternate bytes register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,low-power timeout register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration" bitfld.long 0x0 29. "DQSE,DQSE" "0,1" bitfld.long 0x0 27. "DDTR,DDTR" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate-byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 3. "ISIZE,Instruction size" "0,1" bitfld.long 0x0 2. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--1. "IMODE,Instruction mode" "0,1,2,3" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration" hexmask.long.byte 0x0 0.--4. 1. "DCYC,DCYC" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBusTM latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" group.long 0x90++0x3 line.long 0x0 "PIR,OCTOSPI polling interval" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval" group.long 0x190++0x3 line.long 0x0 "WIR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" tree.end endif sif (cpuis("STM32H7B3*")) tree "OCTOSPI1" base ad:0x52005000 group.long 0x0++0x3 line.long 0x0 "CR,control register" bitfld.long 0x0 28.--29. "FMODE,Functional mode" "0,1,2,3" bitfld.long 0x0 23. "PMM,Polling match mode" "0,1" bitfld.long 0x0 22. "APMS,Automatic poll mode stop" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable" "0,1" bitfld.long 0x0 19. "SMIE,Status match interrupt" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt" "0,1" bitfld.long 0x0 17. "TCIE,Transfer complete interrupt" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,IFO threshold level" bitfld.long 0x0 7. "FSEL,FLASH memory selection" "0,1" bitfld.long 0x0 6. "DQM,Dual-quad mode" "0,1" bitfld.long 0x0 3. "TCEN,Timeout counter enable" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable" "0,1" bitfld.long 0x0 1. "ABORT,Abort request" "0,1" bitfld.long 0x0 0. "EN,Enable" "0,1" group.long 0x8++0xF line.long 0x0 "DCR1,device configuration register" bitfld.long 0x0 24.--25. "MTYP,Memory type" "0,1,2,3" hexmask.long.byte 0x0 16.--20. 1. "DEVSIZE,Device size" hexmask.long.byte 0x0 8.--11. 1. "CSHT,Chip-select high time" bitfld.long 0x0 1. "FRCK,Free running clock" "0,1" bitfld.long 0x0 0. "CKMODE,Mode 0 / mode 3" "0,1" line.long 0x4 "DCR2,device configuration register" hexmask.long.byte 0x4 16.--19. 1. "WRAPSIZE,Wrap size" hexmask.long.byte 0x4 0.--7. 1. "PRESCALER,Clock prescaler" line.long 0x8 "DCR3,device configuration register" hexmask.long.byte 0x8 16.--20. 1. "CSBOUND,CS boundary" hexmask.long.byte 0x8 0.--7. 1. "MAXTRAN,Maximum transfer" line.long 0xC "DCR4,DCR4" hexmask.long.word 0xC 0.--15. 1. "REFRESH,Refresh rate" rgroup.long 0x20++0x3 line.long 0x0 "SR,status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level" bitfld.long 0x0 5. "BUSY,Busy" "0,1" bitfld.long 0x0 4. "TOF,Timeout flag" "0,1" bitfld.long 0x0 3. "SMF,Status match flag" "0,1" bitfld.long 0x0 2. "FTF,FIFO threshold flag" "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag" "0,1" bitfld.long 0x0 0. "TEF,Transfer error flag" "0,1" wgroup.long 0x24++0x3 line.long 0x0 "FCR,flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag" "0,1" bitfld.long 0x0 1. "CTCF,Clear transfer complete" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag" "0,1" group.long 0x40++0x3 line.long 0x0 "DLR,data length register" hexmask.long 0x0 0.--31. 1. "DL,Data length" group.long 0x48++0x3 line.long 0x0 "AR,address register" hexmask.long 0x0 0.--31. 1. "ADRESS,Adress" group.long 0x50++0x3 line.long 0x0 "DR,data register" hexmask.long 0x0 0.--31. 1. "DATA,Data" group.long 0x80++0x3 line.long 0x0 "PSMKR,polling status mask register" hexmask.long 0x0 0.--31. 1. "MASK,Status mask" group.long 0x88++0x3 line.long 0x0 "PSMAR,polling status match register" hexmask.long 0x0 0.--31. 1. "MATCH,Match" group.long 0x100++0x3 line.long 0x0 "CCR,polling interval register" bitfld.long 0x0 31. "SIOO,Send instruction only once" "0,1" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" newline bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x108++0x3 line.long 0x0 "TCR,communication configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x110++0x3 line.long 0x0 "IR,timing configuration register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x120++0x3 line.long 0x0 "ABR,instruction register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x130++0x3 line.long 0x0 "LPTR,alternate bytes register" hexmask.long.word 0x0 0.--15. 1. "TIMEOUT,Timeout period" group.long 0x140++0x3 line.long 0x0 "WPCCR,low-power timeout register" bitfld.long 0x0 29. "DQSE,DQS enable" "0,1" bitfld.long 0x0 27. "DDTR,alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 4.--5. "ISIZE,Instruction size" "0,1,2,3" bitfld.long 0x0 3. "IDTR,Instruction double transfer" "0,1" hexmask.long.byte 0x0 0.--3. 1. "IMODE,Instruction mode" group.long 0x148++0x3 line.long 0x0 "WPTCR,wrap timing configuration" bitfld.long 0x0 30. "SSHIFT,Sample shift" "0,1" bitfld.long 0x0 28. "DHQC,Delay hold quarter cycle" "0,1" hexmask.long.byte 0x0 0.--4. 1. "DCYC,Number of dummy cycles" group.long 0x150++0x3 line.long 0x0 "WPIR,wrap instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" group.long 0x160++0x3 line.long 0x0 "WPABR,wrap alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x180++0x3 line.long 0x0 "WCCR,write communication configuration" bitfld.long 0x0 29. "DQSE,DQSE" "0,1" bitfld.long 0x0 27. "DDTR,DDTR" "0,1" hexmask.long.byte 0x0 24.--27. 1. "DMODE,Data mode" bitfld.long 0x0 20.--21. "ABSIZE,Alternate bytes size" "0,1,2,3" bitfld.long 0x0 19. "ABDTR,Alternate bytes double transfer" "0,1" hexmask.long.byte 0x0 16.--19. 1. "ABMODE,Alternate-byte mode" bitfld.long 0x0 12.--13. "ADSIZE,Address size" "0,1,2,3" bitfld.long 0x0 11. "ADDTR,Address double transfer" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "ADMODE,Address mode" bitfld.long 0x0 3. "ISIZE,Instruction size" "0,1" bitfld.long 0x0 2. "IDTR,Instruction double transfer" "0,1" bitfld.long 0x0 0.--1. "IMODE,Instruction mode" "0,1,2,3" group.long 0x188++0x3 line.long 0x0 "WTCR,write timing configuration" hexmask.long.byte 0x0 0.--4. 1. "DCYC,DCYC" group.long 0x1A0++0x3 line.long 0x0 "WABR,write alternate bytes register" hexmask.long 0x0 0.--31. 1. "ALTERNATE,Alternate bytes" group.long 0x200++0x3 line.long 0x0 "HLCR,HyperBusTM latency configuration" hexmask.long.byte 0x0 16.--23. 1. "TRWR,Read write recovery time" hexmask.long.byte 0x0 8.--15. 1. "TACC,Access time" bitfld.long 0x0 1. "WZL,Write zero latency" "0,1" bitfld.long 0x0 0. "LM,Latency mode" "0,1" group.long 0x90++0x3 line.long 0x0 "PIR,OCTOSPI polling interval" hexmask.long.word 0x0 0.--15. 1. "INTERVAL,Polling interval" group.long 0x190++0x3 line.long 0x0 "WIR,instruction register" hexmask.long 0x0 0.--31. 1. "INSTRUCTION,INSTRUCTION" tree.end endif tree.end tree "OCTOSPIM (OCTOSPI I/O Manager)" base ad:0x5200B400 group.long 0x0++0xB line.long 0x0 "CR,OctoSPI IO Manager Control" hexmask.long.byte 0x0 16.--23. 1. "REQ2ACK_TIME,REQ to ACK Time" bitfld.long 0x0 0. "MUXEN,Multiplexed mode Enable" "0,1" line.long 0x4 "P1CR,OctoSPI IO Manager Port 1 configuration" bitfld.long 0x4 25.--26. "IOHSRC,IOHSRC" "0,1,2,3" bitfld.long 0x4 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x4 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x4 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x4 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x4 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x4 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x4 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x4 1. "CLKSRC,CLK/CLKn Source for Port n" "0,1" bitfld.long 0x4 0. "CLKEN,CLK/CLKn Enable for Port n" "0,1" line.long 0x8 "P2CR,OctoSPI IO Manager Port 2 configuration" bitfld.long 0x8 25.--26. "IOHSRC,IOHSRC" "0,1,2,3" bitfld.long 0x8 24. "IOHEN,IOHEN" "0,1" bitfld.long 0x8 17.--18. "IOLSRC,IOLSRC" "0,1,2,3" bitfld.long 0x8 16. "IOLEN,IOLEN" "0,1" bitfld.long 0x8 9. "NCSSRC,NCSSRC" "0,1" bitfld.long 0x8 8. "NCSEN,NCSEN" "0,1" bitfld.long 0x8 5. "DQSSRC,DQSSRC" "0,1" bitfld.long 0x8 4. "DQSEN,DQSEN" "0,1" newline bitfld.long 0x8 1. "CLKSRC,CLKSRC" "0,1" bitfld.long 0x8 0. "CLKEN,CLKEN" "0,1" tree.end endif tree "OPAMP (Operational Amplifiers)" base ad:0x40009000 group.long 0x0++0xB line.long 0x0 "OPAMP1_CSR,OPAMP1 control/status register" bitfld.long 0x0 30. "CALOUT,Operational amplifier calibration" "0,1" bitfld.long 0x0 29. "TSTREF,OPAMP calibration reference voltage" "0,1" bitfld.long 0x0 18. "USERTRIM,User trimming enable" "0,1" hexmask.long.byte 0x0 14.--17. 1. "PGA_GAIN,allows to switch from AOP offset trimmed" bitfld.long 0x0 12.--13. "CALSEL,Calibration selection" "0,1,2,3" bitfld.long 0x0 11. "CALON,Calibration mode enabled" "0,1" bitfld.long 0x0 8. "OPAHSM,Operational amplifier high-speed" "0,1" newline bitfld.long 0x0 5.--6. "VM_SEL,Inverting input selection" "0,1,2,3" bitfld.long 0x0 2.--3. "VP_SEL,Operational amplifier PGA" "0,1,2,3" bitfld.long 0x0 1. "FORCE_VP,Force internal reference on VP (reserved" "0,1" bitfld.long 0x0 0. "OPAEN,Operational amplifier" "0,1" line.long 0x4 "OPAMP1_OTR,OPAMP1 offset trimming register in normal" hexmask.long.byte 0x4 8.--12. 1. "TRIMOFFSETP,Trim for PMOS differential" hexmask.long.byte 0x4 0.--4. 1. "TRIMOFFSETN,Trim for NMOS differential" line.long 0x8 "OPAMP1_HSOTR,OPAMP1 offset trimming register in low-power" hexmask.long.byte 0x8 8.--12. 1. "TRIMLPOFFSETP,Trim for PMOS differential" hexmask.long.byte 0x8 0.--4. 1. "TRIMLPOFFSETN,Trim for NMOS differential" group.long 0x10++0xB line.long 0x0 "OPAMP2_CSR,OPAMP2 control/status register" bitfld.long 0x0 30. "CALOUT,Operational amplifier calibration" "0,1" bitfld.long 0x0 29. "TSTREF,OPAMP calibration reference voltage" "0,1" bitfld.long 0x0 18. "USERTRIM,User trimming enable" "0,1" hexmask.long.byte 0x0 14.--17. 1. "PGA_GAIN,Operational amplifier Programmable" bitfld.long 0x0 12.--13. "CALSEL,Calibration selection" "0,1,2,3" bitfld.long 0x0 11. "CALON,Calibration mode enabled" "0,1" bitfld.long 0x0 8. "OPAHSM,Operational amplifier high-speed" "0,1" newline bitfld.long 0x0 5.--6. "VM_SEL,Inverting input selection" "0,1,2,3" bitfld.long 0x0 1. "FORCE_VP,Force internal reference on VP (reserved" "0,1" bitfld.long 0x0 0. "OPAEN,Operational amplifier" "0,1" line.long 0x4 "OPAMP2_OTR,OPAMP2 offset trimming register in normal" hexmask.long.byte 0x4 8.--12. 1. "TRIMOFFSETP,Trim for PMOS differential" hexmask.long.byte 0x4 0.--4. 1. "TRIMOFFSETN,Trim for NMOS differential" line.long 0x8 "OPAMP2_HSOTR,OPAMP2 offset trimming register in low-power" hexmask.long.byte 0x8 8.--12. 1. "TRIMLPOFFSETP,Trim for PMOS differential" hexmask.long.byte 0x8 0.--4. 1. "TRIMLPOFFSETN,Trim for NMOS differential" tree.end sif (cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "OTFDEC (On-the-fly Decryptor Engine)" base ad:0x0 sif (cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7B0*")) tree "OTFDEC1" base ad:0x5200B800 sif (cpuis("STM32H7B0*")) group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" endif sif (cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x20++0x13 line.long 0x0 "OTFDEC_R1CFGR,OTFDEC region 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R1STARTADDR,OTFDEC region 1 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R1ENDADDR,OTFDEC region 1 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R1NONCER0,OTFDEC region 1 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R1NONCER1,OTFDEC region 1 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0x34++0xF line.long 0x0 "OTFDEC_R1KEYR0,OTFDEC region 1 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R1KEYR1,OTFDEC region 1 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R1KEYR2,OTFDEC region 1 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R1KEYR3,OTFDEC region 1 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" group.long 0x50++0x13 line.long 0x0 "OTFDEC_R2CFGR,OTFDEC region 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R2STARTADDR,OTFDEC region 2 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R2ENDADDR,OTFDEC region 2 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R2NONCER0,OTFDEC region 2 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R2NONCER1,OTFDEC region 2 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0x64++0xF line.long 0x0 "OTFDEC_R2KEYR0,OTFDEC region 2 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R2KEYR1,OTFDEC region 2 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R2KEYR2,OTFDEC region 2 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R2KEYR3,OTFDEC region 2 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" group.long 0x80++0x13 line.long 0x0 "OTFDEC_R3CFGR,OTFDEC region 3 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R3STARTADDR,OTFDEC region 3 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R3ENDADDR,OTFDEC region 3 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R3NONCER0,OTFDEC region 3 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R3NONCER1,OTFDEC region 3 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0x94++0xF line.long 0x0 "OTFDEC_R3KEYR0,OTFDEC region 3 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R3KEYR1,OTFDEC region 3 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R3KEYR2,OTFDEC region 3 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R3KEYR3,OTFDEC region 3 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" group.long 0xB0++0x13 line.long 0x0 "OTFDEC_R4CFGR,OTFDEC region 4 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R4STARTADDR,OTFDEC region 4 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R4ENDADDR,OTFDEC region 4 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R4NONCER0,OTFDEC region 4 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R4NONCER1,OTFDEC region 4 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0xC4++0xF line.long 0x0 "OTFDEC_R4KEYR0,OTFDEC region 4 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R4KEYR1,OTFDEC region 4 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R4KEYR2,OTFDEC region 4 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R4KEYR3,OTFDEC region 4 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" rgroup.long 0x300++0x3 line.long 0x0 "OTFDEC_ISR,OTFDEC interrupt status register" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag status" "0: OTFDEC is operating properly.,1: Read access detected on an enabled encrypted.." bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag status" "0: No execute-only error status. No interrupt..,1: Read access detected on one region with MODE.." newline bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag status" "0: No security error status. No interrupt pending.,1: Security error flag status with interrupt.." wgroup.long 0x304++0x3 line.long 0x0 "OTFDEC_ICR,OTFDEC interrupt clear register" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag clear" "0: KEIF flag status is not affected,1: KEIF flag status is cleared in OTFDEC_ISR register" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag clear" "0: XONEIF flag status is not affected,1: XONEIF flag status is cleared in OTFDEC_ISR.." newline bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag clear" "0: SEIF flag status is not affected,1: SEIF flag status is cleared in OTFDEC_ISR register" group.long 0x308++0x3 line.long 0x0 "OTFDEC_IER,OTFDEC interrupt enable register" bitfld.long 0x0 2. "KEIE,Key Error Interrupt Enable" "0: Interrupt generation on key error flag KEIF is..,1: Interrupt generation on key error flag KEIF is.." bitfld.long 0x0 1. "XONEIE,Execute-only execute-Never Error Interrupt Enable" "0: Interrupt generation on execute-only error..,1: Interrupt generation on execute-only error.." newline bitfld.long 0x0 0. "SEIE,Security Error Interrupt Enable" "0: Interrupt generation on security error SEIF is..,1: Interrupt generation on security error SEIF is.." endif sif (cpuis("STM32H7B0*")) group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif sif (cpuis("STM32H7B0*")) group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif sif (cpuis("STM32H7B0*")) group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif sif (cpuis("STM32H7B0*")) group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" newline bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" newline bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" newline bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" endif tree.end endif sif (cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7B0*")) tree "OTFDEC2" base ad:0x5200BC00 sif (cpuis("STM32H7B0*")) group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" endif sif (cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x20++0x13 line.long 0x0 "OTFDEC_R1CFGR,OTFDEC region 1 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R1STARTADDR,OTFDEC region 1 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R1ENDADDR,OTFDEC region 1 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R1NONCER0,OTFDEC region 1 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R1NONCER1,OTFDEC region 1 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0x34++0xF line.long 0x0 "OTFDEC_R1KEYR0,OTFDEC region 1 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R1KEYR1,OTFDEC region 1 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R1KEYR2,OTFDEC region 1 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R1KEYR3,OTFDEC region 1 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" group.long 0x50++0x13 line.long 0x0 "OTFDEC_R2CFGR,OTFDEC region 2 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R2STARTADDR,OTFDEC region 2 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R2ENDADDR,OTFDEC region 2 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R2NONCER0,OTFDEC region 2 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R2NONCER1,OTFDEC region 2 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0x64++0xF line.long 0x0 "OTFDEC_R2KEYR0,OTFDEC region 2 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R2KEYR1,OTFDEC region 2 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R2KEYR2,OTFDEC region 2 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R2KEYR3,OTFDEC region 2 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" group.long 0x80++0x13 line.long 0x0 "OTFDEC_R3CFGR,OTFDEC region 3 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R3STARTADDR,OTFDEC region 3 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R3ENDADDR,OTFDEC region 3 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R3NONCER0,OTFDEC region 3 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R3NONCER1,OTFDEC region 3 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0x94++0xF line.long 0x0 "OTFDEC_R3KEYR0,OTFDEC region 3 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R3KEYR1,OTFDEC region 3 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R3KEYR2,OTFDEC region 3 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R3KEYR3,OTFDEC region 3 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" group.long 0xB0++0x13 line.long 0x0 "OTFDEC_R4CFGR,OTFDEC region 4 configuration register" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" newline bitfld.long 0x0 4.--5. "MODE,operating mode" "0: Only instruction accesses are decrypted.,1: Only data accesses are decrypted.,2: All read accesses are decrypted (instruction or..,3: Only instruction accesses are decrypted and.." bitfld.long 0x0 2. "KEYLOCK,region key lock" "0: Writes to this region KEYRx registers are allowed.,1: Writes to this region KEYRx registers are.." newline bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0: Writes to this region CFGR1 STARTADDR ENDADDR..,1: Writes to this region CFGR1 STARTADDR ENDADDR.." bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption enable" "0: On-the-fly decryption is disabled for this region.,1: On-the-fly decryption is enabled for this.." line.long 0x4 "OTFDEC_R4STARTADDR,OTFDEC region 4 start address register" hexmask.long 0x4 0.--31. 1. "REGx_START_ADDR,Region AXI start address" line.long 0x8 "OTFDEC_R4ENDADDR,OTFDEC region 4 end address register" hexmask.long 0x8 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0xC "OTFDEC_R4NONCER0,OTFDEC region 4 nonce register 0" hexmask.long 0xC 0.--31. 1. "REGx_NONCE,Region nonce bits [31:0]" line.long 0x10 "OTFDEC_R4NONCER1,OTFDEC region 4 nonce register 1" hexmask.long 0x10 0.--31. 1. "REGx_NONCE,Region nonce bits [63:32]" wgroup.long 0xC4++0xF line.long 0x0 "OTFDEC_R4KEYR0,OTFDEC region 4 key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,Region key bits [31:0]" line.long 0x4 "OTFDEC_R4KEYR1,OTFDEC region 4 key register 1" hexmask.long 0x4 0.--31. 1. "REGx_KEY,Region key bits [63:32]" line.long 0x8 "OTFDEC_R4KEYR2,OTFDEC region 4 key register 2" hexmask.long 0x8 0.--31. 1. "REGx_KEY,Region key bits [95:64]" line.long 0xC "OTFDEC_R4KEYR3,OTFDEC region 4 key register 3" hexmask.long 0xC 0.--31. 1. "REGx_KEY,Region key bits [127:96]" rgroup.long 0x300++0x3 line.long 0x0 "OTFDEC_ISR,OTFDEC interrupt status register" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag status" "0: OTFDEC is operating properly.,1: Read access detected on an enabled encrypted.." bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag status" "0: No execute-only error status. No interrupt..,1: Read access detected on one region with MODE.." newline bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag status" "0: No security error status. No interrupt pending.,1: Security error flag status with interrupt.." wgroup.long 0x304++0x3 line.long 0x0 "OTFDEC_ICR,OTFDEC interrupt clear register" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag clear" "0: KEIF flag status is not affected,1: KEIF flag status is cleared in OTFDEC_ISR register" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error Interrupt Flag clear" "0: XONEIF flag status is not affected,1: XONEIF flag status is cleared in OTFDEC_ISR.." newline bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag clear" "0: SEIF flag status is not affected,1: SEIF flag status is cleared in OTFDEC_ISR register" group.long 0x308++0x3 line.long 0x0 "OTFDEC_IER,OTFDEC interrupt enable register" bitfld.long 0x0 2. "KEIE,Key Error Interrupt Enable" "0: Interrupt generation on key error flag KEIF is..,1: Interrupt generation on key error flag KEIF is.." bitfld.long 0x0 1. "XONEIE,Execute-only execute-Never Error Interrupt Enable" "0: Interrupt generation on execute-only error..,1: Interrupt generation on execute-only error.." newline bitfld.long 0x0 0. "SEIE,Security Error Interrupt Enable" "0: Interrupt generation on security error SEIF is..,1: Interrupt generation on security error SEIF is.." endif sif (cpuis("STM32H7B0*")) group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" endif sif (cpuis("STM32H7B0*")) group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" endif sif (cpuis("STM32H7B0*")) group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif sif (cpuis("STM32H7B0*")) group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" endif sif (cpuis("STM32H7B0*")) wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" newline bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" newline bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" newline bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" endif tree.end endif sif (cpuis("STM32H7B3*")) tree "OTFDEC1" base ad:0x5200B800 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end tree "OTFDEC2" base ad:0x5200BC00 group.long 0x0++0x3 line.long 0x0 "CR,OTFDEC control register" bitfld.long 0x0 0. "ENC,Encryption mode bit" "0,1" group.long 0x20++0x3 line.long 0x0 "R1CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x50++0x3 line.long 0x0 "R2CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x80++0x3 line.long 0x0 "R3CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0xB0++0x3 line.long 0x0 "R4CFGR,OTFDEC region x configuration" hexmask.long.word 0x0 16.--31. 1. "REGx_VERSION,region firmware version" hexmask.long.byte 0x0 8.--15. 1. "KEYCRC,region key 8-bit CRC" bitfld.long 0x0 4.--5. "MODE,operating mode" "0,1,2,3" bitfld.long 0x0 2. "KEYLOCK,region key lock" "0,1" bitfld.long 0x0 1. "CONFIGLOCK,region config lock" "0,1" bitfld.long 0x0 0. "REG_EN,region on-the-fly decryption" "0,1" group.long 0x24++0x3 line.long 0x0 "R1STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x54++0x3 line.long 0x0 "R2STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x84++0x3 line.long 0x0 "R3STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0xB4++0x3 line.long 0x0 "R4STARTADDR,OTFDEC region x start address" hexmask.long 0x0 0.--31. 1. "REGx_START_ADDR,Region AXI start address" group.long 0x28++0x3 line.long 0x0 "R1ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x58++0x3 line.long 0x0 "R2ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x88++0x7 line.long 0x0 "R3ENDADDR,OTFDEC region x end address" hexmask.long 0x0 0.--31. 1. "REGx_END_ADDR,Region AXI end address" line.long 0x4 "R4ENDADDR,OTFDEC region x end address" hexmask.long 0x4 0.--31. 1. "REGx_END_ADDR,Region AXI end address" group.long 0x2C++0x3 line.long 0x0 "R1NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x5C++0x3 line.long 0x0 "R2NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x8C++0x3 line.long 0x0 "R3NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xBC++0x3 line.long 0x0 "R4NONCER0,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0x30++0x3 line.long 0x0 "R1NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce" group.long 0x60++0x3 line.long 0x0 "R2NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,Region nonce bits" group.long 0x90++0x3 line.long 0x0 "R3NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" group.long 0xC0++0x3 line.long 0x0 "R4NONCER1,OTFDEC region x nonce register" hexmask.long 0x0 0.--31. 1. "REGx_NONCE,REGx_NONCE" wgroup.long 0x34++0x3 line.long 0x0 "R1KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x64++0x3 line.long 0x0 "R2KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x94++0x3 line.long 0x0 "R3KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC4++0x3 line.long 0x0 "R4KEYR0,OTFDEC region x key register 0" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x38++0x3 line.long 0x0 "R1KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x68++0x3 line.long 0x0 "R2KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x98++0x3 line.long 0x0 "R3KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xC8++0x3 line.long 0x0 "R4KEYR1,OTFDEC region x key register 1" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x3C++0x3 line.long 0x0 "R1KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x6C++0x3 line.long 0x0 "R2KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY_,REGx_KEY" wgroup.long 0x9C++0x3 line.long 0x0 "R3KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xCC++0x3 line.long 0x0 "R4KEYR2,OTFDEC region x key register 2" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x40++0x3 line.long 0x0 "R1KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0x70++0x3 line.long 0x0 "R2KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xA0++0x3 line.long 0x0 "R3KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" wgroup.long 0xD0++0x3 line.long 0x0 "R4KEYR3,OTFDEC region x key register 3" hexmask.long 0x0 0.--31. 1. "REGx_KEY,REGx_KEY" rgroup.long 0x300++0x7 line.long 0x0 "ISR,OTFDEC interrupt status" bitfld.long 0x0 2. "KEIF,Key Error Interrupt Flag" "0,1" bitfld.long 0x0 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x0 0. "SEIF,Security Error Interrupt Flag" "0,1" line.long 0x4 "ICR,OTFDEC interrupt clear" bitfld.long 0x4 2. "KEIF,KEIF" "0,1" bitfld.long 0x4 1. "XONEIF,Execute-only execute-Never Error" "0,1" bitfld.long 0x4 0. "SEIF,SEIF" "0,1" group.long 0x308++0x3 line.long 0x0 "IER,OTFDEC interrupt enable" bitfld.long 0x0 2. "KEIE,KEIE" "0,1" bitfld.long 0x0 1. "XONEIE,XONEIE" "0,1" bitfld.long 0x0 0. "SEIE,Security Error Interrupt" "0,1" tree.end endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "PSSI (Parallel Synchronous Slave Interface)" base ad:0x48020400 group.long 0x0++0x3 line.long 0x0 "PSSI_CR,PSSI control register" bitfld.long 0x0 31. "OUTEN,Data direction selection bit" "0: Receive mode: data is input synchronously with..,1: Transmit mode: data is output synchronously with.." bitfld.long 0x0 30. "DMAEN,DMA enable bit" "0: DMA transfers are disabled. The user application..,1: DMA transfers are enabled (default.." newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H7A3*")) bitfld.long 0x0 18.--20. "DERDYCFG,Data enable and ready configuration" "0: PSSI_DE and PSSI_RDY both disabled,1: Only PSSI_RDY enabled,2: Only PSSI_DE enabled,3: Both PSSI_RDY and PSSI_DE alternate functions..,4: Both PSSI_RDY and PSSI_DE features enabled -..,5: Only PSSI_RDY function enabled but mapped to..,6: Only PSSI_DE function enabled but mapped to..,7: Both PSSI_RDY and PSSI_DE features enabled -.." endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 18.--21. 1. "DERDYCFG,Data enable and ready configuration" newline endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 18.--21. 1. "DERDYCFG,Data enable and ready configuration" endif bitfld.long 0x0 14. "ENABLE,PSSI enable" "0: PSSI disabled,1: PSSI enabled" newline bitfld.long 0x0 10.--11. "EDM,Extended data mode" "0: Interface captures 8-bit data on every parallel..,1: Reserved must not be selected,2: Reserved must not be selected,3: The interface captures 16-bit data on every.." bitfld.long 0x0 8. "RDYPOL,Ready (PSSI_RDY) polarity" "0: PSSI_RDY active low (0 indicates that the..,1: PSSI_RDY active high (1 indicates that the.." newline bitfld.long 0x0 6. "DEPOL,Data enable (PSSI_DE) polarity" "0: PSSI_DE active low (0 indicates that data is..,1: PSSI_DE active high (1 indicates that data is.." bitfld.long 0x0 5. "CKPOL,Parallel data clock polarity" "0: Falling edge active for inputs or rising edge..,1: Rising edge active for inputs or falling edge.." rgroup.long 0x4++0x7 line.long 0x0 "PSSI_SR,PSSI status register" bitfld.long 0x0 3. "RTT1B,FIFO is ready to transfer one byte" "0: FIFO is not ready for a 1-byte transfer,1: FIFO is ready for a one byte (32-bit) transfer." bitfld.long 0x0 2. "RTT4B,FIFO is ready to transfer four bytes" "0: FIFO is not ready for a four-byte transfer,1: FIFO is ready for a four-byte (32-bit) transfer." line.long 0x4 "PSSI_RIS,PSSI raw interrupt status register" bitfld.long 0x4 1. "OVR_RIS,Data buffer overrun/underrun raw interrupt status" "0: No overrun/underrun occurred,1: An overrun/underrun occurred: overrun in receive.." group.long 0xC++0x3 line.long 0x0 "PSSI_IER,PSSI interrupt enable register" bitfld.long 0x0 1. "OVR_IE,Data buffer overrun/underrun interrupt enable" "0: No interrupt generation,1: An interrupt is generated if either an overrun.." rgroup.long 0x10++0x3 line.long 0x0 "PSSI_MIS,PSSI masked interrupt status register" bitfld.long 0x0 1. "OVR_MIS,Data buffer overrun/underrun masked interrupt status" "0: No interrupt is generated when an..,1: An interrupt is generated if there is either an.." wgroup.long 0x14++0x3 line.long 0x0 "PSSI_ICR,PSSI interrupt clear register" bitfld.long 0x0 1. "OVR_ISC,Data buffer overrun/underrun interrupt status clear" "0,1" group.long 0x28++0x3 line.long 0x0 "PSSI_DR,PSSI data register" hexmask.long.byte 0x0 24.--31. 1. "BYTE3,Data byte 3" hexmask.long.byte 0x0 16.--23. 1. "BYTE2,Data byte 2" newline hexmask.long.byte 0x0 8.--15. 1. "BYTE1,Data byte 1" hexmask.long.byte 0x0 0.--7. 1. "BYTE0,Data byte 0" tree.end endif tree "PWR (Power Control)" base ad:0x58024800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR1,PWR control register 1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CSR1,PWR control status register 1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" newline bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 21. "VBATH,VBAT level monitoring versus high" "0,1" rbitfld.long 0x0 20. "VBATL,VBAT level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" newline endif bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x4 2. "SCUEN,SD converter Enable" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x4 2. "SCUEN,SD converter Enable" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline endif bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_D3,Keep system D3 domain in Run mode" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 8. "SBF_D2,D2 domain DStandby flag This bit is set" "0,1" rbitfld.long 0x8 7. "SBF_D1,D1 domain DStandby flag This bit is set" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_D3,System D3 domain Power Down Deepsleep." "0,1" bitfld.long 0x8 1. "PDDS_D2,D2 domain Power Down Deepsleep. This bit" "0,1" newline bitfld.long 0x8 0. "PDDS_D1,D1 domain Power Down Deepsleep" "0,1" group.long 0x18++0x3 line.long 0x0 "D3CR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "WKUPCR,reset only by system reset. not reset by" hexmask.long.byte 0x0 0.--5. 1. "WKUPC,Clear Wakeup pin flag for WKUP. These" line.long 0x4 "WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H750*")) group.long 0x0++0x3 line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "PWR_CSR1,PWR control status register 1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" newline bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "PWR_CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 21. "VBATH,VBAT level monitoring versus high" "0,1" rbitfld.long 0x0 20. "VBATL,VBAT level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "PWR_CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" newline bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "PWR_CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_D3,Keep system D3 domain in Run mode" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 8. "SBF_D2,D2 domain DStandby flag This bit is set" "0,1" rbitfld.long 0x8 7. "SBF_D1,D1 domain DStandby flag This bit is set" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_D3,System D3 domain Power Down Deepsleep." "0,1" bitfld.long 0x8 1. "PDDS_D2,D2 domain Power Down Deepsleep. This bit" "0,1" newline bitfld.long 0x8 0. "PDDS_D1,D1 domain Power Down Deepsleep" "0,1" group.long 0x18++0x3 line.long 0x0 "PWR_D3CR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "PWR_WKUPCR,reset only by system reset. not reset by" hexmask.long.byte 0x0 0.--5. 1. "WKUPC,Clear Wakeup pin flag for WKUP. These" line.long 0x4 "PWR_WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "PWR_WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H753*")) group.long 0x0++0x3 line.long 0x0 "CR1,PWR control register 1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CSR1,PWR control status register 1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" newline bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 21. "VBATH,VBAT level monitoring versus high" "0,1" rbitfld.long 0x0 20. "VBATL,VBAT level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" newline bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" bitfld.long 0x4 2. "SCUEN,SD converter Enable" "0,1" newline bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_D3,Keep system D3 domain in Run mode" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 8. "SBF_D2,D2 domain DStandby flag This bit is set" "0,1" rbitfld.long 0x8 7. "SBF_D1,D1 domain DStandby flag This bit is set" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_D3,System D3 domain Power Down Deepsleep." "0,1" bitfld.long 0x8 1. "PDDS_D2,D2 domain Power Down Deepsleep. This bit" "0,1" newline bitfld.long 0x8 0. "PDDS_D1,D1 domain Power Down Deepsleep" "0,1" group.long 0x18++0x3 line.long 0x0 "D3CR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "WKUPCR,reset only by system reset. not reset by" hexmask.long.byte 0x0 0.--5. 1. "WKUPC,Clear Wakeup pin flag for WKUP. These" line.long 0x4 "WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x3 line.long 0x0 "CR1,PWR control register 1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CSR1,PWR control status register 1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" newline bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 21. "VBATH,VBAT level monitoring versus high" "0,1" rbitfld.long 0x0 20. "VBATL,VBAT level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" newline bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_D3,Keep system D3 domain in Run mode" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 8. "SBF_D2,D2 domain DStandby flag This bit is set" "0,1" rbitfld.long 0x8 7. "SBF_D1,D1 domain DStandby flag This bit is set" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_D3,System D3 domain Power Down Deepsleep." "0,1" bitfld.long 0x8 1. "PDDS_D2,D2 domain Power Down Deepsleep. This bit" "0,1" newline bitfld.long 0x8 0. "PDDS_D1,D1 domain Power Down Deepsleep" "0,1" group.long 0x18++0x3 line.long 0x0 "D3CR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "WKUPCR,reset only by system reset. not reset by" hexmask.long.byte 0x0 0.--5. 1. "WKUPC,Clear Wakeup pin flag for WKUP. These" line.long 0x4 "WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR1,PWR control register 1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CSR1,PWR control status register 1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" newline bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 21. "VBATH,VBAT level monitoring versus high" "0,1" rbitfld.long 0x0 20. "VBATL,VBAT level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" newline bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_D3,Keep system D3 domain in Run mode" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 8. "SBF_D2,D2 domain DStandby flag This bit is set" "0,1" rbitfld.long 0x8 7. "SBF_D1,D1 domain DStandby flag This bit is set" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_D3,System D3 domain Power Down Deepsleep." "0,1" bitfld.long 0x8 1. "PDDS_D2,D2 domain Power Down Deepsleep. This bit" "0,1" newline bitfld.long 0x8 0. "PDDS_D1,D1 domain Power Down Deepsleep" "0,1" group.long 0x18++0x3 line.long 0x0 "D3CR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "WKUPCR,reset only by system reset. not reset by" hexmask.long.byte 0x0 0.--5. 1. "WKUPC,Clear Wakeup pin flag for WKUP. These" line.long 0x4 "WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x3 line.long 0x0 "CR1,PWR control register 1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CSR1,PWR control status register 1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" newline bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 21. "VBATH,VBAT level monitoring versus high" "0,1" rbitfld.long 0x0 20. "VBATL,VBAT level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" newline bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_D3,Keep system D3 domain in Run mode" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 8. "SBF_D2,D2 domain DStandby flag This bit is set" "0,1" rbitfld.long 0x8 7. "SBF_D1,D1 domain DStandby flag This bit is set" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_D3,System D3 domain Power Down Deepsleep." "0,1" bitfld.long 0x8 1. "PDDS_D2,D2 domain Power Down Deepsleep. This bit" "0,1" newline bitfld.long 0x8 0. "PDDS_D1,D1 domain Power Down Deepsleep" "0,1" group.long 0x18++0x3 line.long 0x0 "D3CR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "WKUPCR,reset only by system reset. not reset by" hexmask.long.byte 0x0 0.--5. 1. "WKUPC,Clear Wakeup pin flag for WKUP. These" line.long 0x4 "WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR1,PWR control register 1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" newline bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "CSR1,PWR control status register 1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" newline bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 21. "VBATH,VBAT level monitoring versus high" "0,1" rbitfld.long 0x0 20. "VBATL,VBAT level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" newline bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" bitfld.long 0x4 2. "SDEN,SD converter Enable" "0,1" newline bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_D3,Keep system D3 domain in Run mode" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 8. "SBF_D2,D2 domain DStandby flag This bit is set" "0,1" rbitfld.long 0x8 7. "SBF_D1,D1 domain DStandby flag This bit is set" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_D3,System D3 domain Power Down Deepsleep." "0,1" bitfld.long 0x8 1. "PDDS_D2,D2 domain Power Down Deepsleep. This bit" "0,1" newline bitfld.long 0x8 0. "PDDS_D1,D1 domain Power Down Deepsleep" "0,1" group.long 0x18++0x3 line.long 0x0 "D3CR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "WKUPCR,reset only by system reset. not reset by" hexmask.long.byte 0x0 0.--5. 1. "WKUPC,Clear Wakeup pin flag for WKUP. These" line.long 0x4 "WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x3 line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 27. "SRDRAMSO,SRDRAMSO" "0,1" bitfld.long 0x0 26. "HSITFSO,HSITFSO" "0,1" newline bitfld.long 0x0 25. "GFXSO,GFXSO" "0,1" bitfld.long 0x0 24. "ITCMSO,ITCMSO" "0,1" newline bitfld.long 0x0 23. "AHBRAM2SO,AHBRAM2SO" "0,1" bitfld.long 0x0 22. "AHBRAM1SO,AHBRAM1SO" "0,1" newline bitfld.long 0x0 21. "AXIRAM3SO,AXIRAM3SO" "0,1" bitfld.long 0x0 20. "AXIRAM2SO,AXIRAM2SO" "0,1" newline bitfld.long 0x0 19. "AXIRAM1SO,AXIRAM1SO" "0,1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" newline bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" newline bitfld.long 0x0 13. "AVD_READY,AVD_READY" "0,1" bitfld.long 0x0 12. "BOOSTE,BOOSTE" "0,1" newline bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" newline bitfld.long 0x0 5.--7. "PLS,Programmable voltage detector level" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" newline bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "PWR_CSR1,PWR control status register 1" bitfld.long 0x0 17. "MMCVDO,MMCVDO" "0,1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" newline bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "PWR_CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "PWR_CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" rbitfld.long 0x4 16. "SMPSEXTRDY,SMPSEXTRDY" "0,1" newline bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" newline bitfld.long 0x4 4.--5. "SMPSLEVEL,SMPSLEVEL" "0,1,2,3" bitfld.long 0x4 3. "SMPSEXTHP,SMPSEXTHP" "0,1" newline bitfld.long 0x4 2. "SMPSEN,SMPSEN" "0,1" bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" newline bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "PWR_CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_SRD,RUN_SRD" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_SRD,PDDS_SRD" "0,1" bitfld.long 0x8 0. "RETDS_CD,RETDS_CD" "0,1" group.long 0x18++0x3 line.long 0x0 "PWR_SRDCR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "PWR_WKUPCR,reset only by system reset. not reset by" bitfld.long 0x0 5. "WKUPC6,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 4. "WKUPC5,Clear Wakeup pin flag for WKUP. These" "0,1" newline bitfld.long 0x0 3. "WKUPC4,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 2. "WKUPC3,Clear Wakeup pin flag for WKUP. These" "0,1" newline bitfld.long 0x0 1. "WKUPC2,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 0. "WKUPC1,Clear Wakeup pin flag for WKUP. These" "0,1" line.long 0x4 "PWR_WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "PWR_WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x3 line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 27. "SRDRAMSO,SRDRAMSO" "0,1" bitfld.long 0x0 26. "HSITFSO,HSITFSO" "0,1" newline bitfld.long 0x0 25. "GFXSO,GFXSO" "0,1" bitfld.long 0x0 24. "ITCMSO,ITCMSO" "0,1" newline bitfld.long 0x0 23. "AHBRAM2SO,AHBRAM2SO" "0,1" bitfld.long 0x0 22. "AHBRAM1SO,AHBRAM1SO" "0,1" newline bitfld.long 0x0 21. "AXIRAM3SO,AXIRAM3SO" "0,1" bitfld.long 0x0 20. "AXIRAM2SO,AXIRAM2SO" "0,1" newline bitfld.long 0x0 19. "AXIRAM1SO,AXIRAM1SO" "0,1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" newline bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" newline bitfld.long 0x0 13. "AVD_READY,AVD_READY" "0,1" bitfld.long 0x0 12. "BOOSTE,BOOSTE" "0,1" newline bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" newline hexmask.long.byte 0x0 5.--8. 1. "PLS,Programmable voltage detector level" bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" newline bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "PWR_CSR1,PWR control status register 1" bitfld.long 0x0 17. "MMCVDO,MMCVDO" "0,1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" newline bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "PWR_CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "PWR_CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" rbitfld.long 0x4 16. "SMPSEXTRDY,SMPSEXTRDY" "0,1" newline bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" newline bitfld.long 0x4 4.--5. "SMPSLEVEL,SMPSLEVEL" "0,1,2,3" bitfld.long 0x4 3. "SMPSEXTHP,SMPSEXTHP" "0,1" newline bitfld.long 0x4 2. "SMPSEN,SMPSEN" "0,1" bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" newline bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "PWR_CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_SRD,RUN_SRD" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_SRD,PDDS_SRD" "0,1" bitfld.long 0x8 0. "RETDS_CD,RETDS_CD" "0,1" group.long 0x18++0x3 line.long 0x0 "PWR_SRDCR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "PWR_WKUPCR,reset only by system reset. not reset by" bitfld.long 0x0 5. "WKUPC6,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 4. "WKUPC5,Clear Wakeup pin flag for WKUP. These" "0,1" newline bitfld.long 0x0 3. "WKUPC4,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 2. "WKUPC3,Clear Wakeup pin flag for WKUP. These" "0,1" newline bitfld.long 0x0 1. "WKUPC2,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 0. "WKUPC1,Clear Wakeup pin flag for WKUP. These" "0,1" line.long 0x4 "PWR_WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "PWR_WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x3 line.long 0x0 "PWR_CR1,PWR control register 1" bitfld.long 0x0 27. "SRDRAMSO,SRDRAMSO" "0,1" bitfld.long 0x0 26. "HSITFSO,HSITFSO" "0,1" newline bitfld.long 0x0 25. "GFXSO,GFXSO" "0,1" bitfld.long 0x0 24. "ITCMSO,ITCMSO" "0,1" newline bitfld.long 0x0 23. "AHBRAM2SO,AHBRAM2SO" "0,1" bitfld.long 0x0 22. "AHBRAM1SO,AHBRAM1SO" "0,1" newline bitfld.long 0x0 21. "AXIRAM3SO,AXIRAM3SO" "0,1" bitfld.long 0x0 20. "AXIRAM2SO,AXIRAM2SO" "0,1" newline bitfld.long 0x0 19. "AXIRAM1SO,AXIRAM1SO" "0,1" bitfld.long 0x0 17.--18. "ALS,Analog voltage detector level selection" "0,1,2,3" newline bitfld.long 0x0 16. "AVDEN,Peripheral voltage monitor on VDDA" "0,1" bitfld.long 0x0 14.--15. "SVOS,System Stop mode voltage scaling" "0,1,2,3" newline bitfld.long 0x0 13. "AVD_READY,AVD_READY" "0,1" bitfld.long 0x0 12. "BOOSTE,BOOSTE" "0,1" newline bitfld.long 0x0 9. "FLPS,Flash low-power mode in DStop mode This" "0,1" bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0,1" newline hexmask.long.byte 0x0 5.--8. 1. "PLS,Programmable voltage detector level" bitfld.long 0x0 4. "PVDE,Programmable voltage detector" "0,1" newline bitfld.long 0x0 0. "LPDS,Low-power Deepsleep with SVOS3 (SVOS4" "0,1" rgroup.long 0x4++0x3 line.long 0x0 "PWR_CSR1,PWR control status register 1" bitfld.long 0x0 17. "MMCVDO,MMCVDO" "0,1" bitfld.long 0x0 16. "AVDO,Analog voltage detector output on VDDA" "0,1" newline bitfld.long 0x0 14.--15. "ACTVOS,VOS currently applied for VCORE voltage" "0,1,2,3" bitfld.long 0x0 13. "ACTVOSRDY,Voltage levels ready bit for currently" "0,1" newline bitfld.long 0x0 4. "PVDO,Programmable voltage detect output This" "0,1" group.long 0x8++0xB line.long 0x0 "PWR_CR2,This register is not reset by wakeup from" rbitfld.long 0x0 23. "TEMPH,Temperature level monitoring versus high" "0,1" rbitfld.long 0x0 22. "TEMPL,Temperature level monitoring versus low" "0,1" newline rbitfld.long 0x0 16. "BRRDY,Backup regulator ready This bit is set" "0,1" bitfld.long 0x0 4. "MONEN,VBAT and temperature monitoring enable" "0,1" newline bitfld.long 0x0 0. "BREN,Backup regulator enable When set the" "0,1" line.long 0x4 "PWR_CR3,Reset only by POR only. not reset by wakeup" rbitfld.long 0x4 26. "USB33RDY,USB supply ready." "0,1" bitfld.long 0x4 25. "USBREGEN,USB regulator enable." "0,1" newline bitfld.long 0x4 24. "USB33DEN,VDD33USB voltage level detector" "0,1" rbitfld.long 0x4 16. "SMPSEXTRDY,SMPSEXTRDY" "0,1" newline bitfld.long 0x4 9. "VBRS,VBAT charging resistor" "0,1" bitfld.long 0x4 8. "VBE,VBAT charging enable" "0,1" newline bitfld.long 0x4 4.--5. "SMPSLEVEL,SMPSLEVEL" "0,1,2,3" bitfld.long 0x4 3. "SMPSEXTHP,SMPSEXTHP" "0,1" newline bitfld.long 0x4 2. "SMPSEN,SMPSEN" "0,1" bitfld.long 0x4 1. "LDOEN,Low drop-out regulator" "0,1" newline bitfld.long 0x4 0. "BYPASS,Power management unit" "0,1" line.long 0x8 "PWR_CPUCR,This register allows controlling CPU1" bitfld.long 0x8 11. "RUN_SRD,RUN_SRD" "0,1" bitfld.long 0x8 9. "CSSF,Clear D1 domain CPU1 Standby Stop and" "0,1" newline rbitfld.long 0x8 6. "SBF,System Standby flag This bit is set by" "0,1" rbitfld.long 0x8 5. "STOPF,STOP flag This bit is set by hardware" "0,1" newline bitfld.long 0x8 2. "PDDS_SRD,PDDS_SRD" "0,1" bitfld.long 0x8 0. "RETDS_CD,RETDS_CD" "0,1" group.long 0x18++0x3 line.long 0x0 "PWR_SRDCR,This register allows controlling D3 domain" bitfld.long 0x0 14.--15. "VOS,Voltage scaling selection according to" "0,1,2,3" rbitfld.long 0x0 13. "VOSRDY,VOS Ready bit for VCORE voltage scaling" "0,1" group.long 0x20++0xB line.long 0x0 "PWR_WKUPCR,reset only by system reset. not reset by" bitfld.long 0x0 5. "WKUPC6,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 4. "WKUPC5,Clear Wakeup pin flag for WKUP. These" "0,1" newline bitfld.long 0x0 3. "WKUPC4,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 2. "WKUPC3,Clear Wakeup pin flag for WKUP. These" "0,1" newline bitfld.long 0x0 1. "WKUPC2,Clear Wakeup pin flag for WKUP. These" "0,1" bitfld.long 0x0 0. "WKUPC1,Clear Wakeup pin flag for WKUP. These" "0,1" line.long 0x4 "PWR_WKUPFR,reset only by system reset. not reset by" bitfld.long 0x4 5. "WKUPF6,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 4. "WKUPF5,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 3. "WKUPF4,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 2. "WKUPF3,Wakeup pin WKUPF flag. This bit is set" "0,1" newline bitfld.long 0x4 1. "WKUPF2,Wakeup pin WKUPF flag. This bit is set" "0,1" bitfld.long 0x4 0. "WKUPF1,Wakeup pin WKUPF flag. This bit is set" "0,1" line.long 0x8 "PWR_WKUPEPR,Reset only by system reset. not reset by" bitfld.long 0x8 26.--27. "WKUPPUPD6,Wakeup pin pull configuration for" "0,1,2,3" bitfld.long 0x8 24.--25. "WKUPPUPD5,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 22.--23. "WKUPPUPD4,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 20.--21. "WKUPPUPD3,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 18.--19. "WKUPPUPD2,Wakeup pin pull" "0,1,2,3" bitfld.long 0x8 16.--17. "WKUPPUPD1,Wakeup pin pull" "0,1,2,3" newline bitfld.long 0x8 13. "WKUPP6,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 12. "WKUPP5,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 11. "WKUPP4,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 10. "WKUPP3,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 9. "WKUPP2,Wakeup pin polarity bit for WKUPn-7" "0,1" bitfld.long 0x8 8. "WKUPP1,Wakeup pin polarity bit for WKUPn-7" "0,1" newline bitfld.long 0x8 5. "WKUPEN6,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 4. "WKUPEN5,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 3. "WKUPEN4,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 2. "WKUPEN3,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" newline bitfld.long 0x8 1. "WKUPEN2,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" bitfld.long 0x8 0. "WKUPEN1,Enable Wakeup Pin WKUPn+1 Each bit is" "0,1" endif tree.end sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "QUADSPI (Quad-SPI Interface)" base ad:0x52005000 sif (cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,clock prescaler" bitfld.long 0x0 23. "PMM,Polling match mode This bit indicates" "0,1" newline bitfld.long 0x0 22. "APMS,Automatic poll mode stop This bit" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable This bit" "0,1" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable This bit" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable This bit" "0,1" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable This bit" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level Defines in" bitfld.long 0x0 7. "FSEL,Flash memory selection This bit selects" "0,1" newline bitfld.long 0x0 6. "DFM,Dual-flash mode This bit activates" "0,1" bitfld.long 0x0 4. "SSHIFT,Sample shift By default the QUADSPI" "0,1" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable This bit is valid" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable In indirect mode DMA can be" "0,1" newline bitfld.long 0x0 1. "ABORT,Abort request This bit aborts the" "0,1" bitfld.long 0x0 0. "EN,Enable Enable the QUADSPI." "0,1" line.long 0x4 "DCR,QUADSPI device configuration" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,Flash memory size This field defines the" bitfld.long 0x4 8.--10. "CSHT,Chip select high time CSHT+1 defines the" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CKMODE,indicates the level that clk takes" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SR,QUADSPI status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level This field gives the number" bitfld.long 0x0 5. "BUSY,Busy This bit is set when an operation" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag This bit is set when" "0,1" bitfld.long 0x0 3. "SMF,Status match flag This bit is set in" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag In indirect mode " "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag This bit is set" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag This bit is set in" "0,1" group.long 0xC++0x27 line.long 0x0 "FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag Writing 1 clears the" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag Writing 1 clears" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag Writing 1" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag Writing 1" "0,1" line.long 0x4 "DLR,QUADSPI data length register" hexmask.long 0x4 0.--31. 1. "DL,Data length Number of data to be" line.long 0x8 "CCR,QUADSPI communication configuration" bitfld.long 0x8 31. "DDRM,Double data rate mode This bit sets the" "0,1" bitfld.long 0x8 30. "DHHC,DDR hold Delay the data output by 1/4 of" "0,1" newline bitfld.long 0x8 28. "SIOO,Send instruction only once mode See" "?,?" bitfld.long 0x8 26.--27. "FMODE,Functional mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 24.--25. "DMODE,Data mode This field defines the data" "0,1,2,3" hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles This field" newline bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size This bit defines" "0,1,2,3" bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode This field defines" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADSIZE,Address size This bit defines address" "0,1,2,3" bitfld.long 0x8 10.--11. "ADMODE,Address mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 8.--9. "IMODE,Instruction mode This field defines the" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction Instruction to be send to" line.long 0xC "AR,QUADSPI address register" hexmask.long 0xC 0.--31. 1. "ADDRESS,[31 0]: Address Address to be send to" line.long 0x10 "ABR,QUADSPI alternate bytes" hexmask.long 0x10 0.--31. 1. "ALTERNATE,Alternate Bytes Optional data to be send" line.long 0x14 "DR,QUADSPI data register" hexmask.long 0x14 0.--31. 1. "DATA,Data Data to be sent/received to/from" line.long 0x18 "PSMKR,QUADSPI polling status mask" hexmask.long 0x18 0.--31. 1. "MASK,Status mask Mask to be applied to the" line.long 0x1C "PSMAR,QUADSPI polling status match" hexmask.long 0x1C 0.--31. 1. "MATCH,Status match Value to be compared with" line.long 0x20 "PIR,QUADSPI polling interval" hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval Number of CLK cycles" line.long 0x24 "LPTR,QUADSPI low-power timeout" hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period After each access in" endif sif (cpuis("STM32H750*")) group.long 0x0++0x7 line.long 0x0 "QUADSPI_CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,clock prescaler" bitfld.long 0x0 23. "PMM,Polling match mode This bit indicates" "0,1" newline bitfld.long 0x0 22. "APMS,Automatic poll mode stop This bit" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable This bit" "0,1" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable This bit" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable This bit" "0,1" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable This bit" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level Defines in" bitfld.long 0x0 7. "FSEL,Flash memory selection This bit selects" "0,1" newline bitfld.long 0x0 6. "DFM,Dual-flash mode This bit activates" "0,1" bitfld.long 0x0 4. "SSHIFT,Sample shift By default the QUADSPI" "0,1" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable This bit is valid" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable In indirect mode DMA can be" "0,1" newline bitfld.long 0x0 1. "ABORT,Abort request This bit aborts the" "0,1" bitfld.long 0x0 0. "EN,Enable Enable the QUADSPI." "0,1" line.long 0x4 "QUADSPI_DCR,QUADSPI device configuration" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,Flash memory size This field defines the" bitfld.long 0x4 8.--10. "CSHT,Chip select high time CSHT+1 defines the" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CKMODE,indicates the level that clk takes" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "QUADSPI_SR,QUADSPI status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level This field gives the number" bitfld.long 0x0 5. "BUSY,Busy This bit is set when an operation" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag This bit is set when" "0,1" bitfld.long 0x0 3. "SMF,Status match flag This bit is set in" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag In indirect mode " "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag This bit is set" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag This bit is set in" "0,1" group.long 0xC++0x27 line.long 0x0 "QUADSPI_FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag Writing 1 clears the" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag Writing 1 clears" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag Writing 1" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag Writing 1" "0,1" line.long 0x4 "QUADSPI_DLR,QUADSPI data length register" hexmask.long 0x4 0.--31. 1. "DL,Data length Number of data to be" line.long 0x8 "QUADSPI_CCR,QUADSPI communication configuration" bitfld.long 0x8 31. "DDRM,Double data rate mode This bit sets the" "0,1" bitfld.long 0x8 30. "DHHC,DDR hold Delay the data output by 1/4 of" "0,1" newline bitfld.long 0x8 28. "SIOO,Send instruction only once mode See" "?,?" bitfld.long 0x8 26.--27. "FMODE,Functional mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 24.--25. "DMODE,Data mode This field defines the data" "0,1,2,3" hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles This field" newline bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size This bit defines" "0,1,2,3" bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode This field defines" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADSIZE,Address size This bit defines address" "0,1,2,3" bitfld.long 0x8 10.--11. "ADMODE,Address mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 8.--9. "IMODE,Instruction mode This field defines the" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction Instruction to be send to" line.long 0xC "QUADSPI_AR,QUADSPI address register" hexmask.long 0xC 0.--31. 1. "ADDRESS,[31 0]: Address Address to be send to" line.long 0x10 "QUADSPI_ABR,QUADSPI alternate bytes" hexmask.long 0x10 0.--31. 1. "ALTERNATE,Alternate Bytes Optional data to be send" line.long 0x14 "QUADSPI_DR,QUADSPI data register" hexmask.long 0x14 0.--31. 1. "DATA,Data Data to be sent/received to/from" line.long 0x18 "QUADSPI_PSMKR,QUADSPI polling status mask" hexmask.long 0x18 0.--31. 1. "MASK,Status mask Mask to be applied to the" line.long 0x1C "QUADSPI_PSMAR,QUADSPI polling status match" hexmask.long 0x1C 0.--31. 1. "MATCH,Status match Value to be compared with" line.long 0x20 "QUADSPI_PIR,QUADSPI polling interval" hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval Number of CLK cycles" line.long 0x24 "QUADSPI_LPTR,QUADSPI low-power timeout" hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period After each access in" endif sif (cpuis("STM32H753*")) group.long 0x0++0x7 line.long 0x0 "CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,clock prescaler" bitfld.long 0x0 23. "PMM,Polling match mode This bit indicates" "0,1" newline bitfld.long 0x0 22. "APMS,Automatic poll mode stop This bit" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable This bit" "0,1" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable This bit" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable This bit" "0,1" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable This bit" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level Defines in" bitfld.long 0x0 7. "FSEL,Flash memory selection This bit selects" "0,1" newline bitfld.long 0x0 6. "DFM,Dual-flash mode This bit activates" "0,1" bitfld.long 0x0 4. "SSHIFT,Sample shift By default the QUADSPI" "0,1" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable This bit is valid" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable In indirect mode DMA can be" "0,1" newline bitfld.long 0x0 1. "ABORT,Abort request This bit aborts the" "0,1" bitfld.long 0x0 0. "EN,Enable Enable the QUADSPI." "0,1" line.long 0x4 "DCR,QUADSPI device configuration" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,Flash memory size This field defines the" bitfld.long 0x4 8.--10. "CSHT,Chip select high time CSHT+1 defines the" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CKMODE,indicates the level that clk takes" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SR,QUADSPI status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level This field gives the number" bitfld.long 0x0 5. "BUSY,Busy This bit is set when an operation" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag This bit is set when" "0,1" bitfld.long 0x0 3. "SMF,Status match flag This bit is set in" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag In indirect mode " "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag This bit is set" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag This bit is set in" "0,1" group.long 0xC++0x27 line.long 0x0 "FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag Writing 1 clears the" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag Writing 1 clears" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag Writing 1" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag Writing 1" "0,1" line.long 0x4 "DLR,QUADSPI data length register" hexmask.long 0x4 0.--31. 1. "DL,Data length Number of data to be" line.long 0x8 "CCR,QUADSPI communication configuration" bitfld.long 0x8 31. "DDRM,Double data rate mode This bit sets the" "0,1" bitfld.long 0x8 30. "DHHC,DDR hold Delay the data output by 1/4 of" "0,1" newline bitfld.long 0x8 28. "SIOO,Send instruction only once mode See" "?,?" bitfld.long 0x8 26.--27. "FMODE,Functional mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 24.--25. "DMODE,Data mode This field defines the data" "0,1,2,3" hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles This field" newline bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size This bit defines" "0,1,2,3" bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode This field defines" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADSIZE,Address size This bit defines address" "0,1,2,3" bitfld.long 0x8 10.--11. "ADMODE,Address mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 8.--9. "IMODE,Instruction mode This field defines the" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction Instruction to be send to" line.long 0xC "AR,QUADSPI address register" hexmask.long 0xC 0.--31. 1. "ADDRESS,[31 0]: Address Address to be send to" line.long 0x10 "ABR,QUADSPI alternate bytes" hexmask.long 0x10 0.--31. 1. "ALTERNATE,Alternate Bytes Optional data to be send" line.long 0x14 "DR,QUADSPI data register" hexmask.long 0x14 0.--31. 1. "DATA,Data Data to be sent/received to/from" line.long 0x18 "PSMKR,QUADSPI polling status mask" hexmask.long 0x18 0.--31. 1. "MASK,Status mask Mask to be applied to the" line.long 0x1C "PSMAR,QUADSPI polling status match" hexmask.long 0x1C 0.--31. 1. "MATCH,Status match Value to be compared with" line.long 0x20 "PIR,QUADSPI polling interval" hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval Number of CLK cycles" line.long 0x24 "LPTR,QUADSPI low-power timeout" hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period After each access in" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,clock prescaler" bitfld.long 0x0 23. "PMM,Polling match mode This bit indicates" "0,1" newline bitfld.long 0x0 22. "APMS,Automatic poll mode stop This bit" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable This bit" "0,1" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable This bit" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable This bit" "0,1" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable This bit" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level Defines in" bitfld.long 0x0 7. "FSEL,Flash memory selection This bit selects" "0,1" newline bitfld.long 0x0 6. "DFM,Dual-flash mode This bit activates" "0,1" bitfld.long 0x0 4. "SSHIFT,Sample shift By default the QUADSPI" "0,1" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable This bit is valid" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable In indirect mode DMA can be" "0,1" newline bitfld.long 0x0 1. "ABORT,Abort request This bit aborts the" "0,1" bitfld.long 0x0 0. "EN,Enable Enable the QUADSPI." "0,1" line.long 0x4 "DCR,QUADSPI device configuration" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,Flash memory size This field defines the" bitfld.long 0x4 8.--10. "CSHT,Chip select high time CSHT+1 defines the" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CKMODE,indicates the level that clk takes" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SR,QUADSPI status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level This field gives the number" bitfld.long 0x0 5. "BUSY,Busy This bit is set when an operation" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag This bit is set when" "0,1" bitfld.long 0x0 3. "SMF,Status match flag This bit is set in" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag In indirect mode " "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag This bit is set" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag This bit is set in" "0,1" group.long 0xC++0x27 line.long 0x0 "FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag Writing 1 clears the" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag Writing 1 clears" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag Writing 1" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag Writing 1" "0,1" line.long 0x4 "DLR,QUADSPI data length register" hexmask.long 0x4 0.--31. 1. "DL,Data length Number of data to be" line.long 0x8 "CCR,QUADSPI communication configuration" bitfld.long 0x8 31. "DDRM,Double data rate mode This bit sets the" "0,1" bitfld.long 0x8 30. "DHHC,DDR hold Delay the data output by 1/4 of" "0,1" newline bitfld.long 0x8 28. "SIOO,Send instruction only once mode See" "?,?" bitfld.long 0x8 26.--27. "FMODE,Functional mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 24.--25. "DMODE,Data mode This field defines the data" "0,1,2,3" hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles This field" newline bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size This bit defines" "0,1,2,3" bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode This field defines" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADSIZE,Address size This bit defines address" "0,1,2,3" bitfld.long 0x8 10.--11. "ADMODE,Address mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 8.--9. "IMODE,Instruction mode This field defines the" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction Instruction to be send to" line.long 0xC "AR,QUADSPI address register" hexmask.long 0xC 0.--31. 1. "ADDRESS,[31 0]: Address Address to be send to" line.long 0x10 "ABR,QUADSPI alternate bytes" hexmask.long 0x10 0.--31. 1. "ALTERNATE,Alternate Bytes Optional data to be send" line.long 0x14 "DR,QUADSPI data register" hexmask.long 0x14 0.--31. 1. "DATA,Data Data to be sent/received to/from" line.long 0x18 "PSMKR,QUADSPI polling status mask" hexmask.long 0x18 0.--31. 1. "MASK,Status mask Mask to be applied to the" line.long 0x1C "PSMAR,QUADSPI polling status match" hexmask.long 0x1C 0.--31. 1. "MATCH,Status match Value to be compared with" line.long 0x20 "PIR,QUADSPI polling interval" hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval Number of CLK cycles" line.long 0x24 "LPTR,QUADSPI low-power timeout" hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period After each access in" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,clock prescaler" bitfld.long 0x0 23. "PMM,Polling match mode This bit indicates" "0,1" newline bitfld.long 0x0 22. "APMS,Automatic poll mode stop This bit" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable This bit" "0,1" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable This bit" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable This bit" "0,1" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable This bit" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level Defines in" bitfld.long 0x0 7. "FSEL,Flash memory selection This bit selects" "0,1" newline bitfld.long 0x0 6. "DFM,Dual-flash mode This bit activates" "0,1" bitfld.long 0x0 4. "SSHIFT,Sample shift By default the QUADSPI" "0,1" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable This bit is valid" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable In indirect mode DMA can be" "0,1" newline bitfld.long 0x0 1. "ABORT,Abort request This bit aborts the" "0,1" bitfld.long 0x0 0. "EN,Enable Enable the QUADSPI." "0,1" line.long 0x4 "DCR,QUADSPI device configuration" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,Flash memory size This field defines the" bitfld.long 0x4 8.--10. "CSHT,Chip select high time CSHT+1 defines the" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CKMODE,indicates the level that clk takes" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SR,QUADSPI status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level This field gives the number" bitfld.long 0x0 5. "BUSY,Busy This bit is set when an operation" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag This bit is set when" "0,1" bitfld.long 0x0 3. "SMF,Status match flag This bit is set in" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag In indirect mode " "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag This bit is set" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag This bit is set in" "0,1" group.long 0xC++0x27 line.long 0x0 "FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag Writing 1 clears the" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag Writing 1 clears" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag Writing 1" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag Writing 1" "0,1" line.long 0x4 "DLR,QUADSPI data length register" hexmask.long 0x4 0.--31. 1. "DL,Data length Number of data to be" line.long 0x8 "CCR,QUADSPI communication configuration" bitfld.long 0x8 31. "DDRM,Double data rate mode This bit sets the" "0,1" bitfld.long 0x8 30. "DHHC,DDR hold Delay the data output by 1/4 of" "0,1" newline bitfld.long 0x8 28. "SIOO,Send instruction only once mode See" "?,?" bitfld.long 0x8 26.--27. "FMODE,Functional mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 24.--25. "DMODE,Data mode This field defines the data" "0,1,2,3" hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles This field" newline bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size This bit defines" "0,1,2,3" bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode This field defines" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADSIZE,Address size This bit defines address" "0,1,2,3" bitfld.long 0x8 10.--11. "ADMODE,Address mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 8.--9. "IMODE,Instruction mode This field defines the" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction Instruction to be send to" line.long 0xC "AR,QUADSPI address register" hexmask.long 0xC 0.--31. 1. "ADDRESS,[31 0]: Address Address to be send to" line.long 0x10 "ABR,QUADSPI alternate bytes" hexmask.long 0x10 0.--31. 1. "ALTERNATE,Alternate Bytes Optional data to be send" line.long 0x14 "DR,QUADSPI data register" hexmask.long 0x14 0.--31. 1. "DATA,Data Data to be sent/received to/from" line.long 0x18 "PSMKR,QUADSPI polling status mask" hexmask.long 0x18 0.--31. 1. "MASK,Status mask Mask to be applied to the" line.long 0x1C "PSMAR,QUADSPI polling status match" hexmask.long 0x1C 0.--31. 1. "MATCH,Status match Value to be compared with" line.long 0x20 "PIR,QUADSPI polling interval" hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval Number of CLK cycles" line.long 0x24 "LPTR,QUADSPI low-power timeout" hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period After each access in" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,clock prescaler" bitfld.long 0x0 23. "PMM,Polling match mode This bit indicates" "0,1" newline bitfld.long 0x0 22. "APMS,Automatic poll mode stop This bit" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable This bit" "0,1" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable This bit" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable This bit" "0,1" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable This bit" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level Defines in" bitfld.long 0x0 7. "FSEL,Flash memory selection This bit selects" "0,1" newline bitfld.long 0x0 6. "DFM,Dual-flash mode This bit activates" "0,1" bitfld.long 0x0 4. "SSHIFT,Sample shift By default the QUADSPI" "0,1" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable This bit is valid" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable In indirect mode DMA can be" "0,1" newline bitfld.long 0x0 1. "ABORT,Abort request This bit aborts the" "0,1" bitfld.long 0x0 0. "EN,Enable Enable the QUADSPI." "0,1" line.long 0x4 "DCR,QUADSPI device configuration" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,Flash memory size This field defines the" bitfld.long 0x4 8.--10. "CSHT,Chip select high time CSHT+1 defines the" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CKMODE,indicates the level that clk takes" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SR,QUADSPI status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level This field gives the number" bitfld.long 0x0 5. "BUSY,Busy This bit is set when an operation" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag This bit is set when" "0,1" bitfld.long 0x0 3. "SMF,Status match flag This bit is set in" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag In indirect mode " "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag This bit is set" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag This bit is set in" "0,1" group.long 0xC++0x27 line.long 0x0 "FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag Writing 1 clears the" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag Writing 1 clears" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag Writing 1" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag Writing 1" "0,1" line.long 0x4 "DLR,QUADSPI data length register" hexmask.long 0x4 0.--31. 1. "DL,Data length Number of data to be" line.long 0x8 "CCR,QUADSPI communication configuration" bitfld.long 0x8 31. "DDRM,Double data rate mode This bit sets the" "0,1" bitfld.long 0x8 30. "DHHC,DDR hold Delay the data output by 1/4 of" "0,1" newline bitfld.long 0x8 28. "SIOO,Send instruction only once mode See" "?,?" bitfld.long 0x8 26.--27. "FMODE,Functional mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 24.--25. "DMODE,Data mode This field defines the data" "0,1,2,3" hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles This field" newline bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size This bit defines" "0,1,2,3" bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode This field defines" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADSIZE,Address size This bit defines address" "0,1,2,3" bitfld.long 0x8 10.--11. "ADMODE,Address mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 8.--9. "IMODE,Instruction mode This field defines the" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction Instruction to be send to" line.long 0xC "AR,QUADSPI address register" hexmask.long 0xC 0.--31. 1. "ADDRESS,[31 0]: Address Address to be send to" line.long 0x10 "ABR,QUADSPI alternate bytes" hexmask.long 0x10 0.--31. 1. "ALTERNATE,Alternate Bytes Optional data to be send" line.long 0x14 "DR,QUADSPI data register" hexmask.long 0x14 0.--31. 1. "DATA,Data Data to be sent/received to/from" line.long 0x18 "PSMKR,QUADSPI polling status mask" hexmask.long 0x18 0.--31. 1. "MASK,Status mask Mask to be applied to the" line.long 0x1C "PSMAR,QUADSPI polling status match" hexmask.long 0x1C 0.--31. 1. "MATCH,Status match Value to be compared with" line.long 0x20 "PIR,QUADSPI polling interval" hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval Number of CLK cycles" line.long 0x24 "LPTR,QUADSPI low-power timeout" hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period After each access in" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,QUADSPI control register" hexmask.long.byte 0x0 24.--31. 1. "PRESCALER,clock prescaler" bitfld.long 0x0 23. "PMM,Polling match mode This bit indicates" "0,1" newline bitfld.long 0x0 22. "APMS,Automatic poll mode stop This bit" "0,1" bitfld.long 0x0 20. "TOIE,TimeOut interrupt enable This bit" "0,1" newline bitfld.long 0x0 19. "SMIE,Status match interrupt enable This bit" "0,1" bitfld.long 0x0 18. "FTIE,FIFO threshold interrupt enable This bit" "0,1" newline bitfld.long 0x0 17. "TCIE,Transfer complete interrupt enable This" "0,1" bitfld.long 0x0 16. "TEIE,Transfer error interrupt enable This bit" "0,1" newline hexmask.long.byte 0x0 8.--12. 1. "FTHRES,FIFO threshold level Defines in" bitfld.long 0x0 7. "FSEL,Flash memory selection This bit selects" "0,1" newline bitfld.long 0x0 6. "DFM,Dual-flash mode This bit activates" "0,1" bitfld.long 0x0 4. "SSHIFT,Sample shift By default the QUADSPI" "0,1" newline bitfld.long 0x0 3. "TCEN,Timeout counter enable This bit is valid" "0,1" bitfld.long 0x0 2. "DMAEN,DMA enable In indirect mode DMA can be" "0,1" newline bitfld.long 0x0 1. "ABORT,Abort request This bit aborts the" "0,1" bitfld.long 0x0 0. "EN,Enable Enable the QUADSPI." "0,1" line.long 0x4 "DCR,QUADSPI device configuration" hexmask.long.byte 0x4 16.--20. 1. "FSIZE,Flash memory size This field defines the" bitfld.long 0x4 8.--10. "CSHT,Chip select high time CSHT+1 defines the" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CKMODE,indicates the level that clk takes" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SR,QUADSPI status register" hexmask.long.byte 0x0 8.--13. 1. "FLEVEL,FIFO level This field gives the number" bitfld.long 0x0 5. "BUSY,Busy This bit is set when an operation" "0,1" newline bitfld.long 0x0 4. "TOF,Timeout flag This bit is set when" "0,1" bitfld.long 0x0 3. "SMF,Status match flag This bit is set in" "0,1" newline bitfld.long 0x0 2. "FTF,FIFO threshold flag In indirect mode " "0,1" bitfld.long 0x0 1. "TCF,Transfer complete flag This bit is set" "0,1" newline bitfld.long 0x0 0. "TEF,Transfer error flag This bit is set in" "0,1" group.long 0xC++0x27 line.long 0x0 "FCR,QUADSPI flag clear register" bitfld.long 0x0 4. "CTOF,Clear timeout flag Writing 1 clears the" "0,1" bitfld.long 0x0 3. "CSMF,Clear status match flag Writing 1 clears" "0,1" newline bitfld.long 0x0 1. "CTCF,Clear transfer complete flag Writing 1" "0,1" bitfld.long 0x0 0. "CTEF,Clear transfer error flag Writing 1" "0,1" line.long 0x4 "DLR,QUADSPI data length register" hexmask.long 0x4 0.--31. 1. "DL,Data length Number of data to be" line.long 0x8 "CCR,QUADSPI communication configuration" bitfld.long 0x8 31. "DDRM,Double data rate mode This bit sets the" "0,1" bitfld.long 0x8 30. "DHHC,DDR hold Delay the data output by 1/4 of" "0,1" newline bitfld.long 0x8 28. "SIOO,Send instruction only once mode See" "?,?" bitfld.long 0x8 26.--27. "FMODE,Functional mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 24.--25. "DMODE,Data mode This field defines the data" "0,1,2,3" hexmask.long.byte 0x8 18.--22. 1. "DCYC,Number of dummy cycles This field" newline bitfld.long 0x8 16.--17. "ABSIZE,Alternate bytes size This bit defines" "0,1,2,3" bitfld.long 0x8 14.--15. "ABMODE,Alternate bytes mode This field defines" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADSIZE,Address size This bit defines address" "0,1,2,3" bitfld.long 0x8 10.--11. "ADMODE,Address mode This field defines the" "0,1,2,3" newline bitfld.long 0x8 8.--9. "IMODE,Instruction mode This field defines the" "0,1,2,3" hexmask.long.byte 0x8 0.--7. 1. "INSTRUCTION,Instruction Instruction to be send to" line.long 0xC "AR,QUADSPI address register" hexmask.long 0xC 0.--31. 1. "ADDRESS,[31 0]: Address Address to be send to" line.long 0x10 "ABR,QUADSPI alternate bytes" hexmask.long 0x10 0.--31. 1. "ALTERNATE,Alternate Bytes Optional data to be send" line.long 0x14 "DR,QUADSPI data register" hexmask.long 0x14 0.--31. 1. "DATA,Data Data to be sent/received to/from" line.long 0x18 "PSMKR,QUADSPI polling status mask" hexmask.long 0x18 0.--31. 1. "MASK,Status mask Mask to be applied to the" line.long 0x1C "PSMAR,QUADSPI polling status match" hexmask.long 0x1C 0.--31. 1. "MATCH,Status match Value to be compared with" line.long 0x20 "PIR,QUADSPI polling interval" hexmask.long.word 0x20 0.--15. 1. "INTERVAL,Polling interval Number of CLK cycles" line.long 0x24 "LPTR,QUADSPI low-power timeout" hexmask.long.word 0x24 0.--15. 1. "TIMEOUT,Timeout period After each access in" endif tree.end endif tree "RAMECC (RAM ECC Monitoring)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "RAMECC1" base ad:0x52009000 group.long 0x0++0x3 line.long 0x0 "IER,RAMECC interrupt enable" bitfld.long 0x0 3. "GECCDEBWIE,Global ECC double error on byte write" "0,1" bitfld.long 0x0 2. "GECCDEIE,Global ECC double error interrupt" "0,1" bitfld.long 0x0 1. "GECCSEIE_,Global ECC single error interrupt" "0,1" bitfld.long 0x0 0. "GIE,Global interrupt enable" "0,1" group.long 0x20++0x17 line.long 0x0 "M1CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x4 "M1SR,RAMECC monitor x status" bitfld.long 0x4 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x4 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x4 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x8 "M1FAR,RAMECC monitor x failing address" bitfld.long 0x8 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x8 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x8 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0xC "M1FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0xC 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0xC 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x10 "M1FDRH,RAMECC monitor x failing data high" bitfld.long 0x10 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x10 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x10 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x10 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x14 "M1FECR,RAMECC monitor x failing ECC error code" bitfld.long 0x14 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x14 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x14 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x40++0xF line.long 0x0 "M2CR,RAMECC monitor x configuration" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x4 "M2SR,RAMECC monitor x status" bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x8 "M2FAR,RAMECC monitor x failing address" bitfld.long 0x8 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x8 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0xC "M2FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0xC 0. "SEDCF,ECC single error detected and corrected" "0,1" rgroup.long 0x50++0x3 line.long 0x0 "M2FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x58++0x3 line.long 0x0 "M2FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x60++0x7 line.long 0x0 "M3CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" line.long 0x4 "M3SR,RAMECC monitor x status" hexmask.long 0x4 0.--31. 1. "FADD,ECC error failing address" group.long 0x68++0x3 line.long 0x0 "M3FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x6C++0x7 line.long 0x0 "M3FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M3FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x7C++0xF line.long 0x0 "M3FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M4CR,RAMECC monitor x configuration" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" line.long 0x8 "M4SR,RAMECC monitor x status" hexmask.long 0x8 0.--31. 1. "FDATAL,Failing data low" line.long 0xC "M4FAR,RAMECC monitor x failing address" hexmask.long 0xC 0.--31. 1. "FDATAH,Failing data high (64-bit" group.long 0x8C++0x3 line.long 0x0 "M4FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0xA0++0x3 line.long 0x0 "M5CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" group.long 0xA4++0x7 line.long 0x0 "M5SR,RAMECC monitor x status" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FAR,RAMECC monitor x failing address" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" rgroup.long 0xAC++0xB line.long 0x0 "M5FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" line.long 0x8 "M5FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x8 0.--31. 1. "FEC,Failing error code" tree.end tree "RAMECC2" base ad:0x48023000 group.long 0x0++0x3 line.long 0x0 "IER,RAMECC interrupt enable" bitfld.long 0x0 3. "GECCDEBWIE,Global ECC double error on byte write" "0,1" bitfld.long 0x0 2. "GECCDEIE,Global ECC double error interrupt" "0,1" bitfld.long 0x0 1. "GECCSEIE_,Global ECC single error interrupt" "0,1" bitfld.long 0x0 0. "GIE,Global interrupt enable" "0,1" group.long 0x20++0x3 line.long 0x0 "M1CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" group.long 0x40++0x3 line.long 0x0 "M2CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" group.long 0x60++0x3 line.long 0x0 "M3CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" group.long 0x80++0x3 line.long 0x0 "M4CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" group.long 0xA0++0x3 line.long 0x0 "M5CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" group.long 0x24++0x3 line.long 0x0 "M1SR,RAMECC monitor x status" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x44++0x3 line.long 0x0 "M2SR,RAMECC monitor x status" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x64++0x3 line.long 0x0 "M3SR,RAMECC monitor x status" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x84++0x3 line.long 0x0 "M4SR,RAMECC monitor x status" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0xA4++0x3 line.long 0x0 "M5SR,RAMECC monitor x status" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "M1FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x48++0x3 line.long 0x0 "M2FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x68++0x3 line.long 0x0 "M3FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x88++0x3 line.long 0x0 "M4FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" group.long 0xA8++0x3 line.long 0x0 "M5FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x2C++0x3 line.long 0x0 "M1FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x4C++0x3 line.long 0x0 "M2FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x6C++0x3 line.long 0x0 "M3FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x8C++0x3 line.long 0x0 "M4FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0xAC++0x3 line.long 0x0 "M5FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x30++0x3 line.long 0x0 "M1FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" group.long 0x50++0x3 line.long 0x0 "M2FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x70++0x3 line.long 0x0 "M3FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0xB0++0x3 line.long 0x0 "M5FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" group.long 0x34++0x3 line.long 0x0 "M1FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" group.long 0x58++0x3 line.long 0x0 "M2FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" rgroup.long 0x7C++0x3 line.long 0x0 "M3FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" rgroup.long 0x90++0x3 line.long 0x0 "M4FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" rgroup.long 0xB4++0x3 line.long 0x0 "M5FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" tree.end tree "RAMECC3" base ad:0x58027000 group.long 0x0++0x3 line.long 0x0 "IER,RAMECC interrupt enable" bitfld.long 0x0 3. "GECCDEBWIE,Global ECC double error on byte write" "0,1" bitfld.long 0x0 2. "GECCDEIE,Global ECC double error interrupt" "0,1" bitfld.long 0x0 1. "GECCSEIE_,Global ECC single error interrupt" "0,1" bitfld.long 0x0 0. "GIE,Global interrupt enable" "0,1" group.long 0x20++0x3 line.long 0x0 "M1CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" group.long 0x40++0x3 line.long 0x0 "M2CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" group.long 0x24++0x3 line.long 0x0 "M1SR,RAMECC monitor x status" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x44++0x3 line.long 0x0 "M2SR,RAMECC monitor x status" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" rgroup.long 0x28++0x3 line.long 0x0 "M1FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x48++0x3 line.long 0x0 "M2FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x2C++0x3 line.long 0x0 "M1FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x4C++0x3 line.long 0x0 "M2FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x30++0x3 line.long 0x0 "M1FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" group.long 0x50++0x3 line.long 0x0 "M2FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" group.long 0x34++0x3 line.long 0x0 "M1FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" group.long 0x58++0x3 line.long 0x0 "M2FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" tree.end endif sif (cpuis("STM32H7A3*")) tree "RAMECC" base ad:0x52009000 group.long 0x0++0x3 line.long 0x0 "IER,RAMECC interrupt enable" bitfld.long 0x0 3. "GECCDEBWIE,Global ECC double error on byte write" "0,1" bitfld.long 0x0 2. "GECCDEIE,Global ECC double error interrupt" "0,1" bitfld.long 0x0 1. "GECCSEIE_,Global ECC single error interrupt" "0,1" bitfld.long 0x0 0. "GIE,Global interrupt enable" "0,1" group.long 0x20++0x17 line.long 0x0 "M1CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x4 "M1SR,RAMECC monitor x status" bitfld.long 0x4 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x4 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x4 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x8 "M1FAR,RAMECC monitor x failing address" bitfld.long 0x8 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x8 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x8 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0xC "M1FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0xC 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0xC 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x10 "M1FDRH,RAMECC monitor x failing data high" bitfld.long 0x10 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x10 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x10 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x10 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x14 "M1FECR,RAMECC monitor x failing ECC error code" bitfld.long 0x14 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x14 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x14 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x40++0xF line.long 0x0 "M2CR,RAMECC monitor x configuration" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x4 "M2SR,RAMECC monitor x status" bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x8 "M2FAR,RAMECC monitor x failing address" bitfld.long 0x8 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x8 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0xC "M2FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0xC 0. "SEDCF,ECC single error detected and corrected" "0,1" rgroup.long 0x50++0x3 line.long 0x0 "M2FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x58++0x3 line.long 0x0 "M2FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x60++0x7 line.long 0x0 "M3CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" line.long 0x4 "M3SR,RAMECC monitor x status" hexmask.long 0x4 0.--31. 1. "FADD,ECC error failing address" group.long 0x68++0x3 line.long 0x0 "M3FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x6C++0x7 line.long 0x0 "M3FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M3FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x7C++0xF line.long 0x0 "M3FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M4CR,RAMECC monitor x configuration" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" line.long 0x8 "M4SR,RAMECC monitor x status" hexmask.long 0x8 0.--31. 1. "FDATAL,Failing data low" line.long 0xC "M4FAR,RAMECC monitor x failing address" hexmask.long 0xC 0.--31. 1. "FDATAH,Failing data high (64-bit" group.long 0x8C++0x3 line.long 0x0 "M4FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0xA0++0x3 line.long 0x0 "M5CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" group.long 0xA4++0x7 line.long 0x0 "M5SR,RAMECC monitor x status" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FAR,RAMECC monitor x failing address" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" rgroup.long 0xAC++0xB line.long 0x0 "M5FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" line.long 0x8 "M5FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x8 0.--31. 1. "FEC,Failing error code" tree.end endif sif (cpuis("STM32H7B0*")) tree "RAMECC" base ad:0x52009000 group.long 0x0++0x3 line.long 0x0 "IER,RAMECC interrupt enable" bitfld.long 0x0 3. "GECCDEBWIE,Global ECC double error on byte write" "0,1" bitfld.long 0x0 2. "GECCDEIE,Global ECC double error interrupt" "0,1" bitfld.long 0x0 1. "GECCSEIE_,Global ECC single error interrupt" "0,1" bitfld.long 0x0 0. "GIE,Global interrupt enable" "0,1" group.long 0x20++0x17 line.long 0x0 "M1CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x4 "M1SR,RAMECC monitor x status" bitfld.long 0x4 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x4 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x4 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x8 "M1FAR,RAMECC monitor x failing address" bitfld.long 0x8 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x8 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x8 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0xC "M1FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0xC 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0xC 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x10 "M1FDRH,RAMECC monitor x failing data high" bitfld.long 0x10 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x10 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x10 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x10 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x14 "M1FECR,RAMECC monitor x failing ECC error code" bitfld.long 0x14 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x14 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x14 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x40++0xF line.long 0x0 "M2CR,RAMECC monitor x configuration" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x4 "M2SR,RAMECC monitor x status" bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x8 "M2FAR,RAMECC monitor x failing address" bitfld.long 0x8 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x8 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0xC "M2FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0xC 0. "SEDCF,ECC single error detected and corrected" "0,1" rgroup.long 0x50++0x3 line.long 0x0 "M2FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x58++0x3 line.long 0x0 "M2FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x60++0x7 line.long 0x0 "M3CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" line.long 0x4 "M3SR,RAMECC monitor x status" hexmask.long 0x4 0.--31. 1. "FADD,ECC error failing address" group.long 0x68++0x3 line.long 0x0 "M3FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x6C++0x7 line.long 0x0 "M3FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M3FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x7C++0xF line.long 0x0 "M3FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M4CR,RAMECC monitor x configuration" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" line.long 0x8 "M4SR,RAMECC monitor x status" hexmask.long 0x8 0.--31. 1. "FDATAL,Failing data low" line.long 0xC "M4FAR,RAMECC monitor x failing address" hexmask.long 0xC 0.--31. 1. "FDATAH,Failing data high (64-bit" group.long 0x8C++0x3 line.long 0x0 "M4FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0xA0++0x3 line.long 0x0 "M5CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" group.long 0xA4++0x7 line.long 0x0 "M5SR,RAMECC monitor x status" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FAR,RAMECC monitor x failing address" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" rgroup.long 0xAC++0xB line.long 0x0 "M5FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" line.long 0x8 "M5FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x8 0.--31. 1. "FEC,Failing error code" tree.end endif sif (cpuis("STM32H7B3*")) tree "RAMECC" base ad:0x52009000 group.long 0x0++0x3 line.long 0x0 "IER,RAMECC interrupt enable" bitfld.long 0x0 3. "GECCDEBWIE,Global ECC double error on byte write" "0,1" bitfld.long 0x0 2. "GECCDEIE,Global ECC double error interrupt" "0,1" bitfld.long 0x0 1. "GECCSEIE_,Global ECC single error interrupt" "0,1" bitfld.long 0x0 0. "GIE,Global interrupt enable" "0,1" group.long 0x20++0x17 line.long 0x0 "M1CR,RAMECC monitor x configuration" bitfld.long 0x0 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x0 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x0 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x4 "M1SR,RAMECC monitor x status" bitfld.long 0x4 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x4 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x4 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x8 "M1FAR,RAMECC monitor x failing address" bitfld.long 0x8 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x8 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x8 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0xC "M1FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0xC 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0xC 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x10 "M1FDRH,RAMECC monitor x failing data high" bitfld.long 0x10 5. "ECCELEN,ECC error latching enable" "0,1" bitfld.long 0x10 4. "ECCDEBWIE,ECC double error on byte write (BW)" "0,1" bitfld.long 0x10 3. "ECCDEIE,ECC double error interrupt" "0,1" bitfld.long 0x10 2. "ECCSEIE,ECC single error interrupt" "0,1" line.long 0x14 "M1FECR,RAMECC monitor x failing ECC error code" bitfld.long 0x14 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x14 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x14 0. "SEDCF,ECC single error detected and corrected" "0,1" group.long 0x40++0xF line.long 0x0 "M2CR,RAMECC monitor x configuration" bitfld.long 0x0 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x0 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x0 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x4 "M2SR,RAMECC monitor x status" bitfld.long 0x4 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x4 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x4 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0x8 "M2FAR,RAMECC monitor x failing address" bitfld.long 0x8 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0x8 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0x8 0. "SEDCF,ECC single error detected and corrected" "0,1" line.long 0xC "M2FDRL,RAMECC monitor x failing data low" bitfld.long 0xC 2. "DEBWDF,ECC double error on byte write (BW)" "0,1" bitfld.long 0xC 1. "DEDF,ECC double error detected" "0,1" bitfld.long 0xC 0. "SEDCF,ECC single error detected and corrected" "0,1" rgroup.long 0x50++0x3 line.long 0x0 "M2FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x58++0x3 line.long 0x0 "M2FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x60++0x7 line.long 0x0 "M3CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" line.long 0x4 "M3SR,RAMECC monitor x status" hexmask.long 0x4 0.--31. 1. "FADD,ECC error failing address" group.long 0x68++0x3 line.long 0x0 "M3FAR,RAMECC monitor x failing address" hexmask.long 0x0 0.--31. 1. "FADD,ECC error failing address" rgroup.long 0x6C++0x7 line.long 0x0 "M3FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M3FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" rgroup.long 0x7C++0xF line.long 0x0 "M3FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAL,Failing data low" line.long 0x4 "M4CR,RAMECC monitor x configuration" hexmask.long 0x4 0.--31. 1. "FDATAL,Failing data low" line.long 0x8 "M4SR,RAMECC monitor x status" hexmask.long 0x8 0.--31. 1. "FDATAL,Failing data low" line.long 0xC "M4FAR,RAMECC monitor x failing address" hexmask.long 0xC 0.--31. 1. "FDATAH,Failing data high (64-bit" group.long 0x8C++0x3 line.long 0x0 "M4FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FDRH,RAMECC monitor x failing data high" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0x90++0x3 line.long 0x0 "M4FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x0 0.--31. 1. "FDATAH,Failing data high (64-bit" rgroup.long 0xA0++0x3 line.long 0x0 "M5CR,RAMECC monitor x configuration" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" group.long 0xA4++0x7 line.long 0x0 "M5SR,RAMECC monitor x status" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FAR,RAMECC monitor x failing address" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" rgroup.long 0xAC++0xB line.long 0x0 "M5FDRL,RAMECC monitor x failing data low" hexmask.long 0x0 0.--31. 1. "FEC,Failing error code" line.long 0x4 "M5FDRH,RAMECC monitor x failing data high" hexmask.long 0x4 0.--31. 1. "FEC,Failing error code" line.long 0x8 "M5FECR,RAMECC monitor x failing ECC error code" hexmask.long 0x8 0.--31. 1. "FEC,Failing error code" tree.end endif tree.end tree "RCC (Reset and Clock Control)" base ad:0x58024400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) group.long 0x0++0x3 line.long 0x0 "CR,clock control register" bitfld.long 0x0 29. "PLL3RDY,PLL3 clock ready flag" "0,1" bitfld.long 0x0 28. "PLL3ON,PLL3 enable" "0,1" newline bitfld.long 0x0 27. "PLL2RDY,PLL2 clock ready flag" "0,1" bitfld.long 0x0 26. "PLL2ON,PLL2 enable" "0,1" newline bitfld.long 0x0 25. "PLL1RDY,PLL1 clock ready flag" "0,1" bitfld.long 0x0 24. "PLL1ON,PLL1 enable" "0,1" newline bitfld.long 0x0 19. "HSECSSON,HSE Clock Security System" "0,1" bitfld.long 0x0 18. "HSEBYP,HSE clock bypass" "0,1" newline bitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0,1" bitfld.long 0x0 16. "HSEON,HSE clock enable" "0,1" newline bitfld.long 0x0 15. "D2CKRDY,D2 domain clocks ready" "0,1" bitfld.long 0x0 14. "D1CKRDY,D1 domain clocks ready" "0,1" newline bitfld.long 0x0 13. "RC48RDY,RC48 clock ready flag" "0,1" bitfld.long 0x0 12. "RC48ON,RC48 clock enable" "0,1" newline bitfld.long 0x0 9. "CSIKERON,CSI clock enable in Stop" "0,1" bitfld.long 0x0 8. "CSIRDY,CSI clock ready flag" "0,1" newline bitfld.long 0x0 7. "CSION,CSI clock enable" "0,1" bitfld.long 0x0 5. "HSIDIVF,HSI divider flag" "0,1" newline bitfld.long 0x0 3.--4. "HSIDIV,HSI clock divider" "0,1,2,3" bitfld.long 0x0 2. "HSIRDY,HSI clock ready flag" "0,1" newline bitfld.long 0x0 1. "HSIKERON,High Speed Internal clock enable in Stop" "0,1" bitfld.long 0x0 0. "HSION,Internal high-speed clock" "0,1" group.long 0x8++0x3 line.long 0x0 "CRRCR,RCC clock recovery RC register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) hexmask.long.word 0x0 0.--9. 1. "HSI48CAL,Internal RC 48 MHz clock calibration" endif sif (cpuis("STM32H742*")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" newline endif sif (cpuis("STM32H743*")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" endif sif (cpuis("STM32H745??-CM4")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" newline endif sif (cpuis("STM32H745??-CM7")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" endif sif (cpuis("STM32H747??-CM4")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" newline endif sif (cpuis("STM32H747??-CM7")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" endif sif (cpuis("STM32H750*")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" newline endif sif (cpuis("STM32H753*")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" endif sif (cpuis("STM32H755??-CM4")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" newline endif sif (cpuis("STM32H755??-CM7")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" endif sif (cpuis("STM32H757??-CM4")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" newline endif sif (cpuis("STM32H757??-CM7")) hexmask.long.word 0x0 0.--9. 1. "RC48CAL,Internal RC 48 MHz clock" endif group.long 0x10++0x3 line.long 0x0 "CFGR,RCC Clock Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 29.--31. "MCO2,Micro-controller clock output" "0,1,2,3,4,5,6,7" bitfld.long 0x0 22.--24. "MCO1,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 29.--31. "MCO2SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif hexmask.long.byte 0x0 25.--28. 1. "MCO2PRE,MCO2 prescaler" sif (cpuis("STM32H742*")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 22.--24. "MCO1SEL,Micro-controller clock output" "0,1,2,3,4,5,6,7" endif hexmask.long.byte 0x0 18.--21. 1. "MCO1PRE,MCO1 prescaler" newline bitfld.long 0x0 15. "TIMPRE,Timers clocks prescaler" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 14. "HRTIMSEL,High Resolution Timer clock prescaler" "0,1" endif hexmask.long.byte 0x0 8.--13. 1. "RTCPRE,HSE division factor for RTC" newline bitfld.long 0x0 7. "STOPKERWUCK,Kernel clock selection after a wake up" "0,1" bitfld.long 0x0 6. "STOPWUCK,System clock selection after a wake up" "0,1" newline bitfld.long 0x0 3.--5. "SWS,System clock switch status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "SW,System clock switch" "0,1,2,3,4,5,6,7" group.long 0x18++0xB line.long 0x0 "D1CFGR,RCC Domain 1 Clock Configuration" hexmask.long.byte 0x0 8.--11. 1. "D1CPRE,D1 domain Core prescaler" bitfld.long 0x0 4.--6. "D1PPRE,D1 domain APB3 prescaler" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "HPRE,D1 domain AHB prescaler" line.long 0x4 "D2CFGR,RCC Domain 2 Clock Configuration" bitfld.long 0x4 8.--10. "D2PPRE2,D2 domain APB2 prescaler" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "D2PPRE1,D2 domain APB1 prescaler" "0,1,2,3,4,5,6,7" line.long 0x8 "D3CFGR,RCC Domain 3 Clock Configuration" bitfld.long 0x8 4.--6. "D3PPRE,D3 domain APB4 prescaler" "0,1,2,3,4,5,6,7" group.long 0x28++0x1F line.long 0x0 "PLLCKSELR,RCC PLLs Clock Source Selection" hexmask.long.byte 0x0 20.--25. 1. "DIVM3,Prescaler for PLL3" hexmask.long.byte 0x0 12.--17. 1. "DIVM2,Prescaler for PLL2" newline hexmask.long.byte 0x0 4.--9. 1. "DIVM1,Prescaler for PLL1" bitfld.long 0x0 0.--1. "PLLSRC,DIVMx and PLLs clock source" "0,1,2,3" line.long 0x4 "PLLCFGR,RCC PLLs Configuration" bitfld.long 0x4 24. "DIVR3EN,PLL3 DIVR divider output" "0,1" bitfld.long 0x4 23. "DIVQ3EN,PLL3 DIVQ divider output" "0,1" newline bitfld.long 0x4 22. "DIVP3EN,PLL3 DIVP divider output" "0,1" bitfld.long 0x4 21. "DIVR2EN,PLL2 DIVR divider output" "0,1" newline bitfld.long 0x4 20. "DIVQ2EN,PLL2 DIVQ divider output" "0,1" bitfld.long 0x4 19. "DIVP2EN,PLL2 DIVP divider output" "0,1" newline bitfld.long 0x4 18. "DIVR1EN,PLL1 DIVR divider output" "0,1" bitfld.long 0x4 17. "DIVQ1EN,PLL1 DIVQ divider output" "0,1" newline bitfld.long 0x4 16. "DIVP1EN,PLL1 DIVP divider output" "0,1" bitfld.long 0x4 10.--11. "PLL3RGE,PLL3 input frequency range" "0,1,2,3" newline bitfld.long 0x4 9. "PLL3VCOSEL,PLL3 VCO selection" "0,1" bitfld.long 0x4 8. "PLL3FRACEN,PLL3 fractional latch" "0,1" newline bitfld.long 0x4 6.--7. "PLL2RGE,PLL2 input frequency range" "0,1,2,3" bitfld.long 0x4 5. "PLL2VCOSEL,PLL2 VCO selection" "0,1" newline bitfld.long 0x4 4. "PLL2FRACEN,PLL2 fractional latch" "0,1" bitfld.long 0x4 2.--3. "PLL1RGE,PLL1 input frequency range" "0,1,2,3" newline bitfld.long 0x4 1. "PLL1VCOSEL,PLL1 VCO selection" "0,1" bitfld.long 0x4 0. "PLL1FRACEN,PLL1 fractional latch" "0,1" line.long 0x8 "PLL1DIVR,RCC PLL1 Dividers Configuration" hexmask.long.byte 0x8 24.--30. 1. "DIVR1,PLL1 DIVR division factor" hexmask.long.byte 0x8 16.--22. 1. "DIVQ1,PLL1 DIVQ division factor" newline hexmask.long.byte 0x8 9.--15. 1. "DIVP1,PLL1 DIVP division factor" hexmask.long.word 0x8 0.--8. 1. "DIVN1,Multiplication factor for PLL1" line.long 0xC "PLL1FRACR,RCC PLL1 Fractional Divider" hexmask.long.word 0xC 3.--15. 1. "FRACN1,Fractional part of the multiplication" line.long 0x10 "PLL2DIVR,RCC PLL2 Dividers Configuration" hexmask.long.byte 0x10 24.--30. 1. "DIVR2,PLL1 DIVR division factor" hexmask.long.byte 0x10 16.--22. 1. "DIVQ2,PLL1 DIVQ division factor" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")) hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL1 DIVP division factor" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x10 9.--15. 1. "DIVP12,PLL1 DIVP division factor" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL1 DIVP division factor" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL1 DIVP division factor" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL1 DIVP division factor" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL1 DIVP division factor" newline endif hexmask.long.word 0x10 0.--8. 1. "DIVN2,Multiplication factor for PLL1" line.long 0x14 "PLL2FRACR,RCC PLL2 Fractional Divider" hexmask.long.word 0x14 3.--15. 1. "FRACN2,Fractional part of the multiplication" line.long 0x18 "PLL3DIVR,RCC PLL3 Dividers Configuration" hexmask.long.byte 0x18 24.--30. 1. "DIVR3,PLL DIVR division factor" hexmask.long.byte 0x18 16.--22. 1. "DIVQ3,PLL DIVQ division factor" newline hexmask.long.byte 0x18 9.--15. 1. "DIVP3,PLL DIVP division factor" hexmask.long.word 0x18 0.--8. 1. "DIVN3,Multiplication factor for PLL1" line.long 0x1C "PLL3FRACR,RCC PLL3 Fractional Divider" hexmask.long.word 0x1C 3.--15. 1. "FRACN3,Fractional part of the multiplication" group.long 0x4C++0xF line.long 0x0 "D1CCIPR,RCC Domain 1 Kernel Clock Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 28.--29. "CKPERSEL,per_ck clock source" "0,1,2,3" bitfld.long 0x0 16. "SDMMCSEL,SDMMC kernel clock source" "0,1" newline bitfld.long 0x0 4.--5. "OCTOSPISEL,QUADSPI kernel clock source" "0,1,2,3" bitfld.long 0x0 0.--1. "FMCSEL,FMC kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 28.--29. "CKPERSRC,per_ck clock source" "0,1,2,3" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 16. "SDMMCSRC,SDMMC kernel clock source" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 4.--5. "QSPISRC,QUADSPI kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 0.--1. "FMCSRC,FMC kernel clock source" "0,1,2,3" endif line.long 0x4 "D2CCIP1R,RCC Domain 2 Kernel Clock Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x4 31. "SWPMISEL,SWPMI kernel clock source" "0,1" bitfld.long 0x4 28.--29. "FDCANSEL,FDCAN kernel clock source" "0,1,2,3" newline bitfld.long 0x4 24. "DFSDM1SEL,DFSDM1 kernel Clk clock source" "0,1" bitfld.long 0x4 20.--21. "SPDIFRXSEL,SPDIFRX kernel clock source" "0,1,2,3" newline bitfld.long 0x4 16.--18. "SPI45SEL,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. "SPI123SEL,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "SAI1SEL,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 31. "SWPSRC,SWPMI kernel clock source" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 28.--29. "FDCANSRC,FDCAN kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 24. "DFSDM1SRC,DFSDM1 kernel Clk clock source" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 20.--21. "SPDIFSRC,SPDIFRX kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 16.--18. "SPI45SRC,SPI4 and 5 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 12.--14. "SPI123SRC,SPI/I2S1 2 and 3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 6.--8. "SAI23SRC,SAI2 and SAI3 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H742*")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 0.--2. "SAI1SRC,SAI1 and DFSDM1 kernel Aclk clock source" "0,1,2,3,4,5,6,7" endif line.long 0x8 "D2CCIP2R,RCC Domain 2 Kernel Clock Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 28.--30. "LPTIM1SEL,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22.--23. "CECSEL,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSEL,USBOTG 1 and 2 kernel clock source" "0,1,2,3" bitfld.long 0x8 12.--13. "I2C123SEL,I2C1 2 3 kernel clock source" "0,1,2,3" newline bitfld.long 0x8 8.--9. "RNGSEL,RNG kernel clock source" "0,1,2,3" bitfld.long 0x8 3.--5. "USART16910SEL,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SEL,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H742*")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 28.--30. "LPTIM1SRC,LPTIM1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H742*")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H743*")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H753*")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 22.--23. "CECSRC,HDMI-CEC kernel clock source" "0,1,2,3" newline bitfld.long 0x8 20.--21. "USBSRC,USBOTG 1 and 2 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H742*")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 12.--13. "I2C123SRC,I2C1 2 3 kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H742*")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 8.--9. "RNGSRC,RNG kernel clock source" "0,1,2,3" endif sif (cpuis("STM32H742*")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H743*")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H753*")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 3.--5. "USART16SRC,USART1 and 6 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "USART234578SRC,USART2/3 UART4 5 7/8 (APB1) kernel" "0,1,2,3,4,5,6,7" endif line.long 0xC "D3CCIPR,RCC Domain 3 Kernel Clock Configuration" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0xC 28.--30. "SPI6SEL,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 24.--26. "SAI4BSEL,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 21.--23. "SAI4ASEL,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 16.--17. "ADCSEL,SAR ADC kernel clock source" "0,1,2,3" newline bitfld.long 0xC 13.--15. "LPTIM345SEL,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--12. "LPTIM2SEL,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8.--9. "I2C4SEL,I2C4 kernel clock source" "0,1,2,3" bitfld.long 0xC 0.--2. "LPUART1SEL,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H742*")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H743*")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H753*")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 28.--30. "SPI6SRC,SPI6 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H742*")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H743*")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H753*")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 24.--26. "SAI4BSRC,Sub-Block B of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 21.--23. "SAI4ASRC,Sub-Block A of SAI4 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H742*")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H743*")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H753*")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 16.--17. "ADCSRC,SAR ADC kernel clock source" "0,1,2,3" bitfld.long 0xC 13.--15. "LPTIM345SRC,LPTIM3 4 5 kernel clock source" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10.--12. "LPTIM2SRC,LPTIM2 kernel clock source" "0,1,2,3,4,5,6,7" bitfld.long 0xC 8.--9. "I2C4SRC,I2C4 kernel clock source" "0,1,2,3" newline endif sif (cpuis("STM32H742*")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H743*")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H753*")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 0.--2. "LPUART1SRC,LPUART1 kernel clock source" "0,1,2,3,4,5,6,7" endif group.long 0x60++0xB line.long 0x0 "CIER,RCC Clock Source Interrupt Enable" bitfld.long 0x0 9. "LSECSSIE,LSE clock security system Interrupt" "0,1" bitfld.long 0x0 8. "PLL3RDYIE,PLL3 ready Interrupt" "0,1" newline bitfld.long 0x0 7. "PLL2RDYIE,PLL2 ready Interrupt" "0,1" bitfld.long 0x0 6. "PLL1RDYIE,PLL1 ready Interrupt" "0,1" newline bitfld.long 0x0 5. "RC48RDYIE,RC48 ready Interrupt" "0,1" bitfld.long 0x0 4. "CSIRDYIE,CSI ready Interrupt Enable" "0,1" newline bitfld.long 0x0 3. "HSERDYIE,HSE ready Interrupt Enable" "0,1" bitfld.long 0x0 2. "HSIRDYIE,HSI ready Interrupt Enable" "0,1" newline bitfld.long 0x0 1. "LSERDYIE,LSE ready Interrupt Enable" "0,1" bitfld.long 0x0 0. "LSIRDYIE,LSI ready Interrupt Enable" "0,1" line.long 0x4 "CIFR,RCC Clock Source Interrupt Flag" bitfld.long 0x4 10. "HSECSSF,HSE clock security system Interrupt" "0,1" bitfld.long 0x4 9. "LSECSSF,LSE clock security system Interrupt" "0,1" newline bitfld.long 0x4 8. "PLL3RDYF,PLL3 ready Interrupt Flag" "0,1" bitfld.long 0x4 7. "PLL2RDYF,PLL2 ready Interrupt Flag" "0,1" newline bitfld.long 0x4 6. "PLL1RDYF,PLL1 ready Interrupt Flag" "0,1" bitfld.long 0x4 5. "RC48RDYF,RC48 ready Interrupt Flag" "0,1" newline bitfld.long 0x4 4. "CSIRDY,CSI ready Interrupt Flag" "0,1" bitfld.long 0x4 3. "HSERDYF,HSE ready Interrupt Flag" "0,1" newline bitfld.long 0x4 2. "HSIRDYF,HSI ready Interrupt Flag" "0,1" bitfld.long 0x4 1. "LSERDYF,LSE ready Interrupt Flag" "0,1" newline bitfld.long 0x4 0. "LSIRDYF,LSI ready Interrupt Flag" "0,1" line.long 0x8 "CICR,RCC Clock Source Interrupt Clear" bitfld.long 0x8 10. "HSECSSC,HSE clock security system Interrupt" "0,1" bitfld.long 0x8 9. "LSECSSC,LSE clock security system Interrupt" "0,1" newline bitfld.long 0x8 8. "PLL3RDYC,PLL3 ready Interrupt Clear" "0,1" bitfld.long 0x8 7. "PLL2RDYC,PLL2 ready Interrupt Clear" "0,1" newline bitfld.long 0x8 6. "PLL1RDYC,PLL1 ready Interrupt Clear" "0,1" bitfld.long 0x8 5. "RC48RDYC,RC48 ready Interrupt Clear" "0,1" newline bitfld.long 0x8 4. "HSE_ready_Interrupt_Clear,CSI ready Interrupt Clear" "0,1" bitfld.long 0x8 3. "HSERDYC,HSE ready Interrupt Clear" "0,1" newline bitfld.long 0x8 2. "HSIRDYC,HSI ready Interrupt Clear" "0,1" bitfld.long 0x8 1. "LSERDYC,LSE ready Interrupt Clear" "0,1" newline bitfld.long 0x8 0. "LSIRDYC,LSI ready Interrupt Clear" "0,1" group.long 0x70++0x7 line.long 0x0 "BDCR,RCC Backup Domain Control" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 16. "BDRST,Backup domain software reset" "0,1" bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0,1,2,3" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 16. "VSWRST,VSwitch domain software" "0,1" newline endif bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 8.--9. "RTCSRC,RTC clock source selection" "0,1,2,3" endif bitfld.long 0x0 6. "LSECSSD,LSE clock security system failure" "0,1" newline bitfld.long 0x0 5. "LSECSSON,LSE clock security system" "0,1" bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator driving" "0,1,2,3" newline bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0,1" bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1" newline bitfld.long 0x0 0. "LSEON,LSE oscillator enabled" "0,1" line.long 0x4 "CSR,RCC Clock Control and Status" bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1" bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0,1" group.long 0x7C++0x27 line.long 0x0 "AHB3RSTR,RCC AHB3 Reset Register" bitfld.long 0x0 31. "CPURST,CPU reset" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 23. "OTFD2RST,OTFD2 reset" "0,1" newline bitfld.long 0x0 22. "OTFD1RST,OTFD1 reset" "0,1" bitfld.long 0x0 21. "IOMNGRRST,OCTOSPIM reset" "0,1" newline bitfld.long 0x0 19. "OCTOSPI2RST,OCTOSPI2 and OCTOSPI2 delay block reset" "0,1" bitfld.long 0x0 14. "OCTOSPI1RST,QUADSPI and QUADSPI delay block" "0,1" newline endif bitfld.long 0x0 16. "SDMMC1RST,SDMMC1 and SDMMC1 delay block" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 14. "QSPIRST,QUADSPI and QUADSPI delay block" "0,1" endif bitfld.long 0x0 12. "FMCRST,FMC block reset" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0,1" newline endif bitfld.long 0x0 4. "DMA2DRST,DMA2D block reset" "0,1" bitfld.long 0x0 0. "MDMARST,MDMA block reset" "0,1" line.long 0x4 "AHB1RSTR,RCC AHB1 Peripheral Reset" sif (cpuis("STM32H742*")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 27. "USB2OTGRST,USB2OTG block reset" "0,1" newline endif bitfld.long 0x4 25. "USB1OTGRST,USB1OTG block reset" "0,1" bitfld.long 0x4 15. "ETH1MACRST,ETH1MAC block reset" "0,1" newline bitfld.long 0x4 5. "ADC12RST,ADC1&2 block reset" "0,1" bitfld.long 0x4 1. "DMA2RST,DMA2 block reset" "0,1" newline bitfld.long 0x4 0. "DMA1RST,DMA1 block reset" "0,1" line.long 0x8 "AHB2RSTR,RCC AHB2 Peripheral Reset" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 17. "CORDICRST,CORDIC coprocessor block reset" "0,1" bitfld.long 0x8 16. "FMACRST,FMAC reset" "0,1" newline bitfld.long 0x8 0. "DCMI_PSSIRST,DCMI_PSSIRST" "0,1" endif bitfld.long 0x8 9. "SDMMC2RST,SDMMC2 and SDMMC2 Delay block" "0,1" newline bitfld.long 0x8 6. "RNGRST,Random Number Generator block" "0,1" bitfld.long 0x8 5. "HASHRST,Hash block reset" "0,1" newline bitfld.long 0x8 4. "CRYPTRST,Cryptography block reset" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 0. "CAMITFRST,CAMITF block reset" "0,1" endif line.long 0xC "AHB4RSTR,RCC AHB4 Peripheral Reset" bitfld.long 0xC 25. "HSEMRST,HSEM block reset" "0,1" bitfld.long 0xC 24. "ADC3RST,ADC3 block reset" "0,1" newline bitfld.long 0xC 21. "BDMARST,BDMA block reset" "0,1" bitfld.long 0xC 19. "CRCRST,CRC block reset" "0,1" newline bitfld.long 0xC 10. "GPIOKRST,GPIO block reset" "0,1" bitfld.long 0xC 9. "GPIOJRST,GPIO block reset" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 8. "GPIOIRST,GPIO block reset" "0,1" newline endif bitfld.long 0xC 7. "GPIOHRST,GPIO block reset" "0,1" bitfld.long 0xC 6. "GPIOGRST,GPIO block reset" "0,1" newline bitfld.long 0xC 5. "GPIOFRST,GPIO block reset" "0,1" bitfld.long 0xC 4. "GPIOERST,GPIO block reset" "0,1" newline bitfld.long 0xC 3. "GPIODRST,GPIO block reset" "0,1" bitfld.long 0xC 2. "GPIOCRST,GPIO block reset" "0,1" newline bitfld.long 0xC 1. "GPIOBRST,GPIO block reset" "0,1" bitfld.long 0xC 0. "GPIOARST,GPIO block reset" "0,1" line.long 0x10 "APB3RSTR,RCC APB3 Peripheral Reset" bitfld.long 0x10 3. "LTDCRST,LTDC block reset" "0,1" line.long 0x14 "APB1LRSTR,RCC APB1 Peripheral Reset" bitfld.long 0x14 31. "USART8RST,USART8 block reset" "0,1" bitfld.long 0x14 30. "USART7RST,USART7 block reset" "0,1" newline bitfld.long 0x14 29. "DAC12RST,DAC1 and 2 Blocks Reset" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x14 27. "CECRST,HDMI-CEC block reset" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x14 27. "CECRST,HDMI-CEC block reset" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x14 27. "HDMICECRST,HDMI-CEC block reset" "0,1" newline endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x14 25. "I2C5RST,I2C5 block reset" "0,1" endif bitfld.long 0x14 23. "I2C3RST,I2C3 block reset" "0,1" newline bitfld.long 0x14 22. "I2C2RST,I2C2 block reset" "0,1" bitfld.long 0x14 21. "I2C1RST,I2C1 block reset" "0,1" newline bitfld.long 0x14 20. "UART5RST,UART5 block reset" "0,1" bitfld.long 0x14 19. "UART4RST,UART4 block reset" "0,1" newline bitfld.long 0x14 18. "USART3RST,USART3 block reset" "0,1" bitfld.long 0x14 17. "USART2RST,USART2 block reset" "0,1" newline bitfld.long 0x14 16. "SPDIFRXRST,SPDIFRX block reset" "0,1" bitfld.long 0x14 15. "SPI3RST,SPI3 block reset" "0,1" newline bitfld.long 0x14 14. "SPI2RST,SPI2 block reset" "0,1" bitfld.long 0x14 9. "LPTIM1RST,TIM block reset" "0,1" newline bitfld.long 0x14 8. "TIM14RST,TIM block reset" "0,1" bitfld.long 0x14 7. "TIM13RST,TIM block reset" "0,1" newline bitfld.long 0x14 6. "TIM12RST,TIM block reset" "0,1" bitfld.long 0x14 5. "TIM7RST,TIM block reset" "0,1" newline bitfld.long 0x14 4. "TIM6RST,TIM block reset" "0,1" bitfld.long 0x14 3. "TIM5RST,TIM block reset" "0,1" newline bitfld.long 0x14 2. "TIM4RST,TIM block reset" "0,1" bitfld.long 0x14 1. "TIM3RST,TIM block reset" "0,1" newline bitfld.long 0x14 0. "TIM2RST,TIM block reset" "0,1" line.long 0x18 "APB1HRSTR,RCC APB1 Peripheral Reset" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x18 25. "TIM24RST,TIM24 block resett" "0,1" bitfld.long 0x18 24. "TIM23RST,TIM23 block reset" "0,1" newline bitfld.long 0x18 2. "SWPMIRST,SWPMI block reset" "0,1" endif bitfld.long 0x18 8. "FDCANRST,FDCAN block reset" "0,1" newline bitfld.long 0x18 5. "MDIOSRST,MDIOS block reset" "0,1" bitfld.long 0x18 4. "OPAMPRST,OPAMP block reset" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 2. "SWPRST,SWPMI block reset" "0,1" newline endif bitfld.long 0x18 1. "CRSRST,Clock Recovery System" "0,1" line.long 0x1C "APB2RSTR,RCC APB2 Peripheral Reset" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x1C 30. "DFSDM1RST,DFSDM1 block reset" "0,1" bitfld.long 0x1C 7. "USART10RST,USART10 block reset" "0,1" newline bitfld.long 0x1C 6. "UART9RST,UART9 block reset" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 29. "HRTIMRST,HRTIM block reset" "0,1" newline bitfld.long 0x1C 28. "DFSDM1RST,DFSDM1 block reset" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 24. "SAI3RST,SAI3 block reset" "0,1" newline bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0,1" endif bitfld.long 0x1C 22. "SAI1RST,SAI1 block reset" "0,1" newline bitfld.long 0x1C 20. "SPI5RST,SPI5 block reset" "0,1" bitfld.long 0x1C 18. "TIM17RST,TIM17 block reset" "0,1" newline bitfld.long 0x1C 17. "TIM16RST,TIM16 block reset" "0,1" bitfld.long 0x1C 16. "TIM15RST,TIM15 block reset" "0,1" newline bitfld.long 0x1C 13. "SPI4RST,SPI4 block reset" "0,1" bitfld.long 0x1C 12. "SPI1RST,SPI1 block reset" "0,1" newline bitfld.long 0x1C 5. "USART6RST,USART6 block reset" "0,1" bitfld.long 0x1C 4. "USART1RST,USART1 block reset" "0,1" newline bitfld.long 0x1C 1. "TIM8RST,TIM8 block reset" "0,1" bitfld.long 0x1C 0. "TIM1RST,TIM1 block reset" "0,1" line.long 0x20 "APB4RSTR,RCC APB4 Peripheral Reset" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x20 26. "DTSRST,Digital temperature sensor block reset" "0,1" endif bitfld.long 0x20 21. "SAI4RST,SAI4 block reset" "0,1" newline bitfld.long 0x20 15. "VREFRST,VREF block reset" "0,1" bitfld.long 0x20 14. "COMP12RST,COMP12 Blocks Reset" "0,1" newline bitfld.long 0x20 12. "LPTIM5RST,LPTIM5 block reset" "0,1" bitfld.long 0x20 11. "LPTIM4RST,LPTIM4 block reset" "0,1" newline bitfld.long 0x20 10. "LPTIM3RST,LPTIM3 block reset" "0,1" bitfld.long 0x20 9. "LPTIM2RST,LPTIM2 block reset" "0,1" newline bitfld.long 0x20 7. "I2C4RST,I2C4 block reset" "0,1" bitfld.long 0x20 5. "SPI6RST,SPI6 block reset" "0,1" newline bitfld.long 0x20 3. "LPUART1RST,LPUART1 block reset" "0,1" bitfld.long 0x20 1. "SYSCFGRST,SYSCFG block reset" "0,1" line.long 0x24 "GCR,RCC Global Control Register" bitfld.long 0x24 0. "WW1RSC,WWDG1 reset scope control" "0,1" group.long 0xA8++0x3 line.long 0x0 "D3AMR,RCC D3 Autonomous mode" bitfld.long 0x0 29. "SRAM4AMEN,SRAM4 Autonomous mode" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" newline bitfld.long 0x0 26. "DTSAMEN,Digital temperature sensor Autonomous mode enable" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x0 28. "BKPRAMAMEN,Backup RAM Autonomous mode" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 28. "BKPRAMAMEN,Backup RAM Autonomous mode" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 28. "BKPRAMAMEN,Backup RAM Autonomous mode" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 28. "BKPSRAMAMEN,Backup RAM Autonomous mode" "0,1" endif bitfld.long 0x0 24. "ADC3AMEN,ADC3 Autonomous mode" "0,1" newline bitfld.long 0x0 21. "SAI4AMEN,SAI4 Autonomous mode" "0,1" bitfld.long 0x0 19. "CRCAMEN,CRC Autonomous mode enable" "0,1" newline bitfld.long 0x0 16. "RTCAMEN,RTC Autonomous mode enable" "0,1" bitfld.long 0x0 15. "VREFAMEN,VREF Autonomous mode" "0,1" newline bitfld.long 0x0 14. "COMP12AMEN,COMP12 Autonomous mode" "0,1" bitfld.long 0x0 12. "LPTIM5AMEN,LPTIM5 Autonomous mode" "0,1" newline bitfld.long 0x0 11. "LPTIM4AMEN,LPTIM4 Autonomous mode" "0,1" bitfld.long 0x0 10. "LPTIM3AMEN,LPTIM3 Autonomous mode" "0,1" newline bitfld.long 0x0 9. "LPTIM2AMEN,LPTIM2 Autonomous mode" "0,1" bitfld.long 0x0 7. "I2C4AMEN,I2C4 Autonomous mode" "0,1" newline bitfld.long 0x0 5. "SPI6AMEN,SPI6 Autonomous mode" "0,1" bitfld.long 0x0 3. "LPUART1AMEN,LPUART1 Autonomous mode" "0,1" newline bitfld.long 0x0 0. "BDMAAMEN,BDMA and DMAMUX Autonomous mode" "0,1" group.long 0xD0++0x27 line.long 0x0 "RSR,RCC Reset Status Register" bitfld.long 0x0 30. "LPWRRSTF,Reset due to illegal D1 DStandby or CPU" "0,1" bitfld.long 0x0 28. "WWDG1RSTF,Window Watchdog reset flag" "0,1" newline bitfld.long 0x0 26. "IWDG1RSTF,Independent Watchdog reset" "0,1" bitfld.long 0x0 24. "SFTRSTF,System reset from CPU reset" "0,1" newline bitfld.long 0x0 23. "PORRSTF,POR/PDR reset flag" "0,1" bitfld.long 0x0 22. "PINRSTF,Pin reset flag (NRST)" "0,1" newline bitfld.long 0x0 21. "BORRSTF,BOR reset flag" "0,1" bitfld.long 0x0 20. "D2RSTF,D2 domain power switch reset" "0,1" newline bitfld.long 0x0 19. "D1RSTF,D1 domain power switch reset" "0,1" bitfld.long 0x0 17. "CPURSTF,CPU reset flag" "0,1" newline bitfld.long 0x0 16. "RMVF,Remove reset flag" "0,1" line.long 0x4 "AHB3ENR,RCC AHB3 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x4 23. "OTFD2EN,OTFD2 clock enable" "0,1" bitfld.long 0x4 22. "OTFD1EN,OTFD1 clock enable" "0,1" newline bitfld.long 0x4 21. "IOMNGREN,OCTOSPIM clock enable" "0,1" bitfld.long 0x4 19. "OCTOSPI2EN,OCTOSPI2 clock enable" "0,1" newline bitfld.long 0x4 14. "OCTOSPI1EN,OCTOSPI1 and OCTOSPI1 delay clock enable" "0,1" endif bitfld.long 0x4 16. "SDMMC1EN,SDMMC1 and SDMMC1 Delay Clock" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif bitfld.long 0x4 12. "FMCEN,FMC Peripheral Clocks" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif bitfld.long 0x4 4. "DMA2DEN,DMA2D Peripheral Clock" "0,1" newline bitfld.long 0x4 0. "MDMAEN,MDMA Peripheral Clock" "0,1" line.long 0x8 "AHB1ENR,RCC AHB1 Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 26. "USB1OTGHSULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGHSEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x8 18. "USB2OTGHSULPIEN,Enable USB_PHY2 clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x8 18. "USB2OTGHSULPIEN,Enable USB_PHY2 clocks" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 18. "USB2OTGHSULPIEN,Enable USB_PHY2 clocks" "0,1" endif bitfld.long 0x8 17. "ETH1RXEN,Ethernet Reception Clock" "0,1" newline bitfld.long 0x8 16. "ETH1TXEN,Ethernet Transmission Clock" "0,1" bitfld.long 0x8 15. "ETH1MACEN,Ethernet MAC bus interface Clock" "0,1" newline bitfld.long 0x8 5. "ADC12EN,ADC1/2 Peripheral Clocks" "0,1" bitfld.long 0x8 1. "DMA2EN,DMA2 Clock Enable" "0,1" newline bitfld.long 0x8 0. "DMA1EN,DMA1 Clock Enable" "0,1" line.long 0xC "AHB2ENR,RCC AHB2 Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif bitfld.long 0xC 30. "SRAM2EN,SRAM2 block enable" "0,1" bitfld.long 0xC 29. "SRAM1EN,SRAM1 block enable" "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0xC 17. "CORDICEN,CORDIC clock enable" "0,1" bitfld.long 0xC 16. "FMACEN,FMAC clock enable" "0,1" newline bitfld.long 0xC 0. "DCMI_PSSIEN,CAMITF peripheral clock" "0,1" endif bitfld.long 0xC 9. "SDMMC2EN,SDMMC2 and SDMMC2 delay clock" "0,1" newline bitfld.long 0xC 6. "RNGEN,RNG peripheral clocks" "0,1" bitfld.long 0xC 5. "HASHEN,HASH peripheral clock" "0,1" newline bitfld.long 0xC 4. "CRYPTEN,CRYPT peripheral clock" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif line.long 0x10 "AHB4ENR,RCC AHB4 Clock Register" bitfld.long 0x10 28. "BKPRAMEN,Backup RAM Clock Enable" "0,1" bitfld.long 0x10 25. "HSEMEN,HSEM peripheral clock" "0,1" newline bitfld.long 0x10 24. "ADC3EN,ADC3 Peripheral Clocks" "0,1" bitfld.long 0x10 21. "BDMAEN,BDMA and DMAMUX2 Clock" "0,1" newline bitfld.long 0x10 19. "CRCEN,CRC peripheral clock" "0,1" bitfld.long 0x10 10. "GPIOKEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 9. "GPIOJEN,0GPIO peripheral clock" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif bitfld.long 0x10 7. "GPIOHEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 6. "GPIOGEN,0GPIO peripheral clock" "0,1" bitfld.long 0x10 5. "GPIOFEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 4. "GPIOEEN,0GPIO peripheral clock" "0,1" bitfld.long 0x10 3. "GPIODEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 2. "GPIOCEN,0GPIO peripheral clock" "0,1" bitfld.long 0x10 1. "GPIOBEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 0. "GPIOAEN,0GPIO peripheral clock" "0,1" line.long 0x14 "APB3ENR,RCC APB3 Clock Register" bitfld.long 0x14 6. "WWDG1EN,WWDG1 Clock Enable" "0,1" bitfld.long 0x14 3. "LTDCEN,LTDC peripheral clock" "0,1" line.long 0x18 "APB1LENR,RCC APB1 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x18 31. "UART8EN,UART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "UART7EN,UART7 Peripheral Clocks" "0,1" newline bitfld.long 0x18 25. "I2C5EN,I2C5 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" newline bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" endif bitfld.long 0x18 29. "DAC12EN,DAC1 and 2 peripheral clock" "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x18 27. "CECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x18 27. "CECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif bitfld.long 0x18 23. "I2C3EN,I2C3 Peripheral Clocks" "0,1" newline bitfld.long 0x18 22. "I2C2EN,I2C2 Peripheral Clocks" "0,1" bitfld.long 0x18 21. "I2C1EN,I2C1 Peripheral Clocks" "0,1" newline bitfld.long 0x18 20. "UART5EN,UART5 Peripheral Clocks" "0,1" bitfld.long 0x18 19. "UART4EN,UART4 Peripheral Clocks" "0,1" newline bitfld.long 0x18 18. "USART3EN,USART3 Peripheral Clocks" "0,1" bitfld.long 0x18 17. "USART2EN,USART2 Peripheral Clocks" "0,1" newline bitfld.long 0x18 16. "SPDIFRXEN,SPDIFRX Peripheral Clocks" "0,1" bitfld.long 0x18 15. "SPI3EN,SPI3 Peripheral Clocks" "0,1" newline bitfld.long 0x18 14. "SPI2EN,SPI2 Peripheral Clocks" "0,1" bitfld.long 0x18 9. "LPTIM1EN,LPTIM1 Peripheral Clocks" "0,1" newline bitfld.long 0x18 8. "TIM14EN,TIM peripheral clock" "0,1" bitfld.long 0x18 7. "TIM13EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 6. "TIM12EN,TIM peripheral clock" "0,1" bitfld.long 0x18 5. "TIM7EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 4. "TIM6EN,TIM peripheral clock" "0,1" bitfld.long 0x18 3. "TIM5EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 2. "TIM4EN,TIM peripheral clock" "0,1" bitfld.long 0x18 1. "TIM3EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 0. "TIM2EN,TIM peripheral clock" "0,1" line.long 0x1C "APB1HENR,RCC APB1 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x1C 25. "TIM24EN,TIM24 Peripheral Clocks" "0,1" bitfld.long 0x1C 24. "TIM23EN,TIM23 Peripheral Clocks" "0,1" newline bitfld.long 0x1C 2. "SWPMIEN,SWPMI Peripheral Clocks" "0,1" endif bitfld.long 0x1C 8. "FDCANEN,FDCAN Peripheral Clocks" "0,1" newline bitfld.long 0x1C 5. "MDIOSEN,MDIOS peripheral clock" "0,1" bitfld.long 0x1C 4. "OPAMPEN,OPAMP peripheral clock" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif bitfld.long 0x1C 1. "CRSEN,Clock Recovery System peripheral clock" "0,1" line.long 0x20 "APB2ENR,RCC APB2 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x20 30. "DFSDM1EN,DFSDM1 peripheral clocks enable" "0,1" bitfld.long 0x20 7. "USART10EN,USART10 peripheral clocks enable" "0,1" newline bitfld.long 0x20 6. "UART9EN,UART9 peripheral clocks enable" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif bitfld.long 0x20 22. "SAI1EN,SAI1 Peripheral Clocks" "0,1" newline bitfld.long 0x20 20. "SPI5EN,SPI5 Peripheral Clocks" "0,1" bitfld.long 0x20 18. "TIM17EN,TIM17 peripheral clock" "0,1" newline bitfld.long 0x20 17. "TIM16EN,TIM16 peripheral clock" "0,1" bitfld.long 0x20 16. "TIM15EN,TIM15 peripheral clock enable" "0,1" newline bitfld.long 0x20 13. "SPI4EN,SPI4 Peripheral Clocks" "0,1" bitfld.long 0x20 12. "SPI1EN,SPI1 Peripheral Clocks" "0,1" newline bitfld.long 0x20 5. "USART6EN,USART6 Peripheral Clocks" "0,1" bitfld.long 0x20 4. "USART1EN,USART1 Peripheral Clocks" "0,1" newline bitfld.long 0x20 1. "TIM8EN,TIM8 peripheral clock" "0,1" bitfld.long 0x20 0. "TIM1EN,TIM1 peripheral clock" "0,1" line.long 0x24 "APB4ENR,RCC APB4 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x24 26. "DTSEN,Digital temperature sensor peripheral clock enable" "0,1" endif bitfld.long 0x24 21. "SAI4EN,SAI4 Peripheral Clocks" "0,1" newline bitfld.long 0x24 16. "RTCAPBEN,RTC APB Clock Enable" "0,1" bitfld.long 0x24 15. "VREFEN,VREF peripheral clock" "0,1" newline bitfld.long 0x24 14. "COMP12EN,COMP1/2 peripheral clock" "0,1" bitfld.long 0x24 12. "LPTIM5EN,LPTIM5 Peripheral Clocks" "0,1" newline bitfld.long 0x24 11. "LPTIM4EN,LPTIM4 Peripheral Clocks" "0,1" bitfld.long 0x24 10. "LPTIM3EN,LPTIM3 Peripheral Clocks" "0,1" newline bitfld.long 0x24 9. "LPTIM2EN,LPTIM2 Peripheral Clocks" "0,1" bitfld.long 0x24 7. "I2C4EN,I2C4 Peripheral Clocks" "0,1" newline bitfld.long 0x24 5. "SPI6EN,SPI6 Peripheral Clocks" "0,1" bitfld.long 0x24 3. "LPUART1EN,LPUART1 Peripheral Clocks" "0,1" newline bitfld.long 0x24 1. "SYSCFGEN,SYSCFG peripheral clock" "0,1" group.long 0xFC++0x23 line.long 0x0 "AHB3LPENR,RCC AHB3 Sleep Clock Register" bitfld.long 0x0 31. "AXISRAMLPEN,AXISRAM Block Clock Enable During CSleep" "0,1" bitfld.long 0x0 30. "ITCMLPEN,D1ITCM Block Clock Enable During CSleep" "0,1" newline bitfld.long 0x0 29. "DTCM2LPEN,D1 DTCM2 Block Clock Enable During" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 28. "DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline bitfld.long 0x0 23. "OTFD2LPEN,OTFD2 block clock enable during CSleep mode" "0,1" bitfld.long 0x0 22. "OTFD1LPEN,OTFD1 block clock enable during CSleep mode" "0,1" newline bitfld.long 0x0 21. "IOMNGRLPEN,OCTOSPIM block clock enable during CSleep mode" "0,1" bitfld.long 0x0 19. "OCTO2LPEN,OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode" "0,1" newline bitfld.long 0x0 14. "OCTO1LPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif bitfld.long 0x0 16. "SDMMC1LPEN,SDMMC1 and SDMMC1 Delay Clock Enable" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif bitfld.long 0x0 12. "FMCLPEN,FMC Peripheral Clocks Enable During" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x0 8. "FLASHLPEN,Flash interface Clock Enable During CSleep Mode" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 8. "FLASHLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif bitfld.long 0x0 4. "DMA2DLPEN,DMA2D Clock Enable During CSleep" "0,1" bitfld.long 0x0 0. "MDMALPEN,MDMA Clock Enable During CSleep" "0,1" line.long 0x4 "AHB1LPENR,RCC AHB1 Sleep Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0x4 28. "USB2OTGHSULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGHSLPEN,USB2OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 28. "USB2OTGHSULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGHSLPEN,USB2OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 28. "USB2OTGHSULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGHSLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1OTGHSULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGHSLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x4 26. "USB1OTGHSULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGHSLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif bitfld.long 0x4 17. "ETH1RXLPEN,Ethernet Reception Clock Enable During" "0,1" bitfld.long 0x4 16. "ETH1TXLPEN,Ethernet Transmission Clock Enable" "0,1" newline bitfld.long 0x4 15. "ETH1MACLPEN,Ethernet MAC bus interface Clock Enable" "0,1" bitfld.long 0x4 5. "ADC12LPEN,ADC1/2 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x4 1. "DMA2LPEN,DMA2 Clock Enable During CSleep" "0,1" bitfld.long 0x4 0. "DMA1LPEN,DMA1 Clock Enable During CSleep" "0,1" line.long 0x8 "AHB2LPENR,RCC AHB2 Sleep Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif bitfld.long 0x8 30. "SRAM2LPEN,SRAM2 Clock Enable During CSleep" "0,1" bitfld.long 0x8 29. "SRAM1LPEN,SRAM1 Clock Enable During CSleep" "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 17. "CORDICLPEN,CORDIC peripheral clock enable during" "0,1" bitfld.long 0x8 16. "FMACLPEN,FMAC peripheral clock enable during" "0,1" newline bitfld.long 0x8 0. "DCMI_PSSILPEN,DCMI_PSSILPEN" "0,1" endif bitfld.long 0x8 9. "SDMMC2LPEN,SDMMC2 and SDMMC2 Delay Clock Enable" "0,1" newline bitfld.long 0x8 6. "RNGLPEN,RNG peripheral clock enable during" "0,1" bitfld.long 0x8 5. "HASHLPEN,HASH peripheral clock enable during" "0,1" newline bitfld.long 0x8 4. "CRYPTLPEN,CRYPT peripheral clock enable during" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif line.long 0xC "AHB4LPENR,RCC AHB4 Sleep Clock Register" bitfld.long 0xC 29. "SRAM4LPEN,SRAM4 Clock Enable During CSleep" "0,1" bitfld.long 0xC 28. "BKPRAMLPEN,Backup RAM Clock Enable During CSleep" "0,1" newline bitfld.long 0xC 24. "ADC3LPEN,ADC3 Peripheral Clocks Enable During" "0,1" bitfld.long 0xC 21. "BDMALPEN,BDMA Clock Enable During CSleep" "0,1" newline bitfld.long 0xC 19. "CRCLPEN,CRC peripheral clock enable during" "0,1" bitfld.long 0xC 10. "GPIOKLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 9. "GPIOJLPEN,GPIO peripheral clock enable during" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif bitfld.long 0xC 7. "GPIOHLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 6. "GPIOGLPEN,GPIO peripheral clock enable during" "0,1" bitfld.long 0xC 5. "GPIOFLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 4. "GPIOELPEN,GPIO peripheral clock enable during" "0,1" bitfld.long 0xC 3. "GPIODLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 2. "GPIOCLPEN,GPIO peripheral clock enable during" "0,1" bitfld.long 0xC 1. "GPIOBLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 0. "GPIOALPEN,GPIO peripheral clock enable during" "0,1" line.long 0x10 "APB3LPENR,RCC APB3 Sleep Clock Register" bitfld.long 0x10 6. "WWDG1LPEN,WWDG1 Clock Enable During CSleep" "0,1" bitfld.long 0x10 3. "LTDCLPEN,LTDC peripheral clock enable during" "0,1" line.long 0x14 "APB1LLPENR,RCC APB1 Low Sleep Clock" bitfld.long 0x14 31. "USART8LPEN,USART8 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 30. "USART7LPEN,USART7 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 29. "DAC12LPEN,DAC1/2 peripheral clock enable during" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x14 27. "CECLPEN,CEC Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 25. "I2C5LPEN,I2C5 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif bitfld.long 0x14 23. "I2C3LPEN,I2C3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 22. "I2C2LPEN,I2C2 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 21. "I2C1LPEN,I2C1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 20. "UART5LPEN,UART5 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 19. "UART4LPEN,UART4 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 18. "USART3LPEN,USART3 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 17. "USART2LPEN,USART2 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 16. "SPDIFRXLPEN,SPDIFRX Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 15. "SPI3LPEN,SPI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 14. "SPI2LPEN,SPI2 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 9. "LPTIM1LPEN,LPTIM1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 8. "TIM14LPEN,TIM14 peripheral clock enable during" "0,1" bitfld.long 0x14 7. "TIM13LPEN,TIM13 peripheral clock enable during" "0,1" newline bitfld.long 0x14 6. "TIM12LPEN,TIM12 peripheral clock enable during" "0,1" bitfld.long 0x14 5. "TIM7LPEN,TIM7 peripheral clock enable during" "0,1" newline bitfld.long 0x14 4. "TIM6LPEN,TIM6 peripheral clock enable during" "0,1" bitfld.long 0x14 3. "TIM5LPEN,TIM5 peripheral clock enable during" "0,1" newline bitfld.long 0x14 2. "TIM4LPEN,TIM4 peripheral clock enable during" "0,1" bitfld.long 0x14 1. "TIM3LPEN,TIM3 peripheral clock enable during" "0,1" newline bitfld.long 0x14 0. "TIM2LPEN,TIM2 peripheral clock enable during" "0,1" line.long 0x18 "APB1HLPENR,RCC APB1 High Sleep Clock" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x18 25. "TIM24LPEN,TIM24 Peripheral Clocks Enable During" "0,1" bitfld.long 0x18 24. "TIM23LPEN,TIM23 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x18 2. "SWPMILPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif bitfld.long 0x18 8. "FDCANLPEN,FDCAN Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x18 5. "MDIOSLPEN,MDIOS peripheral clock enable during" "0,1" bitfld.long 0x18 4. "OPAMPLPEN,OPAMP peripheral clock enable during" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif bitfld.long 0x18 1. "CRSLPEN,Clock Recovery System peripheral clock" "0,1" line.long 0x1C "APB2LPENR,RCC APB2 Sleep Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x1C 30. "DFSDM1LPEN,DFSDM1 peripheral clocks enable during CSleep mode" "0,1" bitfld.long 0x1C 7. "USART10LPEN,USART10 peripheral clock enable during CSleep mode" "0,1" newline bitfld.long 0x1C 6. "UART9LPEN,UART9 peripheral clock enable during CSleep mode" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif bitfld.long 0x1C 22. "SAI1LPEN,SAI1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 20. "SPI5LPEN,SPI5 Peripheral Clocks Enable During" "0,1" bitfld.long 0x1C 18. "TIM17LPEN,TIM17 peripheral clock enable during" "0,1" newline bitfld.long 0x1C 17. "TIM16LPEN,TIM16 peripheral clock enable during" "0,1" bitfld.long 0x1C 16. "TIM15LPEN,TIM15 peripheral clock enable during" "0,1" newline bitfld.long 0x1C 13. "SPI4LPEN,SPI4 Peripheral Clocks Enable During" "0,1" bitfld.long 0x1C 12. "SPI1LPEN,SPI1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 5. "USART6LPEN,USART6 Peripheral Clocks Enable During" "0,1" bitfld.long 0x1C 4. "USART1LPEN,USART1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 1. "TIM8LPEN,TIM8 peripheral clock enable during" "0,1" bitfld.long 0x1C 0. "TIM1LPEN,TIM1 peripheral clock enable during" "0,1" line.long 0x20 "APB4LPENR,RCC APB4 Sleep Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x20 26. "DTSLPEN,Digital temperature sensor peripheral clock enable during CSleep mode" "0,1" endif bitfld.long 0x20 21. "SAI4LPEN,SAI4 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 16. "RTCAPBLPEN,RTC APB Clock Enable During CSleep" "0,1" bitfld.long 0x20 15. "VREFLPEN,VREF peripheral clock enable during" "0,1" newline bitfld.long 0x20 14. "COMP12LPEN,COMP1/2 peripheral clock enable during" "0,1" bitfld.long 0x20 12. "LPTIM5LPEN,LPTIM5 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 11. "LPTIM4LPEN,LPTIM4 Peripheral Clocks Enable During" "0,1" bitfld.long 0x20 10. "LPTIM3LPEN,LPTIM3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 9. "LPTIM2LPEN,LPTIM2 Peripheral Clocks Enable During" "0,1" bitfld.long 0x20 7. "I2C4LPEN,I2C4 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 5. "SPI6LPEN,SPI6 Peripheral Clocks Enable During" "0,1" bitfld.long 0x20 3. "LPUART1LPEN,LPUART1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 1. "SYSCFGLPEN,SYSCFG peripheral clock enable during" "0,1" group.long 0x130++0x27 line.long 0x0 "C1_RSR,RCC Reset Status Register" bitfld.long 0x0 30. "LPWRRSTF,Reset due to illegal D1 DStandby or CPU" "0,1" bitfld.long 0x0 28. "WWDG1RSTF,Window Watchdog reset flag" "0,1" newline bitfld.long 0x0 26. "IWDG1RSTF,Independent Watchdog reset" "0,1" bitfld.long 0x0 24. "SFTRSTF,System reset from CPU reset" "0,1" newline bitfld.long 0x0 23. "PORRSTF,POR/PDR reset flag" "0,1" bitfld.long 0x0 22. "PINRSTF,Pin reset flag (NRST)" "0,1" newline bitfld.long 0x0 21. "BORRSTF,BOR reset flag" "0,1" bitfld.long 0x0 20. "D2RSTF,D2 domain power switch reset" "0,1" newline bitfld.long 0x0 19. "D1RSTF,D1 domain power switch reset" "0,1" bitfld.long 0x0 17. "CPURSTF,CPU reset flag" "0,1" newline bitfld.long 0x0 16. "RMVF,Remove reset flag" "0,1" line.long 0x4 "C1_AHB3ENR,RCC AHB3 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x4 23. "OTFD2EN,OTFD2 clock enable" "0,1" bitfld.long 0x4 22. "OTFD1EN,OTFD1 clock enable" "0,1" newline bitfld.long 0x4 21. "IOMNGREN,OCTOSPIM clock enable" "0,1" bitfld.long 0x4 19. "OCTOSPI2EN,OCTOSPI2 clock enable" "0,1" newline bitfld.long 0x4 14. "OCTOSPI1EN,OCTOSPI1 and OCTOSPI1 delay clock enable" "0,1" endif bitfld.long 0x4 16. "SDMMC1EN,SDMMC1 and SDMMC1 Delay Clock" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 14. "QSPIEN,QUADSPI and QUADSPI Delay Clock" "0,1" newline endif bitfld.long 0x4 12. "FMCEN,FMC Peripheral Clocks" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 5. "JPGDECEN,JPGDEC Peripheral Clock" "0,1" endif bitfld.long 0x4 4. "DMA2DEN,DMA2D Peripheral Clock" "0,1" newline bitfld.long 0x4 0. "MDMAEN,MDMA Peripheral Clock" "0,1" line.long 0x8 "C1_AHB1ENR,RCC AHB1 Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 28. "USB2ULPIEN,USB_PHY2 Clocks Enable" "0,1" bitfld.long 0x8 27. "USB2OTGEN,USB2OTG Peripheral Clocks" "0,1" newline bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 26. "USB1OTGHSULPIEN,USB_PHY1 Clocks Enable" "0,1" bitfld.long 0x8 25. "USB1OTGHSEN,USB1OTG Peripheral Clocks" "0,1" newline endif bitfld.long 0x8 17. "ETH1RXEN,Ethernet Reception Clock" "0,1" bitfld.long 0x8 16. "ETH1TXEN,Ethernet Transmission Clock" "0,1" newline bitfld.long 0x8 15. "ETH1MACEN,Ethernet MAC bus interface Clock" "0,1" bitfld.long 0x8 5. "ADC12EN,ADC1/2 Peripheral Clocks" "0,1" newline bitfld.long 0x8 1. "DMA2EN,DMA2 Clock Enable" "0,1" bitfld.long 0x8 0. "DMA1EN,DMA1 Clock Enable" "0,1" line.long 0xC "C1_AHB2ENR,RCC AHB2 Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 31. "SRAM3EN,SRAM3 block enable" "0,1" newline endif bitfld.long 0xC 30. "SRAM2EN,SRAM2 block enable" "0,1" bitfld.long 0xC 29. "SRAM1EN,SRAM1 block enable" "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0xC 17. "CORDICEN,CORDIC clock enable" "0,1" bitfld.long 0xC 16. "FMACEN,FMAC clock enable" "0,1" newline bitfld.long 0xC 0. "DCMI_PSSIEN,CAMITF peripheral clock" "0,1" endif bitfld.long 0xC 9. "SDMMC2EN,SDMMC2 and SDMMC2 delay clock" "0,1" newline bitfld.long 0xC 6. "RNGEN,RNG peripheral clocks" "0,1" bitfld.long 0xC 5. "HASHEN,HASH peripheral clock" "0,1" newline bitfld.long 0xC 4. "CRYPTEN,CRYPT peripheral clock" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 0. "CAMITFEN,CAMITF peripheral clock" "0,1" endif line.long 0x10 "C1_AHB4ENR,RCC AHB4 Clock Register" bitfld.long 0x10 28. "BKPRAMEN,Backup RAM Clock Enable" "0,1" bitfld.long 0x10 25. "HSEMEN,HSEM peripheral clock" "0,1" newline bitfld.long 0x10 24. "ADC3EN,ADC3 Peripheral Clocks" "0,1" bitfld.long 0x10 21. "BDMAEN,BDMA and DMAMUX2 Clock" "0,1" newline bitfld.long 0x10 19. "CRCEN,CRC peripheral clock" "0,1" bitfld.long 0x10 10. "GPIOKEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 9. "GPIOJEN,0GPIO peripheral clock" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x10 8. "GPIOIEN,0GPIO peripheral clock" "0,1" endif bitfld.long 0x10 7. "GPIOHEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 6. "GPIOGEN,0GPIO peripheral clock" "0,1" bitfld.long 0x10 5. "GPIOFEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 4. "GPIOEEN,0GPIO peripheral clock" "0,1" bitfld.long 0x10 3. "GPIODEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 2. "GPIOCEN,0GPIO peripheral clock" "0,1" bitfld.long 0x10 1. "GPIOBEN,0GPIO peripheral clock" "0,1" newline bitfld.long 0x10 0. "GPIOAEN,0GPIO peripheral clock" "0,1" line.long 0x14 "C1_APB3ENR,RCC APB3 Clock Register" bitfld.long 0x14 6. "WWDG1EN,WWDG1 Clock Enable" "0,1" bitfld.long 0x14 3. "LTDCEN,LTDC peripheral clock" "0,1" line.long 0x18 "C1_APB1LENR,RCC APB1 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x18 31. "UART8EN,UART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "UART7EN,UART7 Peripheral Clocks" "0,1" newline bitfld.long 0x18 27. "CECEN,HDMI-CEC peripheral clock" "0,1" bitfld.long 0x18 25. "I2C5EN,I2C5 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 31. "USART8EN,USART8 Peripheral Clocks" "0,1" bitfld.long 0x18 30. "USART7EN,USART7 Peripheral Clocks" "0,1" newline endif bitfld.long 0x18 29. "DAC12EN,DAC1 and 2 peripheral clock" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 27. "HDMICECEN,HDMI-CEC peripheral clock" "0,1" endif bitfld.long 0x18 23. "I2C3EN,I2C3 Peripheral Clocks" "0,1" newline bitfld.long 0x18 22. "I2C2EN,I2C2 Peripheral Clocks" "0,1" bitfld.long 0x18 21. "I2C1EN,I2C1 Peripheral Clocks" "0,1" newline bitfld.long 0x18 20. "UART5EN,UART5 Peripheral Clocks" "0,1" bitfld.long 0x18 19. "UART4EN,UART4 Peripheral Clocks" "0,1" newline bitfld.long 0x18 18. "USART3EN,USART3 Peripheral Clocks" "0,1" bitfld.long 0x18 17. "USART2EN,USART2 Peripheral Clocks" "0,1" newline bitfld.long 0x18 16. "SPDIFRXEN,SPDIFRX Peripheral Clocks" "0,1" bitfld.long 0x18 15. "SPI3EN,SPI3 Peripheral Clocks" "0,1" newline bitfld.long 0x18 14. "SPI2EN,SPI2 Peripheral Clocks" "0,1" bitfld.long 0x18 9. "LPTIM1EN,LPTIM1 Peripheral Clocks" "0,1" newline bitfld.long 0x18 8. "TIM14EN,TIM peripheral clock" "0,1" bitfld.long 0x18 7. "TIM13EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 6. "TIM12EN,TIM peripheral clock" "0,1" bitfld.long 0x18 5. "TIM7EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 4. "TIM6EN,TIM peripheral clock" "0,1" bitfld.long 0x18 3. "TIM5EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 2. "TIM4EN,TIM peripheral clock" "0,1" bitfld.long 0x18 1. "TIM3EN,TIM peripheral clock" "0,1" newline bitfld.long 0x18 0. "TIM2EN,TIM peripheral clock" "0,1" line.long 0x1C "C1_APB1HENR,RCC APB1 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x1C 25. "TIM24EN,TIM24 Peripheral Clocks" "0,1" bitfld.long 0x1C 24. "TIM23EN,TIM23 Peripheral Clocks" "0,1" newline bitfld.long 0x1C 2. "SWPMIEN,SWPMI Peripheral Clocks" "0,1" endif bitfld.long 0x1C 8. "FDCANEN,FDCAN Peripheral Clocks" "0,1" newline bitfld.long 0x1C 5. "MDIOSEN,MDIOS peripheral clock" "0,1" bitfld.long 0x1C 4. "OPAMPEN,OPAMP peripheral clock" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 2. "SWPEN,SWPMI Peripheral Clocks" "0,1" newline endif bitfld.long 0x1C 1. "CRSEN,Clock Recovery System peripheral clock" "0,1" line.long 0x20 "C1_APB2ENR,RCC APB2 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x20 30. "DFSDM1EN,DFSDM1 peripheral clocks enable" "0,1" bitfld.long 0x20 7. "USART10EN,USART10 peripheral clocks enable" "0,1" newline bitfld.long 0x20 6. "UART9EN,UART9 peripheral clocks enable" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x20 29. "HRTIMEN,HRTIM peripheral clock" "0,1" newline bitfld.long 0x20 28. "DFSDM1EN,DFSDM1 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x20 24. "SAI3EN,SAI3 Peripheral Clocks" "0,1" newline bitfld.long 0x20 23. "SAI2EN,SAI2 Peripheral Clocks" "0,1" endif bitfld.long 0x20 22. "SAI1EN,SAI1 Peripheral Clocks" "0,1" newline bitfld.long 0x20 20. "SPI5EN,SPI5 Peripheral Clocks" "0,1" bitfld.long 0x20 18. "TIM17EN,TIM17 peripheral clock" "0,1" newline bitfld.long 0x20 17. "TIM16EN,TIM16 peripheral clock" "0,1" bitfld.long 0x20 16. "TIM15EN,TIM15 peripheral clock enable" "0,1" newline bitfld.long 0x20 13. "SPI4EN,SPI4 Peripheral Clocks" "0,1" bitfld.long 0x20 12. "SPI1EN,SPI1 Peripheral Clocks" "0,1" newline bitfld.long 0x20 5. "USART6EN,USART6 Peripheral Clocks" "0,1" bitfld.long 0x20 4. "USART1EN,USART1 Peripheral Clocks" "0,1" newline bitfld.long 0x20 1. "TIM8EN,TIM8 peripheral clock" "0,1" bitfld.long 0x20 0. "TIM1EN,TIM1 peripheral clock" "0,1" line.long 0x24 "C1_APB4ENR,RCC APB4 Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x24 26. "DTSEN,Digital temperature sensor peripheral clock enable" "0,1" endif bitfld.long 0x24 21. "SAI4EN,SAI4 Peripheral Clocks" "0,1" newline bitfld.long 0x24 16. "RTCAPBEN,RTC APB Clock Enable" "0,1" bitfld.long 0x24 15. "VREFEN,VREF peripheral clock" "0,1" newline bitfld.long 0x24 14. "COMP12EN,COMP1/2 peripheral clock" "0,1" bitfld.long 0x24 12. "LPTIM5EN,LPTIM5 Peripheral Clocks" "0,1" newline bitfld.long 0x24 11. "LPTIM4EN,LPTIM4 Peripheral Clocks" "0,1" bitfld.long 0x24 10. "LPTIM3EN,LPTIM3 Peripheral Clocks" "0,1" newline bitfld.long 0x24 9. "LPTIM2EN,LPTIM2 Peripheral Clocks" "0,1" bitfld.long 0x24 7. "I2C4EN,I2C4 Peripheral Clocks" "0,1" newline bitfld.long 0x24 5. "SPI6EN,SPI6 Peripheral Clocks" "0,1" bitfld.long 0x24 3. "LPUART1EN,LPUART1 Peripheral Clocks" "0,1" newline bitfld.long 0x24 1. "SYSCFGEN,SYSCFG peripheral clock" "0,1" group.long 0x15C++0x23 line.long 0x0 "C1_AHB3LPENR,RCC AHB3 Sleep Clock Register" bitfld.long 0x0 31. "AXISRAMLPEN,AXISRAM Block Clock Enable During CSleep" "0,1" bitfld.long 0x0 30. "ITCMLPEN,D1ITCM Block Clock Enable During CSleep" "0,1" newline bitfld.long 0x0 29. "DTCM2LPEN,D1 DTCM2 Block Clock Enable During" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x0 28. "DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline bitfld.long 0x0 23. "OTFD2LPEN,OTFD2 block clock enable during CSleep mode" "0,1" bitfld.long 0x0 22. "OTFD1LPEN,OTFD1 block clock enable during CSleep mode" "0,1" newline bitfld.long 0x0 21. "IOMNGRLPEN,OCTOSPIM block clock enable during CSleep mode" "0,1" bitfld.long 0x0 19. "OCTO2LPEN,OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode" "0,1" newline bitfld.long 0x0 14. "OCTO1LPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" bitfld.long 0x0 8. "FLASHLPEN,Flash interface Clock Enable During CSleep Mode" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 28. "D1DTCM1LPEN,D1DTCM1 Block Clock Enable During CSleep" "0,1" newline endif bitfld.long 0x0 16. "SDMMC1LPEN,SDMMC1 and SDMMC1 Delay Clock Enable" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 14. "QSPILPEN,QUADSPI and QUADSPI Delay Clock Enable" "0,1" endif bitfld.long 0x0 12. "FMCLPEN,FMC Peripheral Clocks Enable During" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 8. "FLITFLPEN,FLITF Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC Clock Enable During CSleep" "0,1" newline endif bitfld.long 0x0 4. "DMA2DLPEN,DMA2D Clock Enable During CSleep" "0,1" bitfld.long 0x0 0. "MDMALPEN,MDMA Clock Enable During CSleep" "0,1" line.long 0x4 "C1_AHB1LPENR,RCC AHB1 Sleep Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x4 28. "USB2ULPILPEN,USB_PHY2 clocks enable during CSleep" "0,1" bitfld.long 0x4 27. "USB2OTGLPEN,USB2OTG peripheral clock enable during" "0,1" newline bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x4 26. "USB1OTGHSULPILPEN,USB_PHY1 clock enable during CSleep" "0,1" bitfld.long 0x4 25. "USB1OTGHSLPEN,USB1OTG peripheral clock enable during" "0,1" newline endif bitfld.long 0x4 17. "ETH1RXLPEN,Ethernet Reception Clock Enable During" "0,1" bitfld.long 0x4 16. "ETH1TXLPEN,Ethernet Transmission Clock Enable" "0,1" newline bitfld.long 0x4 15. "ETH1MACLPEN,Ethernet MAC bus interface Clock Enable" "0,1" bitfld.long 0x4 5. "ADC12LPEN,ADC1/2 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x4 1. "DMA2LPEN,DMA2 Clock Enable During CSleep" "0,1" bitfld.long 0x4 0. "DMA1LPEN,DMA1 Clock Enable During CSleep" "0,1" line.long 0x8 "C1_AHB2LPENR,RCC AHB2 Sleep Clock Register" sif (cpuis("STM32H742*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 31. "SRAM3LPEN,SRAM3 Clock Enable During CSleep" "0,1" newline endif bitfld.long 0x8 30. "SRAM2LPEN,SRAM2 Clock Enable During CSleep" "0,1" bitfld.long 0x8 29. "SRAM1LPEN,SRAM1 Clock Enable During CSleep" "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 17. "CORDICLPEN,CORDIC peripheral clock enable during" "0,1" bitfld.long 0x8 16. "FMACLPEN,FMAC peripheral clock enable during" "0,1" newline bitfld.long 0x8 0. "DCMI_PSSILPEN,DCMI_PSSILPEN" "0,1" endif bitfld.long 0x8 9. "SDMMC2LPEN,SDMMC2 and SDMMC2 Delay Clock Enable" "0,1" newline bitfld.long 0x8 6. "RNGLPEN,RNG peripheral clock enable during" "0,1" bitfld.long 0x8 5. "HASHLPEN,HASH peripheral clock enable during" "0,1" newline bitfld.long 0x8 4. "CRYPTLPEN,CRYPT peripheral clock enable during" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x8 0. "CAMITFLPEN,CAMITF peripheral clock enable during" "0,1" endif line.long 0xC "C1_AHB4LPENR,RCC AHB4 Sleep Clock Register" bitfld.long 0xC 29. "SRAM4LPEN,SRAM4 Clock Enable During CSleep" "0,1" bitfld.long 0xC 28. "BKPRAMLPEN,Backup RAM Clock Enable During CSleep" "0,1" newline bitfld.long 0xC 24. "ADC3LPEN,ADC3 Peripheral Clocks Enable During" "0,1" bitfld.long 0xC 21. "BDMALPEN,BDMA Clock Enable During CSleep" "0,1" newline bitfld.long 0xC 19. "CRCLPEN,CRC peripheral clock enable during" "0,1" bitfld.long 0xC 10. "GPIOKLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 9. "GPIOJLPEN,GPIO peripheral clock enable during" "0,1" sif (cpuis("STM32H742*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0xC 8. "GPIOILPEN,GPIO peripheral clock enable during" "0,1" endif bitfld.long 0xC 7. "GPIOHLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 6. "GPIOGLPEN,GPIO peripheral clock enable during" "0,1" bitfld.long 0xC 5. "GPIOFLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 4. "GPIOELPEN,GPIO peripheral clock enable during" "0,1" bitfld.long 0xC 3. "GPIODLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 2. "GPIOCLPEN,GPIO peripheral clock enable during" "0,1" bitfld.long 0xC 1. "GPIOBLPEN,GPIO peripheral clock enable during" "0,1" newline bitfld.long 0xC 0. "GPIOALPEN,GPIO peripheral clock enable during" "0,1" line.long 0x10 "C1_APB3LPENR,RCC APB3 Sleep Clock Register" bitfld.long 0x10 6. "WWDG1LPEN,WWDG1 Clock Enable During CSleep" "0,1" bitfld.long 0x10 3. "LTDCLPEN,LTDC peripheral clock enable during" "0,1" line.long 0x14 "C1_APB1LLPENR,RCC APB1 Low Sleep Clock" bitfld.long 0x14 31. "USART8LPEN,USART8 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 30. "USART7LPEN,USART7 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 29. "DAC12LPEN,DAC1/2 peripheral clock enable during" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x14 27. "CECLPEN,CEC Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 25. "I2C5LPEN,I2C5 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H743*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x14 27. "HDMICECLPEN,HDMI-CEC Peripheral Clocks Enable During" "0,1" endif bitfld.long 0x14 23. "I2C3LPEN,I2C3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 22. "I2C2LPEN,I2C2 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 21. "I2C1LPEN,I2C1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 20. "UART5LPEN,UART5 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 19. "UART4LPEN,UART4 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 18. "USART3LPEN,USART3 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 17. "USART2LPEN,USART2 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 16. "SPDIFRXLPEN,SPDIFRX Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 15. "SPI3LPEN,SPI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 14. "SPI2LPEN,SPI2 Peripheral Clocks Enable During" "0,1" bitfld.long 0x14 9. "LPTIM1LPEN,LPTIM1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x14 8. "TIM14LPEN,TIM14 peripheral clock enable during" "0,1" bitfld.long 0x14 7. "TIM13LPEN,TIM13 peripheral clock enable during" "0,1" newline bitfld.long 0x14 6. "TIM12LPEN,TIM12 peripheral clock enable during" "0,1" bitfld.long 0x14 5. "TIM7LPEN,TIM7 peripheral clock enable during" "0,1" newline bitfld.long 0x14 4. "TIM6LPEN,TIM6 peripheral clock enable during" "0,1" bitfld.long 0x14 3. "TIM5LPEN,TIM5 peripheral clock enable during" "0,1" newline bitfld.long 0x14 2. "TIM4LPEN,TIM4 peripheral clock enable during" "0,1" bitfld.long 0x14 1. "TIM3LPEN,TIM3 peripheral clock enable during" "0,1" newline bitfld.long 0x14 0. "TIM2LPEN,TIM2 peripheral clock enable during" "0,1" line.long 0x18 "C1_APB1HLPENR,RCC APB1 High Sleep Clock" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x18 25. "TIM24LPEN,TIM24 Peripheral Clocks Enable During" "0,1" bitfld.long 0x18 24. "TIM23LPEN,TIM23 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x18 2. "SWPMILPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif bitfld.long 0x18 8. "FDCANLPEN,FDCAN Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x18 5. "MDIOSLPEN,MDIOS peripheral clock enable during" "0,1" bitfld.long 0x18 4. "OPAMPLPEN,OPAMP peripheral clock enable during" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x18 2. "SWPLPEN,SWPMI Peripheral Clocks Enable During" "0,1" newline endif bitfld.long 0x18 1. "CRSLPEN,Clock Recovery System peripheral clock" "0,1" line.long 0x1C "C1_APB2LPENR,RCC APB2 Sleep Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x1C 30. "DFSDM1LPEN,DFSDM1 peripheral clocks enable during CSleep mode" "0,1" bitfld.long 0x1C 7. "USART10LPEN,USART10 peripheral clock enable during CSleep mode" "0,1" newline bitfld.long 0x1C 6. "UART9LPEN,UART9 peripheral clock enable during CSleep mode" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 29. "HRTIMLPEN,HRTIM peripheral clock enable during" "0,1" newline bitfld.long 0x1C 28. "DFSDM1LPEN,DFSDM1 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H742*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x1C 24. "SAI3LPEN,SAI3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 23. "SAI2LPEN,SAI2 Peripheral Clocks Enable During" "0,1" endif bitfld.long 0x1C 22. "SAI1LPEN,SAI1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 20. "SPI5LPEN,SPI5 Peripheral Clocks Enable During" "0,1" bitfld.long 0x1C 18. "TIM17LPEN,TIM17 peripheral clock enable during" "0,1" newline bitfld.long 0x1C 17. "TIM16LPEN,TIM16 peripheral clock enable during" "0,1" bitfld.long 0x1C 16. "TIM15LPEN,TIM15 peripheral clock enable during" "0,1" newline bitfld.long 0x1C 13. "SPI4LPEN,SPI4 Peripheral Clocks Enable During" "0,1" bitfld.long 0x1C 12. "SPI1LPEN,SPI1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 5. "USART6LPEN,USART6 Peripheral Clocks Enable During" "0,1" bitfld.long 0x1C 4. "USART1LPEN,USART1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x1C 1. "TIM8LPEN,TIM8 peripheral clock enable during" "0,1" bitfld.long 0x1C 0. "TIM1LPEN,TIM1 peripheral clock enable during" "0,1" line.long 0x20 "C1_APB4LPENR,RCC APB4 Sleep Clock Register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x20 26. "DTSLPEN,Digital temperature sensor peripheral clock enable during CSleep mode" "0,1" endif bitfld.long 0x20 21. "SAI4LPEN,SAI4 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 16. "RTCAPBLPEN,RTC APB Clock Enable During CSleep" "0,1" bitfld.long 0x20 15. "VREFLPEN,VREF peripheral clock enable during" "0,1" newline bitfld.long 0x20 14. "COMP12LPEN,COMP1/2 peripheral clock enable during" "0,1" bitfld.long 0x20 12. "LPTIM5LPEN,LPTIM5 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 11. "LPTIM4LPEN,LPTIM4 Peripheral Clocks Enable During" "0,1" bitfld.long 0x20 10. "LPTIM3LPEN,LPTIM3 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 9. "LPTIM2LPEN,LPTIM2 Peripheral Clocks Enable During" "0,1" bitfld.long 0x20 7. "I2C4LPEN,I2C4 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 5. "SPI6LPEN,SPI6 Peripheral Clocks Enable During" "0,1" bitfld.long 0x20 3. "LPUART1LPEN,LPUART1 Peripheral Clocks Enable During" "0,1" newline bitfld.long 0x20 1. "SYSCFGLPEN,SYSCFG peripheral clock enable during" "0,1" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI calibration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" group.long 0xC++0x3 line.long 0x0 "CSICFGR,RCC CSI calibration register" hexmask.long.byte 0x0 24.--29. 1. "CSITRIM,CSI clock trimming" hexmask.long.word 0x0 0.--9. 1. "CSICAL,CSI clock calibration" endif sif (cpuis("STM32H742*")) group.long 0x4++0x3 line.long 0x0 "ICSCR,RCC Internal Clock Source Calibration" hexmask.long.byte 0x0 26.--30. 1. "CSITRIM,CSI clock trimming" hexmask.long.byte 0x0 18.--25. 1. "CSICAL,CSI clock calibration" newline hexmask.long.byte 0x0 12.--17. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H743*")) group.long 0x4++0x3 line.long 0x0 "ICSCR,RCC Internal Clock Source Calibration" hexmask.long.byte 0x0 26.--30. 1. "CSITRIM,CSI clock trimming" hexmask.long.byte 0x0 18.--25. 1. "CSICAL,CSI clock calibration" newline hexmask.long.byte 0x0 12.--17. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H745??-CM4")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H745??-CM7")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H747??-CM4")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H747??-CM7")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H750*")) group.long 0x4++0x3 line.long 0x0 "ICSCR,RCC Internal Clock Source Calibration" hexmask.long.byte 0x0 26.--30. 1. "CSITRIM,CSI clock trimming" hexmask.long.byte 0x0 18.--25. 1. "CSICAL,CSI clock calibration" newline hexmask.long.byte 0x0 12.--17. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H753*")) group.long 0x4++0x3 line.long 0x0 "ICSCR,RCC Internal Clock Source Calibration" hexmask.long.byte 0x0 26.--30. 1. "CSITRIM,CSI clock trimming" hexmask.long.byte 0x0 18.--25. 1. "CSICAL,CSI clock calibration" newline hexmask.long.byte 0x0 12.--17. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H755??-CM4")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H755??-CM7")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H757??-CM4")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H757??-CM7")) group.long 0x4++0x3 line.long 0x0 "HSICFGR,RCC HSI configuration register" hexmask.long.byte 0x0 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x0 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x7 line.long 0x0 "RCC_CR," rbitfld.long 0x0 29. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked (default after reset),1: PLL3 locked" bitfld.long 0x0 28. "PLL3ON,PLL3 enable" "0: PLL3 OFF (default after reset),1: PLL3 ON" newline rbitfld.long 0x0 27. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked (default after reset),1: PLL2 locked" bitfld.long 0x0 26. "PLL2ON,PLL2 enable" "0: PLL2 OFF (default after reset),1: PLL2 ON" newline rbitfld.long 0x0 25. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked (default after reset),1: PLL1 locked" bitfld.long 0x0 24. "PLL1ON,PLL1 enable" "0: PLL1 OFF (default after reset),1: PLL1 ON" newline bitfld.long 0x0 20. "HSEEXT,external high speed clock type in Bypass mode" "0: HSE in analog mode (default after reset),1: HSE in digital mode" bitfld.long 0x0 19. "HSECSSON,HSE clock security system enable" "0: CSS on HSE OFF (clock detector OFF) (default..,1: CSS on HSE ON (clock detector ON if the HSE.." newline bitfld.long 0x0 18. "HSEBYP,HSE clock bypass" "0: HSE oscillator not bypassed (default after reset),1: HSE oscillator bypassed with an external clock" rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE clock is not ready (default after reset),1: HSE clock is ready" newline bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE is OFF (default after reset),1: HSE is ON" rbitfld.long 0x0 15. "CDCKRDY,CPU domain clocks ready flag" "0: CPU domain clocks are not available (default..,1: CPU domain clocks are available" newline rbitfld.long 0x0 14. "CPUCKRDY,CPU related clocks ready flag" "0: CPU related clocks are not available (default..,1: CPU related clocks are available" rbitfld.long 0x0 13. "HSI48RDY,HSI48 clock ready flag" "0: HSI48 clock is not ready (default after reset),1: HSI48 clock is ready" newline bitfld.long 0x0 12. "HSI48ON,HSI48 clock enable" "0: HSI48 is OFF (default after reset),1: HSI48 is ON" bitfld.long 0x0 9. "CSIKERON,CSI clock enable in Stop mode" "0: no effect on CSI (default after reset),1: CSI is forced to ON even in Stop mode" newline rbitfld.long 0x0 8. "CSIRDY,CSI clock ready flag" "0: CSI clock is not ready (default after reset),1: CSI clock is ready" bitfld.long 0x0 7. "CSION,CSI clock enable" "0: CSI is OFF (default after reset),1: CSI is ON" newline rbitfld.long 0x0 5. "HSIDIVF,HSI divider flag" "0: new division ratio not yet propagated to..,1: hsi(_ker)_ck clock frequency reflects the new.." bitfld.long 0x0 3.--4. "HSIDIV,HSI clock divider" "0: division by 1 hsi(_ker)_ck = 64 MHz (default..,1: division by 2 hsi(_ker)_ck = 32 MHz,2: division by 4 hsi(_ker)_ck = 16 MHz,3: division by 8 hsi(_ker)_ck = 8 MHz" newline rbitfld.long 0x0 2. "HSIRDY,HSI clock ready flag" "0: HSI clock is not ready (default after reset),1: HSI clock is ready" bitfld.long 0x0 1. "HSIKERON,HSI clock enable in Stop mode" "0: no effect on HSI (default after reset),1: HSI is forced to ON even in Stop mode" newline bitfld.long 0x0 0. "HSION,HSI clock enable" "0: HSI is OFF,1: HSI is ON (default after reset)" line.long 0x4 "RCC_HSICFGR,RCC HSI calibration register" hexmask.long.byte 0x4 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x4 0.--11. 1. "HSICAL,HSI clock calibration" endif sif (cpuis("STM32H742*")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H743*")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H745??-CM4")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H745??-CM7")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H747??-CM4")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H747??-CM7")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H750*")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H753*")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H755??-CM4")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H755??-CM7")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H757??-CM4")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H757??-CM7")) rgroup.long 0x8++0x3 line.long 0x0 "CRRCR,RCC Clock Recovery RC Register" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x8++0x3 line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register" hexmask.long.word 0x0 0.--9. 1. "HSI48CAL,Internal RC 48 MHz clock calibration" group.long 0xC++0x7 line.long 0x0 "RCC_CSICFGR,RCC CSI calibration register" hexmask.long.byte 0x0 24.--29. 1. "CSITRIM,CSI clock trimming" hexmask.long.byte 0x0 0.--7. 1. "CSICAL,CSI clock calibration" line.long 0x4 "RCC_CFGR," bitfld.long 0x4 29.--31. "MCO2SEL,microcontroller clock output 2" "0: system clock selected (sys_ck) (default after..,1: PLL2 oscillator clock selected (pll2_p_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_p_ck),4: CSI clock selected (csi_ck),5: LSI clock selected (lsi_ck),?,?" hexmask.long.byte 0x4 25.--28. 1. "MCO2PRE,MCO2 prescaler" newline bitfld.long 0x4 22.--24. "MCO1SEL,Microcontroller clock output 1" "0: HSI clock selected (hsi_ck) (default after reset),1: LSE oscillator clock selected (lse_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_q_ck),4: HSI48 clock selected (hsi48_ck),?,?,?" hexmask.long.byte 0x4 18.--21. 1. "MCO1PRE,MCO1 prescaler" newline bitfld.long 0x4 15. "TIMPRE,timers clocks prescaler selection" "0: The timers kernel clock is equal to rcc_hclk1 if..,1: The timers kernel clock is equal to 2 x.." hexmask.long.byte 0x4 8.--13. 1. "RTCPRE,HSE division factor for RTC clock" newline bitfld.long 0x4 7. "STOPKERWUCK,kernel clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" bitfld.long 0x4 6. "STOPWUCK,system clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" newline rbitfld.long 0x4 3.--5. "SWS,system clock switch status" "0: HSI used as system clock (hsi_ck) (default after..,1: CSI used as system clock (csi_ck),2: HSE used as system clock (hse_ck),3: PLL1 used as system clock (pll1_p_ck),?,?,?,?" bitfld.long 0x4 0.--2. "SW,system clock and trace clock switch" "0: HSI selected as system clock (hsi_ck) (default..,1: CSI selected as system clock (csi_ck),2: HSE selected as system clock (hse_ck),3: PLL1 selected as system clock (pll1_p_ck for..,?,?,?,?" group.long 0x18++0xB line.long 0x0 "RCC_CDCFGR1," hexmask.long.byte 0x0 8.--11. 1. "CDCPRE,CPU domain core prescaler" bitfld.long 0x0 4.--6. "CDPPRE,CPU domain APB3 prescaler" "?,?,?,?,4: rcc_pclk3 = rcc_hclk3 / 2,5: rcc_pclk3 = rcc_hclk3 / 4,6: rcc_pclk3 = rcc_hclk3 / 8,7: rcc_pclk3 = rcc_hclk3 / 16" newline hexmask.long.byte 0x0 0.--3. 1. "HPRE,CPU domain AHB prescaler" line.long 0x4 "RCC_CDCFGR2," bitfld.long 0x4 8.--10. "CDPPRE2,CPU domain APB2 prescaler" "?,?,?,?,4: rcc_pclk2 = rcc_hclk1 / 2,5: rcc_pclk2 = rcc_hclk1 / 4,6: rcc_pclk2 = rcc_hclk1 / 8,7: rcc_pclk2 = rcc_hclk1 / 16" bitfld.long 0x4 4.--6. "CDPPRE1,CPU domain APB1 prescaler" "?,?,?,?,4: rcc_pclk1 = rcc_hclk1 / 2,5: rcc_pclk1 = rcc_hclk1 / 4,6: rcc_pclk1 = rcc_hclk1 / 8,7: rcc_pclk1 = rcc_hclk1 / 16" line.long 0x8 "RCC_SRDCFGR," bitfld.long 0x8 4.--6. "SRDPPRE,SmartRun domain APB4 prescaler" "?,?,?,?,4: rcc_pclk4 = rcc_hclk4 / 2,5: rcc_pclk4 = rcc_hclk4 / 4,6: rcc_pclk4 = rcc_hclk4 / 8,7: rcc_pclk4 = rcc_hclk4 / 16" group.long 0x28++0x1F line.long 0x0 "RCC_PLLCKSELR," hexmask.long.byte 0x0 20.--25. 1. "DIVM3,prescaler for PLL3" hexmask.long.byte 0x0 12.--17. 1. "DIVM2,prescaler for PLL2" newline hexmask.long.byte 0x0 4.--9. 1. "DIVM1,prescaler for PLL1" bitfld.long 0x0 0.--1. "PLLSRC,DIVMx and PLLs clock source selection" "0: HSI selected as PLL clock (hsi_ck) (default..,1: CSI selected as PLL clock (csi_ck),2: HSE selected as PLL clock (hse_ck),3: no clock send to DIVMx divider and PLLs" line.long 0x4 "RCC_PLLCFGR," bitfld.long 0x4 24. "DIVR3EN,PLL3 DIVR divider output enable" "0: pll3_r_ck output disabled,1: pll3_r_ck output enabled (default after reset)" bitfld.long 0x4 23. "DIVQ3EN,PLL3 DIVQ divider output enable" "0: pll3_q_ck output disabled,1: pll3_q_ck output enabled (default after reset)" newline bitfld.long 0x4 22. "DIVP3EN,PLL3 DIVP divider output enable" "0: pll3_p_ck output disabled,1: pll3_p_ck output enabled (default after reset)" bitfld.long 0x4 21. "DIVR2EN,PLL2 DIVR divider output enable" "0: pll2_r_ck output disabled,1: pll2_r_ck output enabled (default after reset)" newline bitfld.long 0x4 20. "DIVQ2EN,PLL2 DIVQ divider output enable" "0: pll2_q_ck output disabled,1: pll2_q_ck output enabled (default after reset)" bitfld.long 0x4 19. "DIVP2EN,PLL2 DIVP divider output enable" "0: pll2_p_ck output disabled,1: pll2_p_ck output enabled (default after reset)" newline bitfld.long 0x4 18. "DIVR1EN,PLL1 DIVR divider output enable" "0: pll1_r_ck output disabled,1: pll1_r_ck output enabled (default after reset)" bitfld.long 0x4 17. "DIVQ1EN,PLL1 DIVQ divider output enable" "0: pll1_q_ck output disabled,1: pll1_q_ck output enabled (default after reset)" newline bitfld.long 0x4 16. "DIVP1EN,PLL1 DIVP divider output enable" "0: pll1_p_ck output disabled,1: pll1_p_ck output enabled (default after reset)" bitfld.long 0x4 10.--11. "PLL3RGE,PLL3 input frequency range" "0: PLL3 input (ref3_ck) clock range frequency..,1: PLL3 input (ref3_ck) clock range frequency..,2: PLL3 input (ref3_ck) clock range frequency..,3: PLL3 input (ref3_ck) clock range frequency.." newline bitfld.long 0x4 9. "PLL3VCOSEL,PLL3 VCO selection" "0: wide VCO range 128 to 560 MHz (default after..,1: medium VCO range 150 to 420 MHz" bitfld.long 0x4 8. "PLL3FRACEN,PLL3 fractional latch enable" "0,1" newline bitfld.long 0x4 6.--7. "PLL2RGE,PLL2 input frequency range" "0: PLL2 input (ref2_ck) clock range frequency..,1: PLL2 input (ref2_ck) clock range frequency..,2: PLL2 input (ref2_ck) clock range frequency..,3: PLL2 input (ref2_ck) clock range frequency.." bitfld.long 0x4 5. "PLL2VCOSEL,PLL2 VCO selection" "0: wide VCO range 128 to 560 MHz (default after..,1: medium VCO range 150 to 420 MHz" newline bitfld.long 0x4 4. "PLL2FRACEN,PLL2 fractional latch enable" "0,1" bitfld.long 0x4 2.--3. "PLL1RGE,PLL1 input frequency range" "0: PLL1 input (ref1_ck) clock range frequency..,1: PLL1 input (ref1_ck) clock range frequency..,2: PLL1 input (ref1_ck) clock range frequency..,3: PLL1 input (ref1_ck) clock range frequency.." newline bitfld.long 0x4 1. "PLL1VCOSEL,PLL1 VCO selection" "0: wide VCO range from 128 to 560 MHz (default..,1: medium VCO range from 150 to 420 MHz" bitfld.long 0x4 0. "PLL1FRACEN,PLL1 fractional latch enable" "0,1" line.long 0x8 "RCC_PLL1DIVR," hexmask.long.byte 0x8 24.--30. 1. "DIVR1,PLL1 DIVR division factor" hexmask.long.byte 0x8 16.--22. 1. "DIVQ1,PLL1 DIVQ division factor" newline hexmask.long.byte 0x8 9.--15. 1. "DIVP1,PLL1 DIVP division factor" hexmask.long.word 0x8 0.--8. 1. "DIVN1,multiplication factor for PLL1 VCO" line.long 0xC "RCC_PLL1FRACR," hexmask.long.word 0xC 3.--15. 1. "FRACN1,fractional part of the multiplication factor for PLL1 VCO" line.long 0x10 "RCC_PLL2DIVR," hexmask.long.byte 0x10 24.--30. 1. "DIVR2,PLL2 DIVR division factor" hexmask.long.byte 0x10 16.--22. 1. "DIVQ2,PLL2 DIVQ division factor" newline hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL2 DIVP division factor" hexmask.long.word 0x10 0.--8. 1. "DIVN2,multiplication factor for PLL2 VCO" line.long 0x14 "RCC_PLL2FRACR," hexmask.long.word 0x14 3.--15. 1. "FRACN2,fractional part of the multiplication factor for PLL2 VCO" line.long 0x18 "RCC_PLL3DIVR," hexmask.long.byte 0x18 24.--30. 1. "DIVR3,PLL3 DIVR division factor" hexmask.long.byte 0x18 16.--22. 1. "DIVQ3,PLL3 DIVQ division factor" newline hexmask.long.byte 0x18 9.--15. 1. "DIVP3,PLL3 DIVP division factor" hexmask.long.word 0x18 0.--8. 1. "DIVN3,Multiplication factor for PLL3 VCO" line.long 0x1C "RCC_PLL3FRACR," hexmask.long.word 0x1C 3.--15. 1. "FRACN3,fractional part of the multiplication factor for PLL3 VCO" group.long 0x4C++0xF line.long 0x0 "RCC_CDCCIPR,RCC CPU domain kernel clock configuration register" bitfld.long 0x0 28.--29. "CKPERSEL,per_ck clock source selection" "0: hsi_ker_ck selected as per_ck clock (default..,1: csi_ker_ck selected as per_ck clock,2: hse_ck selected as per_ck clock,3: reserved the per_ck clock is disabled" bitfld.long 0x0 16. "SDMMCSEL,SDMMC kernel clock source selection" "0: pll1_q_ck selected as kernel peripheral clock..,1: pll2_r_ck selected as kernel peripheral clock" newline bitfld.long 0x0 4.--5. "OCTOSPISEL,OCTOSPI kernel clock source selection" "0: rcc_hclk3 selected as kernel peripheral clock..,1: pll1_q_ck selected as kernel peripheral clock,2: pll2_r_ck selected as kernel peripheral clock,3: per_ck selected as kernel peripheral clock" bitfld.long 0x0 0.--1. "FMCSEL,FMC kernel clock source selection" "0: rcc_hclk3 selected as kernel peripheral clock..,1: pll1_q_ck selected as kernel peripheral clock,2: pll2_r_ck selected as kernel peripheral clock,3: per_ck selected as kernel peripheral clock" line.long 0x4 "RCC_CDCCIP1R,RCC CPU domain kernel clock configuration register" bitfld.long 0x4 31. "SWPMISEL,SWPMI kernel clock source selection" "0: rcc_pclk1 selected as SWPMI kernel clock..,1: hsi_ker_ck selected as SWPMI kernel clock" bitfld.long 0x4 28.--29. "FDCANSEL,FDCAN kernel clock source selection" "0: hse_ck clock selected as FDCAN kernel clock..,1: pll1_q_ck selected as FDCAN kernel clock,2: pll2_q_ck selected as FDCAN kernel clock,3: reserved the kernel clock is disabled" newline bitfld.long 0x4 24. "DFSDM1SEL,DFSDM1 kernel clock Clk source selection" "0: rcc_pclk2 selected as DFSDM1 Clk kernel clock..,1: sys_ck selected as DFSDM1 Clk kernel clock" bitfld.long 0x4 20.--21. "SPDIFRXSEL,SPDIFRX kernel clock source selection" "0: pll1_q_ck selected as SPDIFRX kernel clock..,1: pll2_r_ck selected as SPDIFRX kernel clock,2: pll3_r_ck selected as SPDIFRX kernel clock,3: hsi_ker_ck selected as SPDIFRX kernel clock" newline bitfld.long 0x4 16.--18. "SPI45SEL,SPI4 and 5 kernel clock source selection" "0: rcc_pclk2 clock selected as kernel clock..,1: pll2_q_ck is selected as kernel clock,2: pll3_q_ck is selected as kernel clock,3: hsi_ker_ck is selected as kernel clock,4: csi_ker_ck is selected as kernel clock,5: hse_ck is selected as kernel clock,?,?" bitfld.long 0x4 12.--14. "SPI123SEL,SPI/I2S1 2 and 3 kernel clock source selection" "0: pll1_q_ck selected as SPI/I2S1 2 and 3 kernel..,1: pll2_p_ck selected as SPI/I2S1 2 and 3 kernel..,2: pll3_p_ck selected as SPI/I2S1 2 and 3 kernel..,3: I2S_CKIN selected as SPI/I2S1 2 and 3 kernel clock,4: per_ck selected as SPI/I2S1 2 and 3 kernel clock,?,?,?" newline bitfld.long 0x4 9.--11. "SAI2BSEL,SAI2 kernel clock B source selection" "0: pll1_q_ck selected as SAI2 kernel clock B..,1: pll2_p_ck selected as SAI2 kernel clock B,2: pll3_p_ck selected as SAI2 kernel clock B,3: I2S_CKIN selected as SAI2 kernel clock B,4: per_ck selected as SAI2 kernel clock B,5: spdifrx_symb_ck selected as SAI2 kernel clock B,?,?" bitfld.long 0x4 6.--8. "SAI2ASEL,SAI2 kernel clock source A selection" "0: pll1_q_ck selected as SAI2 kernel clock A..,1: pll2_p_ck selected as SAI2 kernel clock A,2: pll3_p_ck selected as SAI2 kernel clock A,3: I2S_CKIN selected as SAI2 kernel clock A,4: per_ck selected as SAI2 kernel clock A,5: spdifrx_symb_ck selected as SAI2 kernel clock A,?,?" newline bitfld.long 0x4 0.--2. "SAI1SEL,SAI1 and DFSDM1 kernel Aclk clock source selection" "0: pll1_q_ck selected as SAI1 and DFSDM1 Aclk..,1: pll2_p_ck selected as SAI1 and DFSDM1 Aclk..,2: pll3_p_ck selected as SAI1 and DFSDM1 Aclk..,3: I2S_CKIN selected as SAI1 and DFSDM1 Aclk kernel..,4: per_ck selected as SAI1 and DFSDM1 Aclk kernel..,?,?,?" line.long 0x8 "RCC_CDCCIP2R,RCC CPU domain kernel clock configuration register" bitfld.long 0x8 28.--30. "LPTIM1SEL,LPTIM1 kernel clock source selection" "0: rcc_pclk1 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" bitfld.long 0x8 22.--23. "CECSEL,HDMI-CEC kernel clock source selection" "0: lse_ck selected as kernel clock (default after..,1: lsi_ck selected as kernel clock,2: csi_ker_ck divided by 122 selected as kernel..,3: reserved the kernel clock is disabled" newline bitfld.long 0x8 20.--21. "USBSEL,USBOTG 1 and 2 kernel clock source selection" "0: Disable the kernel clock (default after reset),1: pll1_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi48_ck selected as kernel clock" bitfld.long 0x8 12.--13. "I2C123SEL,I2C1 2 3 kernel clock source selection" "0: rcc_pclk1 selected as kernel clock (default..,1: pll3_r_ck selected as kernel clock,2: hsi_ker_ck selected as kernel clock,3: csi_ker_ck selected as kernel clock" newline bitfld.long 0x8 8.--9. "RNGSEL,RNG kernel clock source selection" "0: hsi48_ck selected as kernel clock (default after..,1: pll1_q_ck selected as kernel clock,2: lse_ck selected as kernel clock,3: lsi_ck selected as kernel clock" bitfld.long 0x8 3.--5. "USART16910SEL,USART1 6 9 and 10 kernel clock source selection" "0: rcc_pclk2 selected as kernel clock (default..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?" newline bitfld.long 0x8 0.--2. "USART234578SEL,USART2/3 UART4 5 7 and 8 (APB1) kernel clock source selection" "0: rcc_pclk1 selected as kernel clock (default..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?" line.long 0xC "RCC_SRDCCIPR,RCC SmartRun domain kernel clock configuration register" bitfld.long 0xC 28.--30. "SPI6SEL,SPI6 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: hse_ck selected as kernel peripheral clock,6: I2S_CKIN selected as kernel peripheral clock,?" bitfld.long 0xC 27. "DFSDM2SEL,DFSDM2 kernel Clk clock source selection" "0: rcc_pclk4 selected as DFSDM2 Clk kernel clock..,1: sys_ck selected as DFSDM2 Clk kernel clock" newline bitfld.long 0xC 16.--17. "ADCSEL,SAR ADC kernel clock source selection" "0: pll2_p_ck selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: per_ck selected as kernel peripheral clock,?" bitfld.long 0xC 13.--15. "LPTIM3SEL,LPTIM3 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" newline bitfld.long 0xC 10.--12. "LPTIM2SEL,LPTIM2 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" bitfld.long 0xC 8.--9. "I2C4SEL,I2C4 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: hsi_ker_ck selected as kernel peripheral clock,3: csi_ker_ck selected as kernel peripheral clock" newline bitfld.long 0xC 0.--2. "LPUART1SEL,LPUART1 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: lse_ck selected as kernel peripheral clock,?,?" group.long 0x60++0x3 line.long 0x0 "RCC_CIER," bitfld.long 0x0 9. "LSECSSIE,LSE clock security system interrupt enable" "0: LSE CSS interrupt disabled (default after reset),1: LSE CSS interrupt enabled" bitfld.long 0x0 8. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled (default after reset),1: PLL3 lock interrupt enabled" newline bitfld.long 0x0 7. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled (default after reset),1: PLL2 lock interrupt enabled" bitfld.long 0x0 6. "PLL1RDYIE,PLL1 ready interrupt enable" "0: PLL1 lock interrupt disabled (default after reset),1: PLL1 lock interrupt enabled" newline bitfld.long 0x0 5. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled (default after..,1: HSI48 ready interrupt enabled" bitfld.long 0x0 4. "CSIRDYIE,CSI ready interrupt enable" "0: CSI ready interrupt disabled (default after reset),1: CSI ready interrupt enabled" newline bitfld.long 0x0 3. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled (default after reset),1: HSE ready interrupt enabled" bitfld.long 0x0 2. "HSIRDYIE,HSI ready interrupt enable" "0: HSI ready interrupt disabled (default after reset),1: HSI ready interrupt enabled" newline bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled (default after reset),1: LSE ready interrupt enabled" bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled (default after reset),1: LSI ready interrupt enabled" rgroup.long 0x64++0x3 line.long 0x0 "RCC_CIFR," bitfld.long 0x0 10. "HSECSSF,HSE clock security system interrupt flag" "0: no clock security interrupt caused by HSE clock..,1: clock security interrupt caused by HSE clock.." bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: no failure detected on the external 32 kHz..,1: failure detected on the external 32 kHz oscillator" newline bitfld.long 0x0 8. "PLL3RDYF,PLL3 ready interrupt flag" "0: no clock ready interrupt caused by PLL3 lock..,1: clock ready interrupt caused by PLL3 lock" bitfld.long 0x0 7. "PLL2RDYF,PLL2 ready interrupt flag" "0: no clock ready interrupt caused by PLL2 lock..,1: clock ready interrupt caused by PLL2 lock" newline bitfld.long 0x0 6. "PLL1RDYF,PLL1 ready interrupt flag" "0: no clock ready interrupt caused by PLL1 lock..,1: clock ready interrupt caused by PLL1 lock" bitfld.long 0x0 5. "HSI48RDYF,HSI48 ready interrupt flag" "0: no clock ready interrupt caused by the HSI48..,1: clock ready interrupt caused by the HSI48.." newline bitfld.long 0x0 4. "CSIRDYF,CSI ready interrupt flag" "0: no clock ready interrupt caused by the CSI..,1: clock ready interrupt caused by the CSI" bitfld.long 0x0 3. "HSERDYF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE" newline bitfld.long 0x0 2. "HSIRDYF,HSI ready interrupt flag" "0: no clock ready interrupt caused by the HSI..,1: clock ready interrupt caused by the HSI" bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE" newline bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: no clock ready interrupt caused by the LSI..,1: clock ready interrupt caused by the LSI" group.long 0x68++0x3 line.long 0x0 "RCC_CICR," bitfld.long 0x0 10. "HSECSSC,HSE clock security system interrupt clear" "0: HSECSSF no effect (default after reset),1: HSECSSF cleared" bitfld.long 0x0 9. "LSECSSC,LSE clock security system interrupt clear" "0: LSECSSF no effect (default after reset),1: LSECSSF cleared" newline bitfld.long 0x0 8. "PLL3RDYC,PLL3 ready interrupt clear" "0: PLL3RDYF no effect (default after reset),1: PLL3RDYF cleared" bitfld.long 0x0 7. "PLL2RDYC,PLL2 ready interrupt clear" "0: PLL2RDYF no effect (default after reset),1: PLL2RDYF cleared" newline bitfld.long 0x0 6. "PLL1RDYC,PLL1 ready interrupt clear" "0: PLL1RDYF no effect (default after reset),1: PLL1RDYF cleared" bitfld.long 0x0 5. "HSI48RDYC,HSI48 ready interrupt clear" "0: HSI48RDYF no effect (default after reset),1: HSI48RDYF cleared" newline bitfld.long 0x0 4. "CSIRDYC,CSI ready interrupt clear" "0: CSIRDYF no effect (default after reset),1: CSIRDYF cleared" bitfld.long 0x0 3. "HSERDYC,HSE ready interrupt clear" "0: HSERDYF no effect (default after reset),1: HSERDYF cleared" newline bitfld.long 0x0 2. "HSIRDYC,HSI ready interrupt clear" "0: HSIRDYF no effect (default after reset),1: HSIRDYF cleared" bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: LSERDYF no effect (default after reset),1: LSERDYF cleared" newline bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: LSIRDYF no effect (default after reset),1: LSIRDYF cleared" group.long 0x70++0x7 line.long 0x0 "RCC_BDCR,RCC Backup domain control register" bitfld.long 0x0 16. "VSWRST,VSwitch domain software reset" "0: reset not activated (default after Backup domain..,1: resets the entire VSW domain" bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0: rtc_ck disabled (default after Backup domain..,1: rtc_ck enabled" newline bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0: no clock (default after Backup domain reset),1: LSE selected as RTC clock,2: LSI selected as RTC clock,3: HSE divided by RTCPRE value selected as RTC clock" bitfld.long 0x0 7. "LSEEXT,low-speed external clock type in Bypass mode" "0: LSE in analog mode (default after Backup domain..,1: LSE in digital mode (do not use if RTC is active)." newline rbitfld.long 0x0 6. "LSECSSD,LSE clock security system failure detection" "0: no failure detected on 32 kHz oscillator..,1: failure detected on 32 kHz oscillator" bitfld.long 0x0 5. "LSECSSON,LSE clock security system enable" "0: CSS on 32 kHz oscillator OFF (default after..,1: CSS on 32 kHz oscillator ON" newline bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator driving capability" "0: lowest drive (default after Backup domain reset),1: medium-low drive,2: medium-high drive,3: highest drive" bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed (default after..,1: LSE oscillator bypassed" newline rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready (default after Backup..,1: LSE oscillator ready" bitfld.long 0x0 0. "LSEON,LSE oscillator enabled" "0: LSE oscillator OFF (default after Backup domain..,1: LSE oscillator ON" line.long 0x4 "RCC_CSR,RCC clock control and status register" rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: LSI clock is not ready (default after reset),1: LSI clock is ready" bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0: LSI is OFF (default after reset),1: LSI is ON" group.long 0x7C++0x23 line.long 0x0 "RCC_AHB3RSTR," bitfld.long 0x0 24. "GFXMMURST,GFXMMU reset" "0: does not reset the GFXMMU (default after reset),1: resets the GFXMMU" bitfld.long 0x0 23. "OTFD2RST,OTFD2 reset" "0: does not reset the OTFD2 (default after reset),1: resets the OTFD2" newline bitfld.long 0x0 22. "OTFD1RST,OTFD1 reset" "0: does not reset the OTFD1 (default after reset),1: resets the OTFD1" bitfld.long 0x0 21. "OCTOSPIMRST,OCTOSPIM reset" "0: does not reset the OCTOSPIM (default after reset),1: resets the OCTOSPIM" newline bitfld.long 0x0 19. "OCTOSPI2RST,OCTOSPI2 and OCTOSPI2 delay block reset" "0: does not reset the OCTOSPI2 and OCTOSPI2 delay..,1: resets the OCTOSPI2 and OCTOSPI2 delay block" bitfld.long 0x0 16. "SDMMC1RST,SDMMC1 and SDMMC1 delay blocks reset" "0: does not reset SDMMC1 and SDMMC1 delay blocks..,1: resets SDMMC1 and SDMMC1 delay blocks" newline bitfld.long 0x0 14. "OCTOSPI1RST,OCTOSPI1 and OCTOSPI1 delay blocks reset" "0: does not reset OCTOSPI1 and OCTOSPI1 delay..,1: resets OCTOSPI1 and OCTOSPI1 delay blocks" bitfld.long 0x0 12. "FMCRST,FMC block reset" "0: does not reset FMC block (default after reset),1: resets FMC block" newline bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0: does not reset JPGDEC block (default after reset),1: resets JPGDEC block" bitfld.long 0x0 4. "DMA2DRST,DMA2D block reset" "0: does not reset DMA2D block (default after reset),1: resets DMA2D block" newline bitfld.long 0x0 0. "MDMARST,MDMA block reset" "0: does not reset MDMA block (default after reset),1: resets MDMA block" line.long 0x4 "RCC_AHB1RSTR," bitfld.long 0x4 25. "USB1OTGRST,USB1OTG block reset" "0: does not reset USB1OTG block (default after reset),1: resets USB1OTG block" bitfld.long 0x4 9. "CRCRST,CRC block reset" "0: does not reset CRC block (default after reset),1: resets CRC block" newline bitfld.long 0x4 5. "ADC12RST,ADC1 and 2 blocks reset" "0: does not reset ADC1 and 2 blocks (default after..,1: resets ADC1 and 2 blocks" bitfld.long 0x4 1. "DMA2RST,DMA2 and DMAMUX2 blocks reset" "0: does not reset DMA2 and DMAMUX2 blocks (default..,1: resets DMA2 and DMAMUX2 blocks" newline bitfld.long 0x4 0. "DMA1RST,DMA1 and DMAMUX1 blocks reset" "0: does not reset DMA1 and DMAMUX1 blocks (default..,1: resets DMA1 and DMAMUX1 blocks" line.long 0x8 "RCC_AHB2RSTR," bitfld.long 0x8 11. "BDMA1RST,BDMA1 reset (DFSDM dedicated DMA)" "0: does not reset DMA block (default after reset),1: resets DMA block" bitfld.long 0x8 9. "SDMMC2RST,SDMMC2 and SDMMC2 delay blocks reset" "0: does not reset SDMMC2 and SDMMC2 delay blocks..,1: resets SDMMC2 and SDMMC2 delay blocks" newline bitfld.long 0x8 6. "RNGRST,random number generator block reset" "0: does not reset RNG block (default after reset),1: resets RNG block" bitfld.long 0x8 2. "HSEMRST,HSEM block reset" "0: does not reset HSEM block (default after reset),1: resets HSEM block" newline bitfld.long 0x8 0. "DCMI_PSSIRST,digital camera interface block reset (DCMI or PSSI depending which IP is active)" "0: does not reset the DCMI/PSSI block (default..,1: resets the DCMI/PSSI block" line.long 0xC "RCC_AHB4RSTR," bitfld.long 0xC 21. "BDMA2RST,SmartRun domain DMA and DMAMUX blocks reset" "0: does not reset the DMA and DMAMUX blocks..,1: resets the DMA and DMAMUX blocks" bitfld.long 0xC 10. "GPIOKRST,GPIOK block reset" "0: does not reset the GPIOK block (default after..,1: resets the GPIOK block" newline bitfld.long 0xC 9. "GPIOJRST,GPIOJ block reset" "0: does not reset the GPIOJ block (default after..,1: resets the GPIOJ block" bitfld.long 0xC 8. "GPIOIRST,GPIOI block reset" "0: does not reset the GPIOI block (default after..,1: resets the GPIOI block" newline bitfld.long 0xC 7. "GPIOHRST,GPIOH block reset" "0: does not reset the GPIOH block (default after..,1: resets the GPIOH block" bitfld.long 0xC 6. "GPIOGRST,GPIOG block reset" "0: does not reset the GPIOG block (default after..,1: resets the GPIOG block" newline bitfld.long 0xC 5. "GPIOFRST,GPIOF block reset" "0: does not reset the GPIOF block (default after..,1: resets the GPIOF block" bitfld.long 0xC 4. "GPIOERST,GPIOE block reset" "0: does not reset the GPIOE block (default after..,1: resets the GPIOE block" newline bitfld.long 0xC 3. "GPIODRST,GPIOD block reset" "0: does not reset the GPIOD block (default after..,1: resets the GPIOD block" bitfld.long 0xC 2. "GPIOCRST,GPIOC block reset" "0: does not reset the GPIOC block (default after..,1: resets the GPIOC block" newline bitfld.long 0xC 1. "GPIOBRST,GPIOB block reset" "0: does not reset the GPIOB block (default after..,1: resets the GPIOB block" bitfld.long 0xC 0. "GPIOARST,GPIOA block reset" "0: does not reset the GPIOA block (default after..,1: resets the GPIOA block" line.long 0x10 "RCC_APB3RSTR," bitfld.long 0x10 3. "LTDCRST,LTDC block reset" "0: does not reset the LTDC block (default after..,1: resets the LTDC block" line.long 0x14 "RCC_APB1LRSTR," bitfld.long 0x14 31. "UART8RST,UART8 block reset" "0: does not reset the UART8 block (default after..,1: resets the UART8 block" bitfld.long 0x14 30. "UART7RST,UART7 block reset" "0: does not reset the UART7 block (default after..,1: resets the UART7 block" newline bitfld.long 0x14 29. "DAC1RST,DAC1 (containing two converters) reset" "0: does not reset the DAC1 (default after reset),1: resets the DAC1" bitfld.long 0x14 27. "CECRST,HDMI-CEC block reset" "0: does not reset the HDMI-CEC block (default after..,1: resets the HDMI-CEC block" newline bitfld.long 0x14 23. "I2C3RST,I2C3 block reset" "0: does not reset the I2C3 block (default after..,1: resets the I2C3 block" bitfld.long 0x14 22. "I2C2RST,I2C2 block reset" "0: does not reset the I2C2 block (default after..,1: resets the I2C2 block" newline bitfld.long 0x14 21. "I2C1RST,I2C1 block reset" "0: does not reset the I2C1 block (default after..,1: resets the I2C1 block" bitfld.long 0x14 20. "UART5RST,UART5 block reset" "0: does not reset the UART5 block (default after..,1: resets the UART5 block" newline bitfld.long 0x14 19. "UART4RST,UART4 block reset" "0: does not reset the UART4 block (default after..,1: resets the UART4 block" bitfld.long 0x14 18. "USART3RST,USART3 block reset" "0: does not reset the USART3 block (default after..,1: resets the USART3 block" newline bitfld.long 0x14 17. "USART2RST,USART2 block reset" "0: does not reset the USART2 block (default after..,1: resets the USART2 block" bitfld.long 0x14 16. "SPDIFRXRST,SPDIFRX block reset" "0: does not reset the SPDIFRX block (default after..,1: resets the SPDIFRX block" newline bitfld.long 0x14 15. "SPI3RST,SPI3 block reset" "0: does not reset the SPI3 block (default after..,1: resets the SPI3 block" bitfld.long 0x14 14. "SPI2RST,SPI2 block reset" "0: does not reset the SPI2 block (default after..,1: resets the SPI2 block" newline bitfld.long 0x14 9. "LPTIM1RST,LPTIM1 block reset" "0: does not reset the LPTIM1 block (default after..,1: resets the LPTIM1 block" bitfld.long 0x14 8. "TIM14RST,TIM14 block reset" "0: does not reset the TIM14 block (default after..,1: resets the TIM14 block" newline bitfld.long 0x14 7. "TIM13RST,TIM13 block reset" "0: does not reset the TIM13 block (default after..,1: resets the TIM13 block" bitfld.long 0x14 6. "TIM12RST,TIM12 block reset" "0: does not reset the TIM12 block (default after..,1: resets the TIM12 block" newline bitfld.long 0x14 5. "TIM7RST,TIM7 block reset" "0: does not reset the TIM7 block (default after..,1: resets the TIM7 block" bitfld.long 0x14 4. "TIM6RST,TIM6 block reset" "0: does not reset the TIM6 block (default after..,1: resets the TIM6 block" newline bitfld.long 0x14 3. "TIM5RST,TIM5 block reset" "0: does not reset the TIM5 block (default after..,1: resets the TIM5 block" bitfld.long 0x14 2. "TIM4RST,TIM4 block reset" "0: does not reset the TIM4 block (default after..,1: resets the TIM4 block" newline bitfld.long 0x14 1. "TIM3RST,TIM3 block reset" "0: does not reset the TIM3 block (default after..,1: resets the TIM3 block" bitfld.long 0x14 0. "TIM2RST,TIM2 block reset" "0: does not reset the TIM2 block (default after..,1: resets the TIM2 block" line.long 0x18 "RCC_APB1HRSTR," bitfld.long 0x18 8. "FDCANRST,FDCAN block reset" "0: does not reset the FDCAN block (default after..,1: resets the FDCAN block" bitfld.long 0x18 5. "MDIOSRST,MDIOS block reset" "0: does not reset the MDIOS block (default after..,1: resets the MDIOS block" newline bitfld.long 0x18 4. "OPAMPRST,OPAMP block reset" "0: does not reset the OPAMP block (default after..,1: resets the OPAMP block" bitfld.long 0x18 2. "SWPMIRST,SWPMI block reset" "0: does not reset the SWPMI block (default after..,1: resets the SWPMI block" newline bitfld.long 0x18 1. "CRSRST,clock recovery system reset" "0: does not reset CRS (default after reset),1: resets CRS" line.long 0x1C "RCC_APB2RSTR," bitfld.long 0x1C 30. "DFSDM1RST,DFSDM1 block reset" "0: does not reset DFSDM1 block (default after reset),1: resets DFSDM1 block" bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0: does not reset the SAI2 block (default after..,1: resets the SAI2 block" newline bitfld.long 0x1C 22. "SAI1RST,SAI1 block reset" "0: does not reset the SAI1 (default after reset),1: resets the SAI1" bitfld.long 0x1C 20. "SPI5RST,SPI5 block reset" "0: does not reset the SPI5 block (default after..,1: resets the SPI5 block" newline bitfld.long 0x1C 18. "TIM17RST,TIM17 block reset" "0: does not reset the TIM17 block (default after..,1: resets the TIM17 block" bitfld.long 0x1C 17. "TIM16RST,TIM16 block reset" "0: does not reset the TIM16 block (default after..,1: resets the TIM16 block" newline bitfld.long 0x1C 16. "TIM15RST,TIM15 block reset" "0: does not reset the TIM15 block (default after..,1: resets the TIM15 block" bitfld.long 0x1C 13. "SPI4RST,SPI4 block reset" "0: does not reset the SPI4 block (default after..,1: resets the SPI4 block" newline bitfld.long 0x1C 12. "SPI1RST,SPI1 block reset" "0: does not reset the SPI1 block (default after..,1: resets the SPI1 block" bitfld.long 0x1C 7. "USART10RST,USART10 block reset" "0: does not reset the USART10 block (default after..,1: resets the USART10 block" newline bitfld.long 0x1C 6. "UART9RST,UART9 block reset" "0: does not reset the UART9 block (default after..,1: resets the UART9 block" bitfld.long 0x1C 5. "USART6RST,USART6 block reset" "0: does not reset the USART6 block (default after..,1: resets the USART6 block" newline bitfld.long 0x1C 4. "USART1RST,USART1 block reset" "0: does not reset the USART1 block (default after..,1: resets the USART1 block" bitfld.long 0x1C 1. "TIM8RST,TIM8 block reset" "0: does not reset the TIM8 block (default after..,1: resets the TIM8 block" newline bitfld.long 0x1C 0. "TIM1RST,TIM1 block reset" "0: does not reset the TIM1 block (default after..,1: resets the TIM1 block" line.long 0x20 "RCC_APB4RSTR," bitfld.long 0x20 27. "DFSDM2RST,DFSDM2 block reset" "0: does not reset the DFSDM2 block (default after..,1: resets the DFSDM2 block" bitfld.long 0x20 26. "DTSRST,Digital temperature sensor block reset" "0: does not reset the DTS block (default after reset),1: resets the DTS block" newline bitfld.long 0x20 15. "VREFRST,VREF block reset" "0: does not reset the VREF block (default after..,1: resets the VREF block" bitfld.long 0x20 14. "COMP12RST,COMP1 and 2 blocks reset" "0: does not reset the COMP1 and 2 blocks (default..,1: resets the COMP1 and 2 blocks" newline bitfld.long 0x20 13. "DAC2RST,DAC2 (containing one converter) reset" "0: does not reset the DAC2 (default after reset),1: resets the DAC2" bitfld.long 0x20 10. "LPTIM3RST,LPTIM3 block reset" "0: does not reset the LPTIM3 block (default after..,1: resets the LPTIM3 block" newline bitfld.long 0x20 9. "LPTIM2RST,LPTIM2 block reset" "0: does not reset the LPTIM2 block (default after..,1: resets the LPTIM2 block" bitfld.long 0x20 7. "I2C4RST,I2C4 block reset" "0: does not reset the I2C4 block (default after..,1: resets the I2C4 block" newline bitfld.long 0x20 5. "SPI6RST,SPI6 block reset" "0: does not reset the SPI6 block (default after..,1: resets the SPI6 block" bitfld.long 0x20 3. "LPUART1RST,LPUART1 block reset" "0: does not reset the LPUART1 block (default after..,1: resets the LPUART1 block" newline bitfld.long 0x20 1. "SYSCFGRST,SYSCFG block reset" "0: does not reset the SYSCFG block (default after..,1: resets the SYSCFG block" group.long 0xA8++0x3 line.long 0x0 "RCC_SRDAMR,RCC SmartRun domain Autonomous mode register" bitfld.long 0x0 29. "SRDSRAMAMEN,SmartRun domain SRAM Autonomous mode enable" "0: SRDSRAM clock disabled when the CPU is in CStop..,1: SRDSRAM bus clock enabled when the SmartRun.." bitfld.long 0x0 28. "BKPRAMAMEN,Backup RAM Autonomous mode enable" "0: Backup RAM clock disabled when the CPU is in..,1: Backup RAM clock enabling is controlled by the.." newline bitfld.long 0x0 27. "DFSDM2AMEN,DFSDM2 Autonomous mode enable" "0: DFSDM2 clock disabled when the CPU is in CStop..,1: DFSDM2 peripheral clocks enabled when the.." bitfld.long 0x0 26. "DTSAMEN,Digital temperature sensor Autonomous mode enable" "0: DTS clocks disabled when the CPU is in CStop..,1: DTS clocks enabled when the SmartRun domain is.." newline bitfld.long 0x0 16. "RTCAMEN,RTC Autonomous mode enable" "0: RTC bus clocks disabled when the CPU is in CStop..,1: RTC bus clocks enabled when the SmartRun domain.." bitfld.long 0x0 15. "VREFAMEN,VREF Autonomous mode enable" "0: VREF clocks disabled when the CPU is in CStop..,1: VREF clocks enabled when the SmartRun domain is.." newline bitfld.long 0x0 14. "COMP12AMEN,COMP1 and 2 Autonomous mode enable" "0: COMP1 and 2 peripheral clocks disabled when the..,1: COMP1 and 2 peripheral clocks enabled when the.." bitfld.long 0x0 13. "DAC2AMEN,DAC2 (containing one converter) Autonomous mode enable" "0: DAC2 peripheral clocks disabled when the CPU is..,1: DAC2 peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 10. "LPTIM3AMEN,LPTIM3 Autonomous mode enable" "0: LPTIM3 peripheral clocks disabled when the CPU..,1: LPTIM3 peripheral clocks enabled when the.." bitfld.long 0x0 9. "LPTIM2AMEN,LPTIM2 Autonomous mode enable" "0: LPTIM2 peripheral clocks are disabled when the..,1: LPTIM2 peripheral clocks enabled when the.." newline bitfld.long 0x0 7. "I2C4AMEN,I2C4 Autonomous mode enable" "0: I2C4 peripheral clocks disabled when the CPU is..,1: I2C4 peripheral clocks enabled when the SmartRun.." bitfld.long 0x0 5. "SPI6AMEN,SPI6 Autonomous mode enable" "0: SPI6 peripheral clocks disabled when the CPU is..,1: SPI6 peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 3. "LPUART1AMEN,LPUART1 Autonomous mode enable" "0: LPUART1 peripheral clocks disabled when the CPU..,1: LPUART1 peripheral clocks enabled when the.." bitfld.long 0x0 1. "GPIOAMEN,GPIO Autonomous mode enable" "0: GPIO peripheral clocks disabled when the CPU is..,1: GPIO peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 0. "BDMA2AMEN,SmartRun domain DMA and DMAMUX Autonomous mode enable" "0: BDMA2 and DMAMUX2 peripheral clocks disabled..,1: BDMA2 and DMAMUX2 peripheral clocks enabled when.." group.long 0xB0++0x3 line.long 0x0 "RCC_CKGAENR,RCC AXI clocks gating enable register" bitfld.long 0x0 31. "JTAGCKG,JTAG automatic clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The clock is.." bitfld.long 0x0 30. "EXTICKG,EXTI clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The clock is.." newline bitfld.long 0x0 29. "ECCRAMCKG,RAM error code correction (ECC) clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The ECC clock is.." bitfld.long 0x0 17. "GFXMMUSCKG,AXI matrix slave GFXMMU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 16. "AXIRAM3CKG,AXI matrix slave SRAM3 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 15. "AXIRAM2CKG,AXI matrix slave SRAM2 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 14. "AXIRAM1CKG,AXI slave SRAM1 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 13. "OCTOSPI1CKG,AXI slave OCTOSPI1 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 12. "FMCCKG,AXI slave FMC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 11. "OCTOSPI2CKG,AXI slave OCTOSPI2 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 10. "FLIFTCKG,AXI slave Flash interface (FLIFT) clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 9. "AHB34CKG,AXI slave AHB34 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 8. "AHB12CKG,AXI slave AHB12 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 7. "GFXMMUMCKG,AXI master GFXMMU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 6. "LTDCCKG,AXI master LTDC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 5. "DMA2DCKG,AXI master DMA2D clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 4. "MDMACKG,AXI master MDMA clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 3. "SDMMCCKG,AXI master SDMMC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 2. "CPUCKG,AXI master CPU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 1. "AHBCKG,AXI master AHB clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 0. "AXICKG,AXI interconnect matrix clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI.." group.long 0x130++0x27 line.long 0x0 "RCC_RSR,RCC reset status register" rbitfld.long 0x0 30. "LPWRRSTF,reset due to illegal CD DStop or CD DStop2 or CPU CStop flag" "0: no illegal reset occurred (default after..,1: illegal CD DStop or CD DStop2 or CPU CStop reset.." rbitfld.long 0x0 28. "WWDGRSTF,window watchdog reset flag" "0: no window watchdog reset occurred from WWDG..,1: window watchdog reset occurred from WWDG" newline rbitfld.long 0x0 26. "IWDGRSTF,independent watchdog reset flag" "0: no independent watchdog reset occurred (default..,1: independent watchdog reset occurred" rbitfld.long 0x0 24. "SFTRSTF,system reset from CPU reset flag" "0: no CPU software reset occurred (default after..,1: a system reset has been generated by the CPU" newline rbitfld.long 0x0 23. "PORRSTF,POR/PDR reset flag" "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.." rbitfld.long 0x0 22. "PINRSTF,pin reset flag (NRST)" "0: no reset from pin occurred,1: reset from pin occurred (default after power-on.." newline rbitfld.long 0x0 21. "BORRSTF,BOR reset flag" "0: no BOR reset occurred,1: BOR reset occurred (default after power-on reset)" rbitfld.long 0x0 19. "CDRSTF,CPU domain power-switch reset flag" "0: no CPU domain power-switch reset occurred,1: CPU domain power-switch (ePOD2) reset occurred.." newline bitfld.long 0x0 16. "RMVF,remove reset flag" "0: reset of the reset flags not activated (default..,1: resets the value of the reset flags" line.long 0x4 "RCC_AHB3ENR," bitfld.long 0x4 24. "GFXMMUEN,GFXMMU clock enable" "0: GFXMMU clock disabled (default after reset),1: GFXMMU clock enabled" bitfld.long 0x4 23. "OTFD2EN,OTFD2 clock enable" "0: OTFD2 clock disabled (default after reset),1: OTFD2 clock enabled" newline bitfld.long 0x4 22. "OTFD1EN,OTFD1 clock enable" "0: OTFD1 clock disabled (default after reset),1: OTFD1 clock enabled" bitfld.long 0x4 21. "OCTOSPIMEN,OCTOSPIM clock enable" "0: OCTOSPIM clock disabled (default after reset),1: OCTOSPIM clock enabled" newline bitfld.long 0x4 19. "OCTOSPI2EN,OCTOSPI2 clock enable" "0: OCTOSPI2 and OCTOSPI2 delay clock disabled..,1: OCTOSPI2 OCTOSPI2 delay clock enabled" bitfld.long 0x4 16. "SDMMC1EN,SDMMC1 and SDMMC1 delay clock enable" "0: SDMMC1 and SDMMC1 delay clock disabled (default..,1: SDMMC1 and SDMMC1 delay clock enabled" newline bitfld.long 0x4 14. "OCTOSPI1EN,OCTOSPI1 and OCTOSPI1 delay clock enable" "0: OCTOSPI1 and OCTOSPI1 delay clock disabled..,1: OCTOSPI1 and OCTOSPI1 delay clock enabled" bitfld.long 0x4 12. "FMCEN,FMC peripheral clocks enable" "0: FMC peripheral clocks disabled (default after..,1: FMC peripheral clocks enabled" newline bitfld.long 0x4 5. "JPGDECEN,JPGDEC peripheral clock enable" "0: JPGDEC peripheral clock disabled (default after..,1: JPGDEC peripheral clock enabled" bitfld.long 0x4 4. "DMA2DEN,DMA2D peripheral clock enable" "0: DMA2D peripheral clock disabled (default after..,1: DMA2D peripheral clock enabled" newline bitfld.long 0x4 0. "MDMAEN,MDMA peripheral clock enable" "0: MDMA peripheral clock disabled (default after..,1: MDMA peripheral clock enabled" line.long 0x8 "RCC_AHB1ENR," bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 clocks enable" "0: USB1ULPI PHY clocks disabled (default after reset),1: USB1ULPI PHY clocks enabled" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG peripheral clocks enable" "0: USB1OTG peripheral clocks disabled (default..,1: USB1OTG peripheral clocks enabled" newline bitfld.long 0x8 9. "CRCEN,CRC peripheral clock enable" "0: CRC peripheral clock disabled (default after..,1: CRC peripheral clock enabled" bitfld.long 0x8 5. "ADC12EN,ADC1 and 2 peripheral clocks enable" "0: ADC1 and 2 peripheral clocks disabled (default..,1: ADC1 and 2 peripheral clocks enabled" newline bitfld.long 0x8 1. "DMA2EN,DMA2 clock enable" "0: DMA2 clock disabled (default after reset),1: DMA2 clock enabled" bitfld.long 0x8 0. "DMA1EN,DMA1 clock enable" "0: DMA1 clock disabled (default after reset),1: DMA1 clock enabled" line.long 0xC "RCC_AHB2ENR," bitfld.long 0xC 30. "AHBSRAM2EN,AHBSRAM2 block enable" "0: AHBSRAM2 interface clock is disabled. (default..,1: AHBSRAM2 interface clock is enabled." bitfld.long 0xC 29. "AHBSRAM1EN,AHBSRAM1 block enable" "0: AHBSRAM1 interface clock is disabled. (default..,1: AHBSRAM1 interface clock is enabled." newline bitfld.long 0xC 11. "BDMA1EN,DMA clock enable (DFSDM dedicated DMA)" "0: DMA clock disabled (default after reset),1: DMA clock enabled" bitfld.long 0xC 9. "SDMMC2EN,SDMMC2 and SDMMC2 delay clock enable" "0: SDMMC2 and SDMMC2 delay clock disabled (default..,1: SDMMC2 and SDMMC2 delay clock enabled" newline bitfld.long 0xC 6. "RNGEN,RNG peripheral clocks enable" "0: RNG peripheral clocks disabled (default after..,1: RNG peripheral clocks enabled:" bitfld.long 0xC 2. "HSEMEN,HSEM peripheral clock enable" "0: HSEM peripheral clock disabled (default after..,1: HSEM peripheral clock enabled" newline bitfld.long 0xC 0. "DCMI_PSSIEN,digital camera interface peripheral clock enable (DCMI or PSSI depending which IP is active)" "0: DCMI/PSSI peripheral clock disabled (default..,1: DCMI/PSSI peripheral clock enabled" line.long 0x10 "RCC_AHB4ENR," bitfld.long 0x10 29. "SRDSRAMEN,SmartRun domain SRAM clock enable" "0: SRDSRAM clock disabled (default after reset),1: SRDSRAM clock enabled" bitfld.long 0x10 28. "BKPRAMEN,Backup RAM clock enable" "0: Backup RAM clock disabled (default after reset),1: Backup RAM clock enabled" newline bitfld.long 0x10 21. "BDMA2EN,SmartRun domain DMA and DMAMUX clock enable" "0: BDMA2 and DMAMUX2 clock disabled (default after..,1: BDMA2 and DMAMUX2 clock enabled" bitfld.long 0x10 10. "GPIOKEN,GPIOK peripheral clock enable" "0: GPIOK peripheral clock disabled (default after..,1: GPIOK peripheral clock enabled" newline bitfld.long 0x10 9. "GPIOJEN,GPIOJ peripheral clock enable" "0: GPIOJ peripheral clock disabled (default after..,1: GPIOJ peripheral clock enabled" bitfld.long 0x10 8. "GPIOIEN,GPIOI peripheral clock enable" "0: GPIOI peripheral clock disabled (default after..,1: GPIOI peripheral clock enabled" newline bitfld.long 0x10 7. "GPIOHEN,GPIOH peripheral clock enable" "0: GPIOH peripheral clock disabled (default after..,1: GPIOH peripheral clock enabled" bitfld.long 0x10 6. "GPIOGEN,GPIOG peripheral clock enable" "0: GPIOG peripheral clock disabled (default after..,1: GPIOG peripheral clock enabled" newline bitfld.long 0x10 5. "GPIOFEN,GPIOF peripheral clock enable" "0: GPIOF peripheral clock disabled (default after..,1: GPIOF peripheral clock enabled" bitfld.long 0x10 4. "GPIOEEN,GPIOE peripheral clock enable" "0: GPIOE peripheral clock disabled (default after..,1: GPIOE peripheral clock enabled" newline bitfld.long 0x10 3. "GPIODEN,GPIOD peripheral clock enable" "0: GPIOD peripheral clock disabled (default after..,1: GPIOD peripheral clock enabled" bitfld.long 0x10 2. "GPIOCEN,GPIOC peripheral clock enable" "0: GPIOC peripheral clock disabled (default after..,1: GPIOC peripheral clock enabled" newline bitfld.long 0x10 1. "GPIOBEN,GPIOB peripheral clock enable" "0: GPIOB peripheral clock disabled (default after..,1: GPIOB peripheral clock enabled" bitfld.long 0x10 0. "GPIOAEN,GPIOA peripheral clock enable" "0: GPIOA peripheral clock disabled (default after..,1: GPIOA peripheral clock enabled" line.long 0x14 "RCC_APB3ENR," bitfld.long 0x14 6. "WWDGEN,WWDG clock enable" "0: WWDG peripheral clock disable (default after..,1: WWDG peripheral clock enabled" bitfld.long 0x14 3. "LTDCEN,LTDC clock enable" "0: LTDC peripheral clock disabled (default after..,1: LTDC peripheral clock provided to the LTDC block" line.long 0x18 "RCC_APB1LENR," bitfld.long 0x18 31. "UART8EN,UART8 peripheral clocks enable" "0: UART8 peripheral clocks disabled (default after..,1: UART8 peripheral clocks enabled" bitfld.long 0x18 30. "UART7EN,UART7 peripheral clocks enable" "0: UART7 peripheral clocks disabled (default after..,1: UART7 peripheral clocks enabled" newline bitfld.long 0x18 29. "DAC1EN,DAC1 (containing two converters) peripheral clock enable" "0: DAC1 peripheral clock disabled (default after..,1: DAC1 peripheral clock enabled" bitfld.long 0x18 27. "CECEN,HDMI-CEC peripheral clock enable" "0: HDMI-CEC peripheral clock disabled (default..,1: HDMI-CEC peripheral clock enabled" newline bitfld.long 0x18 23. "I2C3EN,I2C3 peripheral clocks enable" "0: I2C3 peripheral clocks disabled (default after..,1: I2C3 peripheral clocks enabled" bitfld.long 0x18 22. "I2C2EN,I2C2 peripheral clocks enable" "0: I2C2 peripheral clocks disabled (default after..,1: I2C2 peripheral clocks enabled" newline bitfld.long 0x18 21. "I2C1EN,I2C1 peripheral clocks enable" "0: I2C1 peripheral clocks disabled (default after..,1: I2C1 peripheral clocks enabled" bitfld.long 0x18 20. "UART5EN,UART5 peripheral clocks enable" "0: UART5 peripheral clocks disabled (default after..,1: UART5 peripheral clocks enabled" newline bitfld.long 0x18 19. "UART4EN,UART4 peripheral clocks enable" "0: UART4 peripheral clocks disabled (default after..,1: UART4 peripheral clocks enabled" bitfld.long 0x18 18. "USART3EN,USART3 peripheral clocks enable" "0: USART3 peripheral clocks disabled (default after..,1: USART3 peripheral clocks enabled" newline bitfld.long 0x18 17. "USART2EN,USART2peripheral clocks enable" "0: USART2 peripheral clocks disabled (default after..,1: USART2 peripheral clocks enabled" bitfld.long 0x18 16. "SPDIFRXEN,SPDIFRX peripheral clocks enable" "0: SPDIFRX peripheral clocks disabled (default..,1: SPDIFRX peripheral clocks enabled" newline bitfld.long 0x18 15. "SPI3EN,SPI3 peripheral clocks enable" "0: SPI3 peripheral clocks disabled (default after..,1: SPI3 peripheral clocks enabled" bitfld.long 0x18 14. "SPI2EN,SPI2 peripheral clocks enable" "0: SPI2 peripheral clocks disabled (default after..,1: SPI2 peripheral clocks enabled" newline bitfld.long 0x18 9. "LPTIM1EN,LPTIM1 peripheral clocks enable" "0: LPTIM1 peripheral clocks disabled (default after..,1: LPTIM1 peripheral clocks enabled" bitfld.long 0x18 8. "TIM14EN,TIM14 peripheral clock enable" "0: TIM14 peripheral clock disabled (default after..,1: TIM14 peripheral clock enabled" newline bitfld.long 0x18 7. "TIM13EN,TIM13 peripheral clock enable" "0: TIM13 peripheral clock disabled (default after..,1: TIM13 peripheral clock enabled" bitfld.long 0x18 6. "TIM12EN,TIM12 peripheral clock enable" "0: TIM12 peripheral clock disabled (default after..,1: TIM12 peripheral clock enabled" newline bitfld.long 0x18 5. "TIM7EN,TIM7 peripheral clock enable" "0: TIM7 peripheral clock disabled (default after..,1: TIM7 peripheral clock enabled" bitfld.long 0x18 4. "TIM6EN,TIM6 peripheral clock enable" "0: TIM6 peripheral clock disabled (default after..,1: TIM6 peripheral clock enabled" newline bitfld.long 0x18 3. "TIM5EN,TIM5 peripheral clock enable" "0: TIM5 peripheral clock disabled (default after..,1: TIM5 peripheral clock enabled" bitfld.long 0x18 2. "TIM4EN,TIM4 peripheral clock enable" "0: TIM4 peripheral clock disable (default after..,1: TIM4 peripheral clock enabled" newline bitfld.long 0x18 1. "TIM3EN,TIM3 peripheral clock enable" "0: TIM3 peripheral clock disabled (default after..,1: TIM3 peripheral clock enabled" bitfld.long 0x18 0. "TIM2EN,TIM2 peripheral clock enable" "0: TIM2 peripheral clock disabled (default after..,1: TIM2 peripheral clock enabled" line.long 0x1C "RCC_APB1HENR," bitfld.long 0x1C 8. "FDCANEN,FDCAN peripheral clocks enable" "0: FDCAN peripheral clocks disabled (default after..,1: FDCAN peripheral clocks enabled:" bitfld.long 0x1C 5. "MDIOSEN,MDIOS peripheral clock enable" "0: MDIOS peripheral clock disabled (default after..,1: MDIOS peripheral clock enabled" newline bitfld.long 0x1C 4. "OPAMPEN,OPAMP peripheral clock enable" "0: OPAMP peripheral clock disabled (default after..,1: OPAMP peripheral clock enabled" bitfld.long 0x1C 2. "SWPMIEN,SWPMI peripheral clocks enable" "0: SWPMI peripheral clocks disabled (default after..,1: SWPMI peripheral clocks enabled:" newline bitfld.long 0x1C 1. "CRSEN,clock recovery system peripheral clock enable" "0: CRS peripheral clock disabled (default after..,1: CRS peripheral clock enabled" line.long 0x20 "RCC_APB2ENR," bitfld.long 0x20 30. "DFSDM1EN,DFSDM1 peripheral clocks enable" "0: DFSDM1 peripheral clocks disabled (default after..,1: DFSDM1 peripheral clocks enabled" bitfld.long 0x20 23. "SAI2EN,SAI2 peripheral clocks enable" "0: SAI2 peripheral clocks disabled (default after..,1: SAI2 peripheral clocks enabled" newline bitfld.long 0x20 22. "SAI1EN,SAI1 peripheral clocks enable" "0: SAI1 peripheral clocks disabled (default after..,1: SAI1 peripheral clocks enabled:" bitfld.long 0x20 20. "SPI5EN,SPI5 peripheral clocks enable" "0: SPI5 peripheral clocks disabled (default after..,1: SPI5 peripheral clocks enabled:" newline bitfld.long 0x20 18. "TIM17EN,TIM17 peripheral clock enable" "0: TIM17 peripheral clock disabled (default after..,1: TIM17 peripheral clock enabled" bitfld.long 0x20 17. "TIM16EN,TIM16 peripheral clock enable" "0: TIM16 peripheral clock disabled (default after..,1: TIM16 peripheral clock enabled" newline bitfld.long 0x20 16. "TIM15EN,TIM15 peripheral clock enable" "0: TIM15 peripheral clock disabled (default after..,1: TIM15 peripheral clock enabled" bitfld.long 0x20 13. "SPI4EN,SPI4 Peripheral Clocks Enable" "0: SPI4 peripheral clocks disabled (default after..,1: SPI4 peripheral clocks enabled:" newline bitfld.long 0x20 12. "SPI1EN,SPI1 Peripheral Clocks Enable" "0: SPI1 peripheral clocks disabled (default after..,1: SPI1 peripheral clocks enabled:" bitfld.long 0x20 7. "USART10EN,USART10 peripheral clocks enable" "0: USART10 peripheral clocks disabled (default..,1: USART10 peripheral clocks enabled:" newline bitfld.long 0x20 6. "UART9EN,UART9 peripheral clocks enable" "0: UART9 peripheral clocks disabled (default after..,1: UART9 peripheral clocks enabled:" bitfld.long 0x20 5. "USART6EN,USART6 peripheral clocks enable" "0: USART6 peripheral clocks disabled (default after..,1: USART6 peripheral clocks enabled:" newline bitfld.long 0x20 4. "USART1EN,USART1 peripheral clocks enable" "0: USART1 peripheral clocks disabled (default after..,1: USART1 peripheral clocks enabled:" bitfld.long 0x20 1. "TIM8EN,TIM8 peripheral clock enable" "0: TIM8 peripheral clock disabled (default after..,1: TIM8 peripheral clock enabled" newline bitfld.long 0x20 0. "TIM1EN,TIM1 peripheral clock enable" "0: TIM1 peripheral clock disabled (default after..,1: TIM1 peripheral clock enabled" line.long 0x24 "RCC_APB4ENR," bitfld.long 0x24 27. "DFSDM2EN,DFSDM2peripheral clock enable" "0: DFSDM2peripheral peripheral clock disabled..,1: DFSDM2peripheral peripheral clock enabled" bitfld.long 0x24 26. "DTSEN,Digital temperature sensor peripheral clock enable" "0: DTS peripheral clock disabled (default after..,1: DTS peripheral clock enabled" newline bitfld.long 0x24 16. "RTCAPBEN,RTC APB clock enable" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.." bitfld.long 0x24 15. "VREFEN,VREF peripheral clock enable" "0: VREF peripheral clock disabled (default after..,1: VREF peripheral clock enabled" newline bitfld.long 0x24 14. "COMP12EN,COMP1 and 2 peripheral clock enable" "0: COMP1 and 2 peripheral clock disabled (default..,1: COMP1 and 2 peripheral clock enabled" bitfld.long 0x24 13. "DAC2EN,DAC2 (containing one converter) peripheral clock enable" "0: DAC2 peripheral clock disabled (default after..,1: DAC2 peripheral clock enabled" newline bitfld.long 0x24 10. "LPTIM3EN,LPTIM3 peripheral clocks enable" "0: LPTIM3 peripheral clocks disabled (default after..,1: LPTIM3 peripheral clocks enabled" bitfld.long 0x24 9. "LPTIM2EN,LPTIM2 peripheral clocks enable" "0: LPTIM2 peripheral clocks disabled (default after..,1: LPTIM2 peripheral clocks enabled" newline bitfld.long 0x24 7. "I2C4EN,I2C4 peripheral clocks enable" "0: I2C4 peripheral clocks disabled (default after..,1: I2C4 peripheral clocks enabled" bitfld.long 0x24 5. "SPI6EN,SPI6 peripheral clocks enable" "0: SPI6 peripheral clocks disabled (default after..,1: SPI6 peripheral clocks enabled" newline bitfld.long 0x24 3. "LPUART1EN,LPUART1 peripheral clocks enable" "0: LPUART1 peripheral clocks disabled (default..,1: LPUART1 peripheral clocks enabled" bitfld.long 0x24 1. "SYSCFGEN,SYSCFG peripheral clock enable" "0: SYSCFG peripheral clock disabled (default after..,1: SYSCFG peripheral clock enabled" group.long 0x15C++0x23 line.long 0x0 "RCC_AHB3LPENR," bitfld.long 0x0 31. "AXISRAM1LPEN,AXISRAM1 block clock enable during CSleep mode" "0: AXISRAM1 interface clock disabled during CSleep..,1: AXISRAM1 interface clock enabled during CSleep.." bitfld.long 0x0 30. "ITCMLPEN,ITCM block clock enable during CSleep mode" "0: ITCM interface clock disabled during CSleep mode,1: ITCM interface clock enabled during CSleep mode.." newline bitfld.long 0x0 29. "DTCM2LPEN,DTCM2 block clock enable during CSleep mode" "0: DTCM2 interface clock disabled during CSleep mode,1: DTCM2 interface clock enabled during CSleep mode.." bitfld.long 0x0 28. "DTCM1LPEN,DTCM1 block clock enable during CSleep mode" "0: DTCM1 interface clock disabled during CSleep mode,1: DTCM1 interface clock enabled during CSleep mode.." newline bitfld.long 0x0 27. "AXISRAM3LPEN,AXISRAM3 block clock enable during CSleep mode" "0: AXISRAM3 interface clock disabled during CSleep..,1: AXISRAM3 interface clock enabled during CSleep.." bitfld.long 0x0 26. "AXISRAM2LPEN,AXISRAM2 block clock enable during CSleep mode" "0: AXISRAM2 interface clock disabled during CSleep..,1: AXISRAM2 interface clock enabled during CSleep.." newline bitfld.long 0x0 24. "GFXMMULPEN,GFXMMU block clock enable during CSleep mode" "0: GFXMMU interface clock disabled during CSleep mode,1: GFXMMU interface clock enabled during CSleep.." bitfld.long 0x0 23. "OTFD2LPEN,OTFD2 block clock enable during CSleep mode" "0: OTFD2 interface clock disabled during CSleep mode,1: OTFD2 interface clock enabled during CSleep mode.." newline bitfld.long 0x0 22. "OTFD1LPEN,OTFD1 block clock enable during CSleep mode" "0: OTFD1 interface clock disabled during CSleep mode,1: OTFD1 interface clock enabled during CSleep mode.." bitfld.long 0x0 21. "OCTOSPIMLPEN,OCTOSPIM block clock enable during CSleep mode" "0: OCTOSPIM interface clock disabled during CSleep..,1: OCTOSPIM interface clock enabled during CSleep.." newline bitfld.long 0x0 19. "OCTOSPI2LPEN,OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode" "0: OCTOSPI2 and OCTOSPI2 delay clock disabled..,1: OCTOSPI2 and OCTOSPI2 delay clock enabled during.." bitfld.long 0x0 16. "SDMMC1LPEN,SDMMC1 and SDMMC1 delay clock enable during CSleep mode" "0: SDMMC1 and SDMMC1 delay clock disabled during..,1: SDMMC1 and SDMMC1 delay clock enabled during.." newline bitfld.long 0x0 14. "OCTOSPI1LPEN,OCTOSPI1 and OCTOSPI1 delay clock enable during CSleep mode" "0: OCTOSPI1 and OCTOSPI1 delay clock disabled..,1: OCTOSPI1 and OCTOSPI1 delay clock enabled during.." bitfld.long 0x0 12. "FMCLPEN,FMC peripheral clocks enable during CSleep mode" "0: FMC peripheral clocks disabled during CSleep mode,1: FMC peripheral clocks enabled during CSleep mode.." newline bitfld.long 0x0 8. "FLITFLPEN,FLITF clock enable during CSleep mode" "0: FLITF clock disabled during CSleep mode,1: FLITF clock enabled during CSleep mode (default.." bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC clock enable during CSleep mode" "0: JPGDEC peripheral clock disabled during CSleep..,1: JPGDEC peripheral clock enabled during CSleep.." newline bitfld.long 0x0 4. "DMA2DLPEN,DMA2D clock enable during CSleep mode" "0: DMA2D peripheral clock disabled during CSleep mode,1: DMA2D peripheral clock enabled during CSleep.." bitfld.long 0x0 0. "MDMALPEN,MDMA clock enable during CSleep mode" "0: MDMA peripheral clock disabled during CSleep mode,1: MDMA peripheral clock enabled during CSleep mode.." line.long 0x4 "RCC_AHB1LPENR," bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep mode" "0: USB_PHY1 peripheral clock disabled during CSleep..,1: USB_PHY1 peripheral clock enabled during CSleep.." bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during CSleep mode" "0: USB1OTG peripheral clock disabled during CSleep..,1: USB1OTG peripheral clock enabled during CSleep.." newline bitfld.long 0x4 9. "CRCLPEN,CRC peripheral clock enable during CSleep mode" "0: CRC peripheral clock disabled during CSleep mode,1: CRC peripheral clock enabled during CSleep mode.." bitfld.long 0x4 5. "ADC12LPEN,ADC1 and 2 peripheral clocks enable during CSleep mode" "0: ADC1 and 2 peripheral clocks disabled during..,1: ADC1 and 2 peripheral clocks enabled during.." newline bitfld.long 0x4 1. "DMA2LPEN,DMA2 clock enable during CSleep mode" "0: DMA2 clock disabled during CSleep mode,1: DMA2 clock enabled during CSleep mode (default.." bitfld.long 0x4 0. "DMA1LPEN,DMA1 clock enable during CSleep mode" "0: DMA1 clock disabled during CSleep mode,1: DMA1 clock enabled during CSleep mode (default.." line.long 0x8 "RCC_AHB2LPENR," bitfld.long 0x8 30. "AHBSRAM2LPEN,AHBSRAM2 clock enable during CSleep mode" "0: AHBSRAM2 clock disabled during CSleep mode,1: AHBSRAM2 clock enabled during CSleep mode.." bitfld.long 0x8 29. "AHBSRAM1LPEN,AHBSRAM1 clock enable during CSleep mode" "0: AHBSRAM1 clock disabled during CSleep mode,1: AHBSRAM1 clock enabled during CSleep mode.." newline bitfld.long 0x8 11. "DFSDMDMALPEN,DFSDMDMA clock enable during CSleep mode" "0: DFSDMDMA clock disabled during CSleep mode,1: DFSDMDMA clock enabled during CSleep mode.." bitfld.long 0x8 9. "SDMMC2LPEN,SDMMC2 and SDMMC2 delay clock enable during CSleep mode" "0: SDMMC2 and SDMMC2 delay clock disabled during..,1: SDMMC2 and SDMMC2 delay clock enabled during.." newline bitfld.long 0x8 6. "RNGLPEN,RNG peripheral clock enable during CSleep mode" "0: RNG peripheral clocks disabled during CSleep mode,1: RNG peripheral clock enabled during CSleep mode.." bitfld.long 0x8 0. "DCMI_PSSILPEN,digital camera interface peripheral clock enable during CSleep mode (DCMI or PSSI depending which IP is active)" "0: DCMI/PSSI peripheral clock disabled during..,1: DCMI/PSSI peripheral clock enabled during CSleep.." line.long 0xC "RCC_AHB4LPENR," bitfld.long 0xC 29. "SRDSRAMLPEN,SmartRun domain SRAM clock enable during CSleep mode" "0: SRDSRAM clock disabled during CSleep mode,1: SRDSRAM clock enabled during CSleep mode.." bitfld.long 0xC 28. "BKPRAMLPEN,Backup RAM clock enable during CSleep mode" "0: Backup RAM clock disabled during CSleep mode,1: Backup RAM clock enabled during CSleep mode.." newline bitfld.long 0xC 21. "BDMA2LPEN,SmartRun domain DMA and DMAMUX clock enable during CSleep mode" "0: BDMA2 and DMAMUX2 clock disabled during CSleep..,1: BDMA2 and DMAMUX2 clock enabled during CSleep.." bitfld.long 0xC 10. "GPIOKLPEN,GPIOK peripheral clock enable during CSleep mode" "0: GPIOK peripheral clock disabled during CSleep mode,1: GPIOK peripheral clock enabled during CSleep.." newline bitfld.long 0xC 9. "GPIOJLPEN,GPIOJ peripheral clock enable during CSleep mode" "0: GPIOJ peripheral clock disabled during CSleep mode,1: GPIOJ peripheral clock enabled during CSleep.." bitfld.long 0xC 8. "GPIOILPEN,GPIOI peripheral clock enable during CSleep mode" "0: GPIOI peripheral clock disabled during CSleep mode,1: GPIOI peripheral clock enabled during CSleep.." newline bitfld.long 0xC 7. "GPIOHLPEN,GPIOH peripheral clock enable during CSleep mode" "0: GPIOH peripheral clock disabled during CSleep mode,1: GPIOH peripheral clock enabled during CSleep.." bitfld.long 0xC 6. "GPIOGLPEN,GPIOG peripheral clock enable during CSleep mode" "0: GPIOG peripheral clock disabled during CSleep mode,1: GPIOG peripheral clock enabled during CSleep.." newline bitfld.long 0xC 5. "GPIOFLPEN,GPIOF peripheral clock enable during CSleep mode" "0: GPIOF peripheral clock disabled during CSleep mode,1: GPIOF peripheral clock enabled during CSleep.." bitfld.long 0xC 4. "GPIOELPEN,GPIOE peripheral clock enable during CSleep mode" "0: GPIOE peripheral clock disabled during CSleep mode,1: GPIOE peripheral clock enabled during CSleep.." newline bitfld.long 0xC 3. "GPIODLPEN,GPIOD peripheral clock enable during CSleep mode" "0: GPIOD peripheral clock disabled during CSleep mode,1: GPIOD peripheral clock enabled during CSleep.." bitfld.long 0xC 2. "GPIOCLPEN,GPIOC peripheral clock enable during CSleep mode" "0: GPIOC peripheral clock disabled during CSleep mode,1: GPIOC peripheral clock enabled during CSleep.." newline bitfld.long 0xC 1. "GPIOBLPEN,GPIOB peripheral clock enable during CSleep mode" "0: GPIOB peripheral clock disabled during CSleep mode,1: GPIOB peripheral clock enabled during CSleep.." bitfld.long 0xC 0. "GPIOALPEN,GPIOA peripheral clock enable during CSleep mode" "0: GPIOA peripheral clock disabled during CSleep mode,1: GPIOA peripheral clock enabled during CSleep.." line.long 0x10 "RCC_APB3LPENR," bitfld.long 0x10 6. "WWDGLPEN,WWDG clock enable during CSleep mode" "0: WWDG clock disable during CSleep mode,1: WWDG clock enabled during CSleep mode (default.." bitfld.long 0x10 3. "LTDCLPEN,LTDC peripheral clock enable during CSleep mode" "0: LTDC clock disabled during CSleep mode,1: LTDC clock provided to the LTDC during CSleep.." line.long 0x14 "RCC_APB1LLPENR," bitfld.long 0x14 31. "UART8LPEN,UART8 peripheral clocks enable during CSleep mode" "0: UART8 peripheral clocks disabled during CSleep..,1: UART8 peripheral clocks enabled during CSleep.." bitfld.long 0x14 30. "UART7LPEN,UART7 peripheral clocks enable during CSleep mode" "0: UART7 peripheral clocks disabled during CSleep..,1: UART7 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 29. "DAC1LPEN,DAC1 (containing two converters) peripheral clock enable during CSleep mode" "0: DAC1 peripheral clock disabled during CSleep mode,1: DAC1 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 27. "CECLPEN,HDMI-CEC peripheral clocks enable during CSleep mode" "0: HDMI-CEC peripheral clocks disabled during..,1: HDMI-CEC peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 23. "I2C3LPEN,I2C3 peripheral clocks enable during CSleep mode" "0: I2C3 peripheral clocks disabled during CSleep mode,1: I2C3 peripheral clocks enabled during CSleep.." bitfld.long 0x14 22. "I2C2LPEN,I2C2 peripheral clocks enable during CSleep mode" "0: I2C2 peripheral clocks disabled during CSleep mode,1: I2C2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 21. "I2C1LPEN,I2C1 peripheral clocks enable during CSleep mode" "0: I2C1 peripheral clocks disabled during CSleep mode,1: I2C1 peripheral clocks enabled during CSleep.." bitfld.long 0x14 20. "UART5LPEN,UART5 peripheral clocks enable during CSleep mode" "0: UART5 peripheral clocks disabled during CSleep..,1: UART5 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 19. "UART4LPEN,UART4 peripheral clocks enable during CSleep mode" "0: UART4 peripheral clocks disabled during CSleep..,1: UART4 peripheral clocks enabled during CSleep.." bitfld.long 0x14 18. "USART3LPEN,USART3 peripheral clocks enable during CSleep mode" "0: USART3 peripheral clocks disabled during CSleep..,1: USART3 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 17. "USART2LPEN,USART2 peripheral clocks enable during CSleep mode" "0: USART2 peripheral clocks disabled during CSleep..,1: USART2 peripheral clocks enabled during CSleep.." bitfld.long 0x14 16. "SPDIFRXLPEN,SPDIFRX peripheral clocks enable during CSleep mode" "0: SPDIFRX peripheral clocks disabled during CSleep..,1: SPDIFRX peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 15. "SPI3LPEN,SPI3 peripheral clocks enable during CSleep mode" "0: SPI3 peripheral clocks disabled during CSleep mode,1: SPI3 peripheral clocks enabled during CSleep.." bitfld.long 0x14 14. "SPI2LPEN,SPI2 peripheral clocks enable during CSleep mode" "0: SPI2 peripheral clocks disabled during CSleep mode,1: SPI2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 9. "LPTIM1LPEN,LPTIM1 peripheral clocks enable during CSleep mode" "0: LPTIM1 peripheral clocks disabled during CSleep..,1: LPTIM1 peripheral clocks enabled during CSleep.." bitfld.long 0x14 8. "TIM14LPEN,TIM14 peripheral clock enable during CSleep mode" "0: TIM14 peripheral clock disabled during CSleep mode,1: TIM14 peripheral clock enabled during CSleep.." newline bitfld.long 0x14 7. "TIM13LPEN,TIM13 peripheral clock enable during CSleep mode" "0: TIM13 peripheral clock disabled during CSleep mode,1: TIM13 peripheral clock enabled during CSleep.." bitfld.long 0x14 6. "TIM12LPEN,TIM12 peripheral clock enable during CSleep mode" "0: TIM12 peripheral clock disabled during CSleep mode,1: TIM12 peripheral clock enabled during CSleep.." newline bitfld.long 0x14 5. "TIM7LPEN,TIM7 peripheral clock enable during CSleep mode" "0: TIM7 peripheral clock disabled during CSleep mode,1: TIM7 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 4. "TIM6LPEN,TIM6 peripheral clock enable during CSleep mode" "0: TIM6 peripheral clock disabled during CSleep mode,1: TIM6 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x14 3. "TIM5LPEN,TIM5 peripheral clock enable during CSleep mode" "0: TIM5 peripheral clock disabled during CSleep mode,1: TIM5 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 2. "TIM4LPEN,TIM4 peripheral clock enable during CSleep mode" "0: TIM4 peripheral clock disabled during CSleep mode,1: TIM4 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x14 1. "TIM3LPEN,TIM3 peripheral clock enable during CSleep mode" "0: TIM3 peripheral clock disabled during CSleep mode,1: TIM3 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 0. "TIM2LPEN,TIM2 peripheral clock enable during CSleep mode" "0: TIM2 peripheral clock disabled during CSleep mode,1: TIM2 peripheral clock enabled during CSleep mode.." line.long 0x18 "RCC_APB1HLPENR," bitfld.long 0x18 8. "FDCANLPEN,FDCAN peripheral clocks enable during CSleep mode" "0: FDCAN peripheral clocks disabled during CSleep..,1: FDCAN peripheral clocks enabled during CSleep.." bitfld.long 0x18 5. "MDIOSLPEN,MDIOS peripheral clock enable during CSleep mode" "0: MDIOS peripheral clock disabled during CSleep mode,1: MDIOS peripheral clock enabled during CSleep.." newline bitfld.long 0x18 4. "OPAMPLPEN,OPAMP peripheral clock enable during CSleep mode" "0: OPAMP peripheral clock disabled during CSleep mode,1: OPAMP peripheral clock enabled during CSleep.." bitfld.long 0x18 2. "SWPMILPEN,SWPMI peripheral clocks enable during CSleep mode" "0: SWPMI peripheral clocks disabled during CSleep..,1: SWPMI peripheral clocks enabled during CSleep.." newline bitfld.long 0x18 1. "CRSLPEN,clock recovery system peripheral clock enable during CSleep mode" "0: CRS peripheral clock disabled during CSleep mode,1: CRS peripheral clock enabled during CSleep mode.." line.long 0x1C "RCC_APB2LPENR," bitfld.long 0x1C 30. "DFSDM1LPEN,DFSDM1 peripheral clocks enable during CSleep mode" "0: DFSDM1 peripheral clocks disabled during CSleep..,1: DFSDM1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 23. "SAI2LPEN,SAI2 peripheral clocks enable during CSleep mode" "0: SAI2 peripheral clocks disabled during CSleep mode,1: SAI2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 22. "SAI1LPEN,SAI1 peripheral clocks enable during CSleep mode" "0: SAI1 peripheral clocks disabled during CSleep mode,1: SAI1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 20. "SPI5LPEN,SPI5 peripheral clocks enable during CSleep mode" "0: SPI5 peripheral clocks disabled during CSleep mode,1: SPI5 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 18. "TIM17LPEN,TIM17 peripheral clock enable during CSleep mode" "0: TIM17 peripheral clock disabled during CSleep mode,1: TIM17 peripheral clock enabled during CSleep.." bitfld.long 0x1C 17. "TIM16LPEN,TIM16 peripheral clock enable during CSleep mode" "0: TIM16 peripheral clock disabled during CSleep mode,1: TIM16 peripheral clock enabled during CSleep.." newline bitfld.long 0x1C 16. "TIM15LPEN,TIM15 peripheral clock enable during CSleep mode" "0: TIM15 peripheral clock disabled during CSleep mode,1: TIM15 peripheral clock enabled during CSleep.." bitfld.long 0x1C 13. "SPI4LPEN,SPI4 peripheral clock enable during CSleep mode" "0: SPI4 peripheral clocks disabled during CSleep mode,1: SPI4 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 12. "SPI1LPEN,SPI1 peripheral clock enable during CSleep mode" "0: SPI1 peripheral clocks disabled during CSleep mode,1: SPI1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 7. "USART10LPEN,USART10 peripheral clock enable during CSleep mode" "0: USART10 peripheral clocks disabled during CSleep..,1: USART10 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 6. "UART9LPEN,UART9 peripheral clock enable during CSleep mode" "0: UART9 peripheral clocks disabled during CSleep..,1: UART9 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 5. "USART6LPEN,USART6 peripheral clock enable during CSleep mode" "0: USART6 peripheral clocks disabled during CSleep..,1: USART6 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 4. "USART1LPEN,USART1 peripheral clock enable during CSleep mode" "0: USART1 peripheral clocks disabled during CSleep..,1: USART1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 1. "TIM8LPEN,TIM8 peripheral clock enable during CSleep mode" "0: TIM8 peripheral clock disabled during CSleep mode,1: TIM8 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x1C 0. "TIM1LPEN,TIM1 peripheral clock enable during CSleep mode" "0: TIM1 peripheral clock disabled during CSleep mode,1: TIM1 peripheral clock enabled during CSleep mode.." line.long 0x20 "RCC_APB4LPENR," bitfld.long 0x20 27. "DFSDM2LPEN,DFSDM2 peripheral clock enable during CSleep mode" "0: DFSDM2 peripheral clock disabled during CSleep..,1: DFSDM2 peripheral clock enabled during CSleep.." bitfld.long 0x20 26. "DTSLPEN,temperature sensor peripheral clock enable during CSleep mode" "0: DTS peripheral clock disabled during CSleep mode,1: DTS peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 16. "RTCAPBLPEN,RTC APB clock enable during CSleep mode" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.." bitfld.long 0x20 15. "VREFLPEN,VREF peripheral clock enable during CSleep mode" "0: VREF peripheral clock disabled during CSleep mode,1: VREF peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 14. "COMP12LPEN,COMP1 and 2 peripheral clock enable during CSleep mode" "0: COMP1 and 2 peripheral clock disabled during..,1: COMP1 and 2 peripheral clock enabled during.." bitfld.long 0x20 13. "DAC2LPEN,DAC2 (containing one converter) peripheral clock enable during CSleep mode" "0: DAC2 peripheral clock disabled during CSleep mode,1: DAC2 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 10. "LPTIM3LPEN,LPTIM3 peripheral clocks enable during CSleep mode" "0: LPTIM3 peripheral clocks disabled during CSleep..,1: LPTIM3 peripheral clocks enabled during CSleep.." bitfld.long 0x20 9. "LPTIM2LPEN,LPTIM2 peripheral clocks enable during CSleep mode" "0: LPTIM2 peripheral clocks disabled during CSleep..,1: LPTIM2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x20 7. "I2C4LPEN,I2C4 peripheral clocks enable during CSleep mode" "0: I2C4 peripheral clocks disabled during CSleep mode,1: I2C4 peripheral clocks enabled during CSleep.." bitfld.long 0x20 5. "SPI6LPEN,SPI6 peripheral clocks enable during CSleep mode" "0: SPI6 peripheral clocks disabled during CSleep mode,1: SPI6 peripheral clocks enabled during CSleep.." newline bitfld.long 0x20 3. "LPUART1LPEN,LPUART1 peripheral clocks enable during CSleep mode" "0: LPUART1 peripheral clocks disabled during CSleep..,1: LPUART1 peripheral clocks enabled during CSleep.." bitfld.long 0x20 1. "SYSCFGLPEN,SYSCFG peripheral clock enable during CSleep mode" "0: SYSCFG peripheral clock disabled during CSleep..,1: SYSCFG peripheral clock enabled during CSleep.." endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x7 line.long 0x0 "RCC_CR," rbitfld.long 0x0 29. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked (default after reset),1: PLL3 locked" bitfld.long 0x0 28. "PLL3ON,PLL3 enable" "0: PLL3 OFF (default after reset),1: PLL3 ON" newline rbitfld.long 0x0 27. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked (default after reset),1: PLL2 locked" bitfld.long 0x0 26. "PLL2ON,PLL2 enable" "0: PLL2 OFF (default after reset),1: PLL2 ON" newline rbitfld.long 0x0 25. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked (default after reset),1: PLL1 locked" bitfld.long 0x0 24. "PLL1ON,PLL1 enable" "0: PLL1 OFF (default after reset),1: PLL1 ON" newline bitfld.long 0x0 20. "HSEEXT,external high speed clock type in Bypass mode" "0: HSE in analog mode (default after reset),1: HSE in digital mode" bitfld.long 0x0 19. "HSECSSON,HSE clock security system enable" "0: CSS on HSE OFF (clock detector OFF) (default..,1: CSS on HSE ON (clock detector ON if the HSE.." newline bitfld.long 0x0 18. "HSEBYP,HSE clock bypass" "0: HSE oscillator not bypassed (default after reset),1: HSE oscillator bypassed with an external clock" rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE clock is not ready (default after reset),1: HSE clock is ready" newline bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE is OFF (default after reset),1: HSE is ON" rbitfld.long 0x0 15. "CDCKRDY,CPU domain clocks ready flag" "0: CPU domain clocks are not available (default..,1: CPU domain clocks are available" newline rbitfld.long 0x0 14. "CPUCKRDY,CPU related clocks ready flag" "0: CPU related clocks are not available (default..,1: CPU related clocks are available" rbitfld.long 0x0 13. "HSI48RDY,HSI48 clock ready flag" "0: HSI48 clock is not ready (default after reset),1: HSI48 clock is ready" newline bitfld.long 0x0 12. "HSI48ON,HSI48 clock enable" "0: HSI48 is OFF (default after reset),1: HSI48 is ON" bitfld.long 0x0 9. "CSIKERON,CSI clock enable in Stop mode" "0: no effect on CSI (default after reset),1: CSI is forced to ON even in Stop mode" newline rbitfld.long 0x0 8. "CSIRDY,CSI clock ready flag" "0: CSI clock is not ready (default after reset),1: CSI clock is ready" bitfld.long 0x0 7. "CSION,CSI clock enable" "0: CSI is OFF (default after reset),1: CSI is ON" newline rbitfld.long 0x0 5. "HSIDIVF,HSI divider flag" "0: new division ratio not yet propagated to..,1: hsi(_ker)_ck clock frequency reflects the new.." bitfld.long 0x0 3.--4. "HSIDIV,HSI clock divider" "0: division by 1 hsi(_ker)_ck = 64 MHz (default..,1: division by 2 hsi(_ker)_ck = 32 MHz,2: division by 4 hsi(_ker)_ck = 16 MHz,3: division by 8 hsi(_ker)_ck = 8 MHz" newline rbitfld.long 0x0 2. "HSIRDY,HSI clock ready flag" "0: HSI clock is not ready (default after reset),1: HSI clock is ready" bitfld.long 0x0 1. "HSIKERON,HSI clock enable in Stop mode" "0: no effect on HSI (default after reset),1: HSI is forced to ON even in Stop mode" newline bitfld.long 0x0 0. "HSION,HSI clock enable" "0: HSI is OFF,1: HSI is ON (default after reset)" line.long 0x4 "RCC_HSICFGR,RCC HSI calibration register" hexmask.long.byte 0x4 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x4 0.--11. 1. "HSICAL,HSI clock calibration" rgroup.long 0x8++0x3 line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register" hexmask.long.word 0x0 0.--9. 1. "HSI48CAL,Internal RC 48 MHz clock calibration" group.long 0xC++0x7 line.long 0x0 "RCC_CSICFGR,RCC CSI calibration register" hexmask.long.byte 0x0 24.--29. 1. "CSITRIM,CSI clock trimming" hexmask.long.byte 0x0 0.--7. 1. "CSICAL,CSI clock calibration" line.long 0x4 "RCC_CFGR," bitfld.long 0x4 29.--31. "MCO2SEL,microcontroller clock output 2" "0: system clock selected (sys_ck) (default after..,1: PLL2 oscillator clock selected (pll2_p_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_p_ck),4: CSI clock selected (csi_ck),5: LSI clock selected (lsi_ck),?,?" hexmask.long.byte 0x4 25.--28. 1. "MCO2PRE,MCO2 prescaler" newline bitfld.long 0x4 22.--24. "MCO1SEL,Microcontroller clock output 1" "0: HSI clock selected (hsi_ck) (default after reset),1: LSE oscillator clock selected (lse_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_q_ck),4: HSI48 clock selected (hsi48_ck),?,?,?" hexmask.long.byte 0x4 18.--21. 1. "MCO1PRE,MCO1 prescaler" newline bitfld.long 0x4 15. "TIMPRE,timers clocks prescaler selection" "0: The timers kernel clock is equal to rcc_hclk1 if..,1: The timers kernel clock is equal to 2 x.." hexmask.long.byte 0x4 8.--13. 1. "RTCPRE,HSE division factor for RTC clock" newline bitfld.long 0x4 7. "STOPKERWUCK,kernel clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" bitfld.long 0x4 6. "STOPWUCK,system clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" newline rbitfld.long 0x4 3.--5. "SWS,system clock switch status" "0: HSI used as system clock (hsi_ck) (default after..,1: CSI used as system clock (csi_ck),2: HSE used as system clock (hse_ck),3: PLL1 used as system clock (pll1_p_ck),?,?,?,?" bitfld.long 0x4 0.--2. "SW,system clock and trace clock switch" "0: HSI selected as system clock (hsi_ck) (default..,1: CSI selected as system clock (csi_ck),2: HSE selected as system clock (hse_ck),3: PLL1 selected as system clock (pll1_p_ck for..,?,?,?,?" group.long 0x18++0xB line.long 0x0 "RCC_CDCFGR1," hexmask.long.byte 0x0 8.--11. 1. "CDCPRE,CPU domain core prescaler" bitfld.long 0x0 4.--6. "CDPPRE,CPU domain APB3 prescaler" "?,?,?,?,4: rcc_pclk3 = rcc_hclk3 / 2,5: rcc_pclk3 = rcc_hclk3 / 4,6: rcc_pclk3 = rcc_hclk3 / 8,7: rcc_pclk3 = rcc_hclk3 / 16" newline hexmask.long.byte 0x0 0.--3. 1. "HPRE,CPU domain AHB prescaler" line.long 0x4 "RCC_CDCFGR2," bitfld.long 0x4 8.--10. "CDPPRE2,CPU domain APB2 prescaler" "?,?,?,?,4: rcc_pclk2 = rcc_hclk1 / 2,5: rcc_pclk2 = rcc_hclk1 / 4,6: rcc_pclk2 = rcc_hclk1 / 8,7: rcc_pclk2 = rcc_hclk1 / 16" bitfld.long 0x4 4.--6. "CDPPRE1,CPU domain APB1 prescaler" "?,?,?,?,4: rcc_pclk1 = rcc_hclk1 / 2,5: rcc_pclk1 = rcc_hclk1 / 4,6: rcc_pclk1 = rcc_hclk1 / 8,7: rcc_pclk1 = rcc_hclk1 / 16" line.long 0x8 "RCC_SRDCFGR," bitfld.long 0x8 4.--6. "SRDPPRE,SmartRun domain APB4 prescaler" "?,?,?,?,4: rcc_pclk4 = rcc_hclk4 / 2,5: rcc_pclk4 = rcc_hclk4 / 4,6: rcc_pclk4 = rcc_hclk4 / 8,7: rcc_pclk4 = rcc_hclk4 / 16" group.long 0x28++0x1F line.long 0x0 "RCC_PLLCKSELR," hexmask.long.byte 0x0 20.--25. 1. "DIVM3,prescaler for PLL3" hexmask.long.byte 0x0 12.--17. 1. "DIVM2,prescaler for PLL2" newline hexmask.long.byte 0x0 4.--9. 1. "DIVM1,prescaler for PLL1" bitfld.long 0x0 0.--1. "PLLSRC,DIVMx and PLLs clock source selection" "0: HSI selected as PLL clock (hsi_ck) (default..,1: CSI selected as PLL clock (csi_ck),2: HSE selected as PLL clock (hse_ck),3: no clock send to DIVMx divider and PLLs" line.long 0x4 "RCC_PLLCFGR," bitfld.long 0x4 24. "DIVR3EN,PLL3 DIVR divider output enable" "0: pll3_r_ck output disabled,1: pll3_r_ck output enabled (default after reset)" bitfld.long 0x4 23. "DIVQ3EN,PLL3 DIVQ divider output enable" "0: pll3_q_ck output disabled,1: pll3_q_ck output enabled (default after reset)" newline bitfld.long 0x4 22. "DIVP3EN,PLL3 DIVP divider output enable" "0: pll3_p_ck output disabled,1: pll3_p_ck output enabled (default after reset)" bitfld.long 0x4 21. "DIVR2EN,PLL2 DIVR divider output enable" "0: pll2_r_ck output disabled,1: pll2_r_ck output enabled (default after reset)" newline bitfld.long 0x4 20. "DIVQ2EN,PLL2 DIVQ divider output enable" "0: pll2_q_ck output disabled,1: pll2_q_ck output enabled (default after reset)" bitfld.long 0x4 19. "DIVP2EN,PLL2 DIVP divider output enable" "0: pll2_p_ck output disabled,1: pll2_p_ck output enabled (default after reset)" newline bitfld.long 0x4 18. "DIVR1EN,PLL1 DIVR divider output enable" "0: pll1_r_ck output disabled,1: pll1_r_ck output enabled (default after reset)" bitfld.long 0x4 17. "DIVQ1EN,PLL1 DIVQ divider output enable" "0: pll1_q_ck output disabled,1: pll1_q_ck output enabled (default after reset)" newline bitfld.long 0x4 16. "DIVP1EN,PLL1 DIVP divider output enable" "0: pll1_p_ck output disabled,1: pll1_p_ck output enabled (default after reset)" bitfld.long 0x4 10.--11. "PLL3RGE,PLL3 input frequency range" "0: PLL3 input (ref3_ck) clock range frequency..,1: PLL3 input (ref3_ck) clock range frequency..,2: PLL3 input (ref3_ck) clock range frequency..,3: PLL3 input (ref3_ck) clock range frequency.." newline bitfld.long 0x4 9. "PLL3VCOSEL,PLL3 VCO selection" "0: wide VCO range 128 to 560 MHz (default after..,1: medium VCO range 150 to 420 MHz" bitfld.long 0x4 8. "PLL3FRACEN,PLL3 fractional latch enable" "0,1" newline bitfld.long 0x4 6.--7. "PLL2RGE,PLL2 input frequency range" "0: PLL2 input (ref2_ck) clock range frequency..,1: PLL2 input (ref2_ck) clock range frequency..,2: PLL2 input (ref2_ck) clock range frequency..,3: PLL2 input (ref2_ck) clock range frequency.." bitfld.long 0x4 5. "PLL2VCOSEL,PLL2 VCO selection" "0: wide VCO range 128 to 560 MHz (default after..,1: medium VCO range 150 to 420 MHz" newline bitfld.long 0x4 4. "PLL2FRACEN,PLL2 fractional latch enable" "0,1" bitfld.long 0x4 2.--3. "PLL1RGE,PLL1 input frequency range" "0: PLL1 input (ref1_ck) clock range frequency..,1: PLL1 input (ref1_ck) clock range frequency..,2: PLL1 input (ref1_ck) clock range frequency..,3: PLL1 input (ref1_ck) clock range frequency.." newline bitfld.long 0x4 1. "PLL1VCOSEL,PLL1 VCO selection" "0: wide VCO range from 128 to 560 MHz (default..,1: medium VCO range from 150 to 420 MHz" bitfld.long 0x4 0. "PLL1FRACEN,PLL1 fractional latch enable" "0,1" line.long 0x8 "RCC_PLL1DIVR," hexmask.long.byte 0x8 24.--30. 1. "DIVR1,PLL1 DIVR division factor" hexmask.long.byte 0x8 16.--22. 1. "DIVQ1,PLL1 DIVQ division factor" newline hexmask.long.byte 0x8 9.--15. 1. "DIVP1,PLL1 DIVP division factor" hexmask.long.word 0x8 0.--8. 1. "DIVN1,multiplication factor for PLL1 VCO" line.long 0xC "RCC_PLL1FRACR," hexmask.long.word 0xC 3.--15. 1. "FRACN1,fractional part of the multiplication factor for PLL1 VCO" line.long 0x10 "RCC_PLL2DIVR," hexmask.long.byte 0x10 24.--30. 1. "DIVR2,PLL2 DIVR division factor" hexmask.long.byte 0x10 16.--22. 1. "DIVQ2,PLL2 DIVQ division factor" newline hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL2 DIVP division factor" hexmask.long.word 0x10 0.--8. 1. "DIVN2,multiplication factor for PLL2 VCO" line.long 0x14 "RCC_PLL2FRACR," hexmask.long.word 0x14 3.--15. 1. "FRACN2,fractional part of the multiplication factor for PLL2 VCO" line.long 0x18 "RCC_PLL3DIVR," hexmask.long.byte 0x18 24.--30. 1. "DIVR3,PLL3 DIVR division factor" hexmask.long.byte 0x18 16.--22. 1. "DIVQ3,PLL3 DIVQ division factor" newline hexmask.long.byte 0x18 9.--15. 1. "DIVP3,PLL3 DIVP division factor" hexmask.long.word 0x18 0.--8. 1. "DIVN3,Multiplication factor for PLL3 VCO" line.long 0x1C "RCC_PLL3FRACR," hexmask.long.word 0x1C 3.--15. 1. "FRACN3,fractional part of the multiplication factor for PLL3 VCO" group.long 0x4C++0xF line.long 0x0 "RCC_CDCCIPR,RCC CPU domain kernel clock configuration register" bitfld.long 0x0 28.--29. "CKPERSEL,per_ck clock source selection" "0: hsi_ker_ck selected as per_ck clock (default..,1: csi_ker_ck selected as per_ck clock,2: hse_ck selected as per_ck clock,3: reserved the per_ck clock is disabled" bitfld.long 0x0 16. "SDMMCSEL,SDMMC kernel clock source selection" "0: pll1_q_ck selected as kernel peripheral clock..,1: pll2_r_ck selected as kernel peripheral clock" newline bitfld.long 0x0 4.--5. "OCTOSPISEL,OCTOSPI kernel clock source selection" "0: rcc_hclk3 selected as kernel peripheral clock..,1: pll1_q_ck selected as kernel peripheral clock,2: pll2_r_ck selected as kernel peripheral clock,3: per_ck selected as kernel peripheral clock" bitfld.long 0x0 0.--1. "FMCSEL,FMC kernel clock source selection" "0: rcc_hclk3 selected as kernel peripheral clock..,1: pll1_q_ck selected as kernel peripheral clock,2: pll2_r_ck selected as kernel peripheral clock,3: per_ck selected as kernel peripheral clock" line.long 0x4 "RCC_CDCCIP1R,RCC CPU domain kernel clock configuration register" bitfld.long 0x4 31. "SWPMISEL,SWPMI kernel clock source selection" "0: rcc_pclk1 selected as SWPMI kernel clock..,1: hsi_ker_ck selected as SWPMI kernel clock" bitfld.long 0x4 28.--29. "FDCANSEL,FDCAN kernel clock source selection" "0: hse_ck clock selected as FDCAN kernel clock..,1: pll1_q_ck selected as FDCAN kernel clock,2: pll2_q_ck selected as FDCAN kernel clock,3: reserved the kernel clock is disabled" newline bitfld.long 0x4 24. "DFSDM1SEL,DFSDM1 kernel clock Clk source selection" "0: rcc_pclk2 selected as DFSDM1 Clk kernel clock..,1: sys_ck selected as DFSDM1 Clk kernel clock" bitfld.long 0x4 20.--21. "SPDIFRXSEL,SPDIFRX kernel clock source selection" "0: pll1_q_ck selected as SPDIFRX kernel clock..,1: pll2_r_ck selected as SPDIFRX kernel clock,2: pll3_r_ck selected as SPDIFRX kernel clock,3: hsi_ker_ck selected as SPDIFRX kernel clock" newline bitfld.long 0x4 16.--18. "SPI45SEL,SPI4 and 5 kernel clock source selection" "0: rcc_pclk2 clock selected as kernel clock..,1: pll2_q_ck is selected as kernel clock,2: pll3_q_ck is selected as kernel clock,3: hsi_ker_ck is selected as kernel clock,4: csi_ker_ck is selected as kernel clock,5: hse_ck is selected as kernel clock,?,?" bitfld.long 0x4 12.--14. "SPI123SEL,SPI/I2S1 2 and 3 kernel clock source selection" "0: pll1_q_ck selected as SPI/I2S1 2 and 3 kernel..,1: pll2_p_ck selected as SPI/I2S1 2 and 3 kernel..,2: pll3_p_ck selected as SPI/I2S1 2 and 3 kernel..,3: I2S_CKIN selected as SPI/I2S1 2 and 3 kernel clock,4: per_ck selected as SPI/I2S1 2 and 3 kernel clock,?,?,?" newline bitfld.long 0x4 9.--11. "SAI2BSEL,SAI2 kernel clock B source selection" "0: pll1_q_ck selected as SAI2 kernel clock B..,1: pll2_p_ck selected as SAI2 kernel clock B,2: pll3_p_ck selected as SAI2 kernel clock B,3: I2S_CKIN selected as SAI2 kernel clock B,4: per_ck selected as SAI2 kernel clock B,5: spdifrx_symb_ck selected as SAI2 kernel clock B,?,?" bitfld.long 0x4 6.--8. "SAI2ASEL,SAI2 kernel clock source A selection" "0: pll1_q_ck selected as SAI2 kernel clock A..,1: pll2_p_ck selected as SAI2 kernel clock A,2: pll3_p_ck selected as SAI2 kernel clock A,3: I2S_CKIN selected as SAI2 kernel clock A,4: per_ck selected as SAI2 kernel clock A,5: spdifrx_symb_ck selected as SAI2 kernel clock A,?,?" newline bitfld.long 0x4 0.--2. "SAI1SEL,SAI1 and DFSDM1 kernel Aclk clock source selection" "0: pll1_q_ck selected as SAI1 and DFSDM1 Aclk..,1: pll2_p_ck selected as SAI1 and DFSDM1 Aclk..,2: pll3_p_ck selected as SAI1 and DFSDM1 Aclk..,3: I2S_CKIN selected as SAI1 and DFSDM1 Aclk kernel..,4: per_ck selected as SAI1 and DFSDM1 Aclk kernel..,?,?,?" line.long 0x8 "RCC_CDCCIP2R,RCC CPU domain kernel clock configuration register" bitfld.long 0x8 28.--30. "LPTIM1SEL,LPTIM1 kernel clock source selection" "0: rcc_pclk1 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" bitfld.long 0x8 22.--23. "CECSEL,HDMI-CEC kernel clock source selection" "0: lse_ck selected as kernel clock (default after..,1: lsi_ck selected as kernel clock,2: csi_ker_ck divided by 122 selected as kernel..,3: reserved the kernel clock is disabled" newline bitfld.long 0x8 20.--21. "USBSEL,USBOTG 1 and 2 kernel clock source selection" "0: Disable the kernel clock (default after reset),1: pll1_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi48_ck selected as kernel clock" bitfld.long 0x8 12.--13. "I2C123SEL,I2C1 2 3 kernel clock source selection" "0: rcc_pclk1 selected as kernel clock (default..,1: pll3_r_ck selected as kernel clock,2: hsi_ker_ck selected as kernel clock,3: csi_ker_ck selected as kernel clock" newline bitfld.long 0x8 8.--9. "RNGSEL,RNG kernel clock source selection" "0: hsi48_ck selected as kernel clock (default after..,1: pll1_q_ck selected as kernel clock,2: lse_ck selected as kernel clock,3: lsi_ck selected as kernel clock" bitfld.long 0x8 3.--5. "USART16910SEL,USART1 6 9 and 10 kernel clock source selection" "0: rcc_pclk2 selected as kernel clock (default..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?" newline bitfld.long 0x8 0.--2. "USART234578SEL,USART2/3 UART4 5 7 and 8 (APB1) kernel clock source selection" "0: rcc_pclk1 selected as kernel clock (default..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?" line.long 0xC "RCC_SRDCCIPR,RCC SmartRun domain kernel clock configuration register" bitfld.long 0xC 28.--30. "SPI6SEL,SPI6 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: hse_ck selected as kernel peripheral clock,6: I2S_CKIN selected as kernel peripheral clock,?" bitfld.long 0xC 27. "DFSDM2SEL,DFSDM2 kernel Clk clock source selection" "0: rcc_pclk4 selected as DFSDM2 Clk kernel clock..,1: sys_ck selected as DFSDM2 Clk kernel clock" newline bitfld.long 0xC 16.--17. "ADCSEL,SAR ADC kernel clock source selection" "0: pll2_p_ck selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: per_ck selected as kernel peripheral clock,?" bitfld.long 0xC 13.--15. "LPTIM3SEL,LPTIM3 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" newline bitfld.long 0xC 10.--12. "LPTIM2SEL,LPTIM2 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" bitfld.long 0xC 8.--9. "I2C4SEL,I2C4 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: hsi_ker_ck selected as kernel peripheral clock,3: csi_ker_ck selected as kernel peripheral clock" newline bitfld.long 0xC 0.--2. "LPUART1SEL,LPUART1 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: lse_ck selected as kernel peripheral clock,?,?" group.long 0x60++0x3 line.long 0x0 "RCC_CIER," bitfld.long 0x0 9. "LSECSSIE,LSE clock security system interrupt enable" "0: LSE CSS interrupt disabled (default after reset),1: LSE CSS interrupt enabled" bitfld.long 0x0 8. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled (default after reset),1: PLL3 lock interrupt enabled" newline bitfld.long 0x0 7. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled (default after reset),1: PLL2 lock interrupt enabled" bitfld.long 0x0 6. "PLL1RDYIE,PLL1 ready interrupt enable" "0: PLL1 lock interrupt disabled (default after reset),1: PLL1 lock interrupt enabled" newline bitfld.long 0x0 5. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled (default after..,1: HSI48 ready interrupt enabled" bitfld.long 0x0 4. "CSIRDYIE,CSI ready interrupt enable" "0: CSI ready interrupt disabled (default after reset),1: CSI ready interrupt enabled" newline bitfld.long 0x0 3. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled (default after reset),1: HSE ready interrupt enabled" bitfld.long 0x0 2. "HSIRDYIE,HSI ready interrupt enable" "0: HSI ready interrupt disabled (default after reset),1: HSI ready interrupt enabled" newline bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled (default after reset),1: LSE ready interrupt enabled" bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled (default after reset),1: LSI ready interrupt enabled" rgroup.long 0x64++0x3 line.long 0x0 "RCC_CIFR," bitfld.long 0x0 10. "HSECSSF,HSE clock security system interrupt flag" "0: no clock security interrupt caused by HSE clock..,1: clock security interrupt caused by HSE clock.." bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: no failure detected on the external 32 kHz..,1: failure detected on the external 32 kHz oscillator" newline bitfld.long 0x0 8. "PLL3RDYF,PLL3 ready interrupt flag" "0: no clock ready interrupt caused by PLL3 lock..,1: clock ready interrupt caused by PLL3 lock" bitfld.long 0x0 7. "PLL2RDYF,PLL2 ready interrupt flag" "0: no clock ready interrupt caused by PLL2 lock..,1: clock ready interrupt caused by PLL2 lock" newline bitfld.long 0x0 6. "PLL1RDYF,PLL1 ready interrupt flag" "0: no clock ready interrupt caused by PLL1 lock..,1: clock ready interrupt caused by PLL1 lock" bitfld.long 0x0 5. "HSI48RDYF,HSI48 ready interrupt flag" "0: no clock ready interrupt caused by the HSI48..,1: clock ready interrupt caused by the HSI48.." newline bitfld.long 0x0 4. "CSIRDYF,CSI ready interrupt flag" "0: no clock ready interrupt caused by the CSI..,1: clock ready interrupt caused by the CSI" bitfld.long 0x0 3. "HSERDYF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE" newline bitfld.long 0x0 2. "HSIRDYF,HSI ready interrupt flag" "0: no clock ready interrupt caused by the HSI..,1: clock ready interrupt caused by the HSI" bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE" newline bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: no clock ready interrupt caused by the LSI..,1: clock ready interrupt caused by the LSI" group.long 0x68++0x3 line.long 0x0 "RCC_CICR," bitfld.long 0x0 10. "HSECSSC,HSE clock security system interrupt clear" "0: HSECSSF no effect (default after reset),1: HSECSSF cleared" bitfld.long 0x0 9. "LSECSSC,LSE clock security system interrupt clear" "0: LSECSSF no effect (default after reset),1: LSECSSF cleared" newline bitfld.long 0x0 8. "PLL3RDYC,PLL3 ready interrupt clear" "0: PLL3RDYF no effect (default after reset),1: PLL3RDYF cleared" bitfld.long 0x0 7. "PLL2RDYC,PLL2 ready interrupt clear" "0: PLL2RDYF no effect (default after reset),1: PLL2RDYF cleared" newline bitfld.long 0x0 6. "PLL1RDYC,PLL1 ready interrupt clear" "0: PLL1RDYF no effect (default after reset),1: PLL1RDYF cleared" bitfld.long 0x0 5. "HSI48RDYC,HSI48 ready interrupt clear" "0: HSI48RDYF no effect (default after reset),1: HSI48RDYF cleared" newline bitfld.long 0x0 4. "CSIRDYC,CSI ready interrupt clear" "0: CSIRDYF no effect (default after reset),1: CSIRDYF cleared" bitfld.long 0x0 3. "HSERDYC,HSE ready interrupt clear" "0: HSERDYF no effect (default after reset),1: HSERDYF cleared" newline bitfld.long 0x0 2. "HSIRDYC,HSI ready interrupt clear" "0: HSIRDYF no effect (default after reset),1: HSIRDYF cleared" bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: LSERDYF no effect (default after reset),1: LSERDYF cleared" newline bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: LSIRDYF no effect (default after reset),1: LSIRDYF cleared" group.long 0x70++0x7 line.long 0x0 "RCC_BDCR,RCC Backup domain control register" bitfld.long 0x0 16. "VSWRST,VSwitch domain software reset" "0: reset not activated (default after Backup domain..,1: resets the entire VSW domain" bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0: rtc_ck disabled (default after Backup domain..,1: rtc_ck enabled" newline bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0: no clock (default after Backup domain reset),1: LSE selected as RTC clock,2: LSI selected as RTC clock,3: HSE divided by RTCPRE value selected as RTC clock" bitfld.long 0x0 7. "LSEEXT,low-speed external clock type in Bypass mode" "0: LSE in analog mode (default after Backup domain..,1: LSE in digital mode (do not use if RTC is active)." newline rbitfld.long 0x0 6. "LSECSSD,LSE clock security system failure detection" "0: no failure detected on 32 kHz oscillator..,1: failure detected on 32 kHz oscillator" bitfld.long 0x0 5. "LSECSSON,LSE clock security system enable" "0: CSS on 32 kHz oscillator OFF (default after..,1: CSS on 32 kHz oscillator ON" newline bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator driving capability" "0: lowest drive (default after Backup domain reset),1: medium-low drive,2: medium-high drive,3: highest drive" bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed (default after..,1: LSE oscillator bypassed" newline rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready (default after Backup..,1: LSE oscillator ready" bitfld.long 0x0 0. "LSEON,LSE oscillator enabled" "0: LSE oscillator OFF (default after Backup domain..,1: LSE oscillator ON" line.long 0x4 "RCC_CSR,RCC clock control and status register" rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: LSI clock is not ready (default after reset),1: LSI clock is ready" bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0: LSI is OFF (default after reset),1: LSI is ON" group.long 0x7C++0x23 line.long 0x0 "RCC_AHB3RSTR," bitfld.long 0x0 24. "GFXMMURST,GFXMMU reset" "0: does not reset the GFXMMU (default after reset),1: resets the GFXMMU" bitfld.long 0x0 23. "OTFD2RST,OTFD2 reset" "0: does not reset the OTFD2 (default after reset),1: resets the OTFD2" newline bitfld.long 0x0 22. "OTFD1RST,OTFD1 reset" "0: does not reset the OTFD1 (default after reset),1: resets the OTFD1" bitfld.long 0x0 21. "OCTOSPIMRST,OCTOSPIM reset" "0: does not reset the OCTOSPIM (default after reset),1: resets the OCTOSPIM" newline bitfld.long 0x0 19. "OCTOSPI2RST,OCTOSPI2 and OCTOSPI2 delay block reset" "0: does not reset the OCTOSPI2 and OCTOSPI2 delay..,1: resets the OCTOSPI2 and OCTOSPI2 delay block" bitfld.long 0x0 16. "SDMMC1RST,SDMMC1 and SDMMC1 delay blocks reset" "0: does not reset SDMMC1 and SDMMC1 delay blocks..,1: resets SDMMC1 and SDMMC1 delay blocks" newline bitfld.long 0x0 14. "OCTOSPI1RST,OCTOSPI1 and OCTOSPI1 delay blocks reset" "0: does not reset OCTOSPI1 and OCTOSPI1 delay..,1: resets OCTOSPI1 and OCTOSPI1 delay blocks" bitfld.long 0x0 12. "FMCRST,FMC block reset" "0: does not reset FMC block (default after reset),1: resets FMC block" newline bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0: does not reset JPGDEC block (default after reset),1: resets JPGDEC block" bitfld.long 0x0 4. "DMA2DRST,DMA2D block reset" "0: does not reset DMA2D block (default after reset),1: resets DMA2D block" newline bitfld.long 0x0 0. "MDMARST,MDMA block reset" "0: does not reset MDMA block (default after reset),1: resets MDMA block" line.long 0x4 "RCC_AHB1RSTR," bitfld.long 0x4 25. "USB1OTGRST,USB1OTG block reset" "0: does not reset USB1OTG block (default after reset),1: resets USB1OTG block" bitfld.long 0x4 9. "CRCRST,CRC block reset" "0: does not reset CRC block (default after reset),1: resets CRC block" newline bitfld.long 0x4 5. "ADC12RST,ADC1 and 2 blocks reset" "0: does not reset ADC1 and 2 blocks (default after..,1: resets ADC1 and 2 blocks" bitfld.long 0x4 1. "DMA2RST,DMA2 and DMAMUX2 blocks reset" "0: does not reset DMA2 and DMAMUX2 blocks (default..,1: resets DMA2 and DMAMUX2 blocks" newline bitfld.long 0x4 0. "DMA1RST,DMA1 and DMAMUX1 blocks reset" "0: does not reset DMA1 and DMAMUX1 blocks (default..,1: resets DMA1 and DMAMUX1 blocks" line.long 0x8 "RCC_AHB2RSTR," bitfld.long 0x8 11. "BDMA1RST,BDMA1 reset (DFSDM dedicated DMA)" "0: does not reset DMA block (default after reset),1: resets DMA block" bitfld.long 0x8 9. "SDMMC2RST,SDMMC2 and SDMMC2 delay blocks reset" "0: does not reset SDMMC2 and SDMMC2 delay blocks..,1: resets SDMMC2 and SDMMC2 delay blocks" newline bitfld.long 0x8 6. "RNGRST,random number generator block reset" "0: does not reset RNG block (default after reset),1: resets RNG block" bitfld.long 0x8 5. "HASHRST,hash block reset" "0: does not reset hash block (default after reset),1: resets hash block" newline bitfld.long 0x8 4. "CRYPTRST,cryptography block reset" "0: does not reset cryptography block (default after..,1: resets cryptography block" bitfld.long 0x8 2. "HSEMRST,HSEM block reset" "0: does not reset HSEM block (default after reset),1: resets HSEM block" newline bitfld.long 0x8 0. "DCMI_PSSIRST,digital camera interface block reset (DCMI or PSSI depending which IP is active)" "0: does not reset the DCMI/PSSI block (default..,1: resets the DCMI/PSSI block" line.long 0xC "RCC_AHB4RSTR," bitfld.long 0xC 21. "BDMA2RST,SmartRun domain DMA and DMAMUX blocks reset" "0: does not reset the DMA and DMAMUX blocks..,1: resets the DMA and DMAMUX blocks" bitfld.long 0xC 10. "GPIOKRST,GPIOK block reset" "0: does not reset the GPIOK block (default after..,1: resets the GPIOK block" newline bitfld.long 0xC 9. "GPIOJRST,GPIOJ block reset" "0: does not reset the GPIOJ block (default after..,1: resets the GPIOJ block" bitfld.long 0xC 8. "GPIOIRST,GPIOI block reset" "0: does not reset the GPIOI block (default after..,1: resets the GPIOI block" newline bitfld.long 0xC 7. "GPIOHRST,GPIOH block reset" "0: does not reset the GPIOH block (default after..,1: resets the GPIOH block" bitfld.long 0xC 6. "GPIOGRST,GPIOG block reset" "0: does not reset the GPIOG block (default after..,1: resets the GPIOG block" newline bitfld.long 0xC 5. "GPIOFRST,GPIOF block reset" "0: does not reset the GPIOF block (default after..,1: resets the GPIOF block" bitfld.long 0xC 4. "GPIOERST,GPIOE block reset" "0: does not reset the GPIOE block (default after..,1: resets the GPIOE block" newline bitfld.long 0xC 3. "GPIODRST,GPIOD block reset" "0: does not reset the GPIOD block (default after..,1: resets the GPIOD block" bitfld.long 0xC 2. "GPIOCRST,GPIOC block reset" "0: does not reset the GPIOC block (default after..,1: resets the GPIOC block" newline bitfld.long 0xC 1. "GPIOBRST,GPIOB block reset" "0: does not reset the GPIOB block (default after..,1: resets the GPIOB block" bitfld.long 0xC 0. "GPIOARST,GPIOA block reset" "0: does not reset the GPIOA block (default after..,1: resets the GPIOA block" line.long 0x10 "RCC_APB3RSTR," bitfld.long 0x10 3. "LTDCRST,LTDC block reset" "0: does not reset the LTDC block (default after..,1: resets the LTDC block" line.long 0x14 "RCC_APB1LRSTR," bitfld.long 0x14 31. "UART8RST,UART8 block reset" "0: does not reset the UART8 block (default after..,1: resets the UART8 block" bitfld.long 0x14 30. "UART7RST,UART7 block reset" "0: does not reset the UART7 block (default after..,1: resets the UART7 block" newline bitfld.long 0x14 29. "DAC1RST,DAC1 (containing two converters) reset" "0: does not reset the DAC1 (default after reset),1: resets the DAC1" bitfld.long 0x14 27. "CECRST,HDMI-CEC block reset" "0: does not reset the HDMI-CEC block (default after..,1: resets the HDMI-CEC block" newline bitfld.long 0x14 23. "I2C3RST,I2C3 block reset" "0: does not reset the I2C3 block (default after..,1: resets the I2C3 block" bitfld.long 0x14 22. "I2C2RST,I2C2 block reset" "0: does not reset the I2C2 block (default after..,1: resets the I2C2 block" newline bitfld.long 0x14 21. "I2C1RST,I2C1 block reset" "0: does not reset the I2C1 block (default after..,1: resets the I2C1 block" bitfld.long 0x14 20. "UART5RST,UART5 block reset" "0: does not reset the UART5 block (default after..,1: resets the UART5 block" newline bitfld.long 0x14 19. "UART4RST,UART4 block reset" "0: does not reset the UART4 block (default after..,1: resets the UART4 block" bitfld.long 0x14 18. "USART3RST,USART3 block reset" "0: does not reset the USART3 block (default after..,1: resets the USART3 block" newline bitfld.long 0x14 17. "USART2RST,USART2 block reset" "0: does not reset the USART2 block (default after..,1: resets the USART2 block" bitfld.long 0x14 16. "SPDIFRXRST,SPDIFRX block reset" "0: does not reset the SPDIFRX block (default after..,1: resets the SPDIFRX block" newline bitfld.long 0x14 15. "SPI3RST,SPI3 block reset" "0: does not reset the SPI3 block (default after..,1: resets the SPI3 block" bitfld.long 0x14 14. "SPI2RST,SPI2 block reset" "0: does not reset the SPI2 block (default after..,1: resets the SPI2 block" newline bitfld.long 0x14 9. "LPTIM1RST,LPTIM1 block reset" "0: does not reset the LPTIM1 block (default after..,1: resets the LPTIM1 block" bitfld.long 0x14 8. "TIM14RST,TIM14 block reset" "0: does not reset the TIM14 block (default after..,1: resets the TIM14 block" newline bitfld.long 0x14 7. "TIM13RST,TIM13 block reset" "0: does not reset the TIM13 block (default after..,1: resets the TIM13 block" bitfld.long 0x14 6. "TIM12RST,TIM12 block reset" "0: does not reset the TIM12 block (default after..,1: resets the TIM12 block" newline bitfld.long 0x14 5. "TIM7RST,TIM7 block reset" "0: does not reset the TIM7 block (default after..,1: resets the TIM7 block" bitfld.long 0x14 4. "TIM6RST,TIM6 block reset" "0: does not reset the TIM6 block (default after..,1: resets the TIM6 block" newline bitfld.long 0x14 3. "TIM5RST,TIM5 block reset" "0: does not reset the TIM5 block (default after..,1: resets the TIM5 block" bitfld.long 0x14 2. "TIM4RST,TIM4 block reset" "0: does not reset the TIM4 block (default after..,1: resets the TIM4 block" newline bitfld.long 0x14 1. "TIM3RST,TIM3 block reset" "0: does not reset the TIM3 block (default after..,1: resets the TIM3 block" bitfld.long 0x14 0. "TIM2RST,TIM2 block reset" "0: does not reset the TIM2 block (default after..,1: resets the TIM2 block" line.long 0x18 "RCC_APB1HRSTR," bitfld.long 0x18 8. "FDCANRST,FDCAN block reset" "0: does not reset the FDCAN block (default after..,1: resets the FDCAN block" bitfld.long 0x18 5. "MDIOSRST,MDIOS block reset" "0: does not reset the MDIOS block (default after..,1: resets the MDIOS block" newline bitfld.long 0x18 4. "OPAMPRST,OPAMP block reset" "0: does not reset the OPAMP block (default after..,1: resets the OPAMP block" bitfld.long 0x18 2. "SWPMIRST,SWPMI block reset" "0: does not reset the SWPMI block (default after..,1: resets the SWPMI block" newline bitfld.long 0x18 1. "CRSRST,clock recovery system reset" "0: does not reset CRS (default after reset),1: resets CRS" line.long 0x1C "RCC_APB2RSTR," bitfld.long 0x1C 30. "DFSDM1RST,DFSDM1 block reset" "0: does not reset DFSDM1 block (default after reset),1: resets DFSDM1 block" bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0: does not reset the SAI2 block (default after..,1: resets the SAI2 block" newline bitfld.long 0x1C 22. "SAI1RST,SAI1 block reset" "0: does not reset the SAI1 (default after reset),1: resets the SAI1" bitfld.long 0x1C 20. "SPI5RST,SPI5 block reset" "0: does not reset the SPI5 block (default after..,1: resets the SPI5 block" newline bitfld.long 0x1C 18. "TIM17RST,TIM17 block reset" "0: does not reset the TIM17 block (default after..,1: resets the TIM17 block" bitfld.long 0x1C 17. "TIM16RST,TIM16 block reset" "0: does not reset the TIM16 block (default after..,1: resets the TIM16 block" newline bitfld.long 0x1C 16. "TIM15RST,TIM15 block reset" "0: does not reset the TIM15 block (default after..,1: resets the TIM15 block" bitfld.long 0x1C 13. "SPI4RST,SPI4 block reset" "0: does not reset the SPI4 block (default after..,1: resets the SPI4 block" newline bitfld.long 0x1C 12. "SPI1RST,SPI1 block reset" "0: does not reset the SPI1 block (default after..,1: resets the SPI1 block" bitfld.long 0x1C 7. "USART10RST,USART10 block reset" "0: does not reset the USART10 block (default after..,1: resets the USART10 block" newline bitfld.long 0x1C 6. "UART9RST,UART9 block reset" "0: does not reset the UART9 block (default after..,1: resets the UART9 block" bitfld.long 0x1C 5. "USART6RST,USART6 block reset" "0: does not reset the USART6 block (default after..,1: resets the USART6 block" newline bitfld.long 0x1C 4. "USART1RST,USART1 block reset" "0: does not reset the USART1 block (default after..,1: resets the USART1 block" bitfld.long 0x1C 1. "TIM8RST,TIM8 block reset" "0: does not reset the TIM8 block (default after..,1: resets the TIM8 block" newline bitfld.long 0x1C 0. "TIM1RST,TIM1 block reset" "0: does not reset the TIM1 block (default after..,1: resets the TIM1 block" line.long 0x20 "RCC_APB4RSTR," bitfld.long 0x20 27. "DFSDM2RST,DFSDM2 block reset" "0: does not reset the DFSDM2 block (default after..,1: resets the DFSDM2 block" bitfld.long 0x20 26. "DTSRST,Digital temperature sensor block reset" "0: does not reset the DTS block (default after reset),1: resets the DTS block" newline bitfld.long 0x20 15. "VREFRST,VREF block reset" "0: does not reset the VREF block (default after..,1: resets the VREF block" bitfld.long 0x20 14. "COMP12RST,COMP1 and 2 blocks reset" "0: does not reset the COMP1 and 2 blocks (default..,1: resets the COMP1 and 2 blocks" newline bitfld.long 0x20 13. "DAC2RST,DAC2 (containing one converter) reset" "0: does not reset the DAC2 (default after reset),1: resets the DAC2" bitfld.long 0x20 10. "LPTIM3RST,LPTIM3 block reset" "0: does not reset the LPTIM3 block (default after..,1: resets the LPTIM3 block" newline bitfld.long 0x20 9. "LPTIM2RST,LPTIM2 block reset" "0: does not reset the LPTIM2 block (default after..,1: resets the LPTIM2 block" bitfld.long 0x20 7. "I2C4RST,I2C4 block reset" "0: does not reset the I2C4 block (default after..,1: resets the I2C4 block" newline bitfld.long 0x20 5. "SPI6RST,SPI6 block reset" "0: does not reset the SPI6 block (default after..,1: resets the SPI6 block" bitfld.long 0x20 3. "LPUART1RST,LPUART1 block reset" "0: does not reset the LPUART1 block (default after..,1: resets the LPUART1 block" newline bitfld.long 0x20 1. "SYSCFGRST,SYSCFG block reset" "0: does not reset the SYSCFG block (default after..,1: resets the SYSCFG block" group.long 0xA8++0x3 line.long 0x0 "RCC_SRDAMR,RCC SmartRun domain Autonomous mode register" bitfld.long 0x0 29. "SRDSRAMAMEN,SmartRun domain SRAM Autonomous mode enable" "0: SRDSRAM clock disabled when the CPU is in CStop..,1: SRDSRAM bus clock enabled when the SmartRun.." bitfld.long 0x0 28. "BKPRAMAMEN,Backup RAM Autonomous mode enable" "0: Backup RAM clock disabled when the CPU is in..,1: Backup RAM clock enabling is controlled by the.." newline bitfld.long 0x0 27. "DFSDM2AMEN,DFSDM2 Autonomous mode enable" "0: DFSDM2 clock disabled when the CPU is in CStop..,1: DFSDM2 peripheral clocks enabled when the.." bitfld.long 0x0 26. "DTSAMEN,Digital temperature sensor Autonomous mode enable" "0: DTS clocks disabled when the CPU is in CStop..,1: DTS clocks enabled when the SmartRun domain is.." newline bitfld.long 0x0 16. "RTCAMEN,RTC Autonomous mode enable" "0: RTC bus clocks disabled when the CPU is in CStop..,1: RTC bus clocks enabled when the SmartRun domain.." bitfld.long 0x0 15. "VREFAMEN,VREF Autonomous mode enable" "0: VREF clocks disabled when the CPU is in CStop..,1: VREF clocks enabled when the SmartRun domain is.." newline bitfld.long 0x0 14. "COMP12AMEN,COMP1 and 2 Autonomous mode enable" "0: COMP1 and 2 peripheral clocks disabled when the..,1: COMP1 and 2 peripheral clocks enabled when the.." bitfld.long 0x0 13. "DAC2AMEN,DAC2 (containing one converter) Autonomous mode enable" "0: DAC2 peripheral clocks disabled when the CPU is..,1: DAC2 peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 10. "LPTIM3AMEN,LPTIM3 Autonomous mode enable" "0: LPTIM3 peripheral clocks disabled when the CPU..,1: LPTIM3 peripheral clocks enabled when the.." bitfld.long 0x0 9. "LPTIM2AMEN,LPTIM2 Autonomous mode enable" "0: LPTIM2 peripheral clocks are disabled when the..,1: LPTIM2 peripheral clocks enabled when the.." newline bitfld.long 0x0 7. "I2C4AMEN,I2C4 Autonomous mode enable" "0: I2C4 peripheral clocks disabled when the CPU is..,1: I2C4 peripheral clocks enabled when the SmartRun.." bitfld.long 0x0 5. "SPI6AMEN,SPI6 Autonomous mode enable" "0: SPI6 peripheral clocks disabled when the CPU is..,1: SPI6 peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 3. "LPUART1AMEN,LPUART1 Autonomous mode enable" "0: LPUART1 peripheral clocks disabled when the CPU..,1: LPUART1 peripheral clocks enabled when the.." bitfld.long 0x0 1. "GPIOAMEN,GPIO Autonomous mode enable" "0: GPIO peripheral clocks disabled when the CPU is..,1: GPIO peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 0. "BDMA2AMEN,SmartRun domain DMA and DMAMUX Autonomous mode enable" "0: BDMA2 and DMAMUX2 peripheral clocks disabled..,1: BDMA2 and DMAMUX2 peripheral clocks enabled when.." group.long 0xB0++0x3 line.long 0x0 "RCC_CKGAENR,RCC AXI clocks gating enable register" bitfld.long 0x0 31. "JTAGCKG,JTAG automatic clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The clock is.." bitfld.long 0x0 30. "EXTICKG,EXTI clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The clock is.." newline bitfld.long 0x0 29. "ECCRAMCKG,RAM error code correction (ECC) clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The ECC clock is.." bitfld.long 0x0 17. "GFXMMUSCKG,AXI matrix slave GFXMMU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 16. "AXIRAM3CKG,AXI matrix slave SRAM3 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 15. "AXIRAM2CKG,AXI matrix slave SRAM2 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 14. "AXIRAM1CKG,AXI slave SRAM1 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 13. "OCTOSPI1CKG,AXI slave OCTOSPI1 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 12. "FMCCKG,AXI slave FMC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 11. "OCTOSPI2CKG,AXI slave OCTOSPI2 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 10. "FLIFTCKG,AXI slave Flash interface (FLIFT) clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 9. "AHB34CKG,AXI slave AHB34 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 8. "AHB12CKG,AXI slave AHB12 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 7. "GFXMMUMCKG,AXI master GFXMMU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 6. "LTDCCKG,AXI master LTDC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 5. "DMA2DCKG,AXI master DMA2D clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 4. "MDMACKG,AXI master MDMA clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 3. "SDMMCCKG,AXI master SDMMC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 2. "CPUCKG,AXI master CPU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 1. "AHBCKG,AXI master AHB clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 0. "AXICKG,AXI interconnect matrix clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI.." group.long 0x130++0x27 line.long 0x0 "RCC_RSR,RCC reset status register" rbitfld.long 0x0 30. "LPWRRSTF,reset due to illegal CD DStop or CD DStop2 or CPU CStop flag" "0: no illegal reset occurred (default after..,1: illegal CD DStop or CD DStop2 or CPU CStop reset.." rbitfld.long 0x0 28. "WWDGRSTF,window watchdog reset flag" "0: no window watchdog reset occurred from WWDG..,1: window watchdog reset occurred from WWDG" newline rbitfld.long 0x0 26. "IWDGRSTF,independent watchdog reset flag" "0: no independent watchdog reset occurred (default..,1: independent watchdog reset occurred" rbitfld.long 0x0 24. "SFTRSTF,system reset from CPU reset flag" "0: no CPU software reset occurred (default after..,1: a system reset has been generated by the CPU" newline rbitfld.long 0x0 23. "PORRSTF,POR/PDR reset flag" "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.." rbitfld.long 0x0 22. "PINRSTF,pin reset flag (NRST)" "0: no reset from pin occurred,1: reset from pin occurred (default after power-on.." newline rbitfld.long 0x0 21. "BORRSTF,BOR reset flag" "0: no BOR reset occurred,1: BOR reset occurred (default after power-on reset)" rbitfld.long 0x0 19. "CDRSTF,CPU domain power-switch reset flag" "0: no CPU domain power-switch reset occurred,1: CPU domain power-switch (ePOD2) reset occurred.." newline bitfld.long 0x0 16. "RMVF,remove reset flag" "0: reset of the reset flags not activated (default..,1: resets the value of the reset flags" line.long 0x4 "RCC_AHB3ENR," bitfld.long 0x4 24. "GFXMMUEN,GFXMMU clock enable" "0: GFXMMU clock disabled (default after reset),1: GFXMMU clock enabled" bitfld.long 0x4 23. "OTFD2EN,OTFD2 clock enable" "0: OTFD2 clock disabled (default after reset),1: OTFD2 clock enabled" newline bitfld.long 0x4 22. "OTFD1EN,OTFD1 clock enable" "0: OTFD1 clock disabled (default after reset),1: OTFD1 clock enabled" bitfld.long 0x4 21. "OCTOSPIMEN,OCTOSPIM clock enable" "0: OCTOSPIM clock disabled (default after reset),1: OCTOSPIM clock enabled" newline bitfld.long 0x4 19. "OCTOSPI2EN,OCTOSPI2 clock enable" "0: OCTOSPI2 and OCTOSPI2 delay clock disabled..,1: OCTOSPI2 OCTOSPI2 delay clock enabled" bitfld.long 0x4 16. "SDMMC1EN,SDMMC1 and SDMMC1 delay clock enable" "0: SDMMC1 and SDMMC1 delay clock disabled (default..,1: SDMMC1 and SDMMC1 delay clock enabled" newline bitfld.long 0x4 14. "OCTOSPI1EN,OCTOSPI1 and OCTOSPI1 delay clock enable" "0: OCTOSPI1 and OCTOSPI1 delay clock disabled..,1: OCTOSPI1 and OCTOSPI1 delay clock enabled" bitfld.long 0x4 12. "FMCEN,FMC peripheral clocks enable" "0: FMC peripheral clocks disabled (default after..,1: FMC peripheral clocks enabled" newline bitfld.long 0x4 5. "JPGDECEN,JPGDEC peripheral clock enable" "0: JPGDEC peripheral clock disabled (default after..,1: JPGDEC peripheral clock enabled" bitfld.long 0x4 4. "DMA2DEN,DMA2D peripheral clock enable" "0: DMA2D peripheral clock disabled (default after..,1: DMA2D peripheral clock enabled" newline bitfld.long 0x4 0. "MDMAEN,MDMA peripheral clock enable" "0: MDMA peripheral clock disabled (default after..,1: MDMA peripheral clock enabled" line.long 0x8 "RCC_AHB1ENR," bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 clocks enable" "0: USB1ULPI PHY clocks disabled (default after reset),1: USB1ULPI PHY clocks enabled" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG peripheral clocks enable" "0: USB1OTG peripheral clocks disabled (default..,1: USB1OTG peripheral clocks enabled" newline bitfld.long 0x8 9. "CRCEN,CRC peripheral clock enable" "0: CRC peripheral clock disabled (default after..,1: CRC peripheral clock enabled" bitfld.long 0x8 5. "ADC12EN,ADC1 and 2 peripheral clocks enable" "0: ADC1 and 2 peripheral clocks disabled (default..,1: ADC1 and 2 peripheral clocks enabled" newline bitfld.long 0x8 1. "DMA2EN,DMA2 clock enable" "0: DMA2 clock disabled (default after reset),1: DMA2 clock enabled" bitfld.long 0x8 0. "DMA1EN,DMA1 clock enable" "0: DMA1 clock disabled (default after reset),1: DMA1 clock enabled" line.long 0xC "RCC_AHB2ENR," bitfld.long 0xC 30. "AHBSRAM2EN,AHBSRAM2 block enable" "0: AHBSRAM2 interface clock is disabled. (default..,1: AHBSRAM2 interface clock is enabled." bitfld.long 0xC 29. "AHBSRAM1EN,AHBSRAM1 block enable" "0: AHBSRAM1 interface clock is disabled. (default..,1: AHBSRAM1 interface clock is enabled." newline bitfld.long 0xC 11. "BDMA1EN,DMA clock enable (DFSDM dedicated DMA)" "0: DMA clock disabled (default after reset),1: DMA clock enabled" bitfld.long 0xC 9. "SDMMC2EN,SDMMC2 and SDMMC2 delay clock enable" "0: SDMMC2 and SDMMC2 delay clock disabled (default..,1: SDMMC2 and SDMMC2 delay clock enabled" newline bitfld.long 0xC 6. "RNGEN,RNG peripheral clocks enable" "0: RNG peripheral clocks disabled (default after..,1: RNG peripheral clocks enabled:" bitfld.long 0xC 5. "HASHEN,HASH peripheral clock enable" "0: HASH peripheral clock disabled (default after..,1: HASH peripheral clock enabled" newline bitfld.long 0xC 4. "CRYPTEN,CRYPT peripheral clock enable" "0: CRYPT peripheral clock disabled (default after..,1: CRYPT peripheral clock enabled" bitfld.long 0xC 2. "HSEMEN,HSEM peripheral clock enable" "0: HSEM peripheral clock disabled (default after..,1: HSEM peripheral clock enabled" newline bitfld.long 0xC 0. "DCMI_PSSIEN,digital camera interface peripheral clock enable (DCMI or PSSI depending which IP is active)" "0: DCMI/PSSI peripheral clock disabled (default..,1: DCMI/PSSI peripheral clock enabled" line.long 0x10 "RCC_AHB4ENR," bitfld.long 0x10 29. "SRDSRAMEN,SmartRun domain SRAM clock enable" "0: SRDSRAM clock disabled (default after reset),1: SRDSRAM clock enabled" bitfld.long 0x10 28. "BKPRAMEN,Backup RAM clock enable" "0: Backup RAM clock disabled (default after reset),1: Backup RAM clock enabled" newline bitfld.long 0x10 21. "BDMA2EN,SmartRun domain DMA and DMAMUX clock enable" "0: BDMA2 and DMAMUX2 clock disabled (default after..,1: BDMA2 and DMAMUX2 clock enabled" bitfld.long 0x10 10. "GPIOKEN,GPIOK peripheral clock enable" "0: GPIOK peripheral clock disabled (default after..,1: GPIOK peripheral clock enabled" newline bitfld.long 0x10 9. "GPIOJEN,GPIOJ peripheral clock enable" "0: GPIOJ peripheral clock disabled (default after..,1: GPIOJ peripheral clock enabled" bitfld.long 0x10 8. "GPIOIEN,GPIOI peripheral clock enable" "0: GPIOI peripheral clock disabled (default after..,1: GPIOI peripheral clock enabled" newline bitfld.long 0x10 7. "GPIOHEN,GPIOH peripheral clock enable" "0: GPIOH peripheral clock disabled (default after..,1: GPIOH peripheral clock enabled" bitfld.long 0x10 6. "GPIOGEN,GPIOG peripheral clock enable" "0: GPIOG peripheral clock disabled (default after..,1: GPIOG peripheral clock enabled" newline bitfld.long 0x10 5. "GPIOFEN,GPIOF peripheral clock enable" "0: GPIOF peripheral clock disabled (default after..,1: GPIOF peripheral clock enabled" bitfld.long 0x10 4. "GPIOEEN,GPIOE peripheral clock enable" "0: GPIOE peripheral clock disabled (default after..,1: GPIOE peripheral clock enabled" newline bitfld.long 0x10 3. "GPIODEN,GPIOD peripheral clock enable" "0: GPIOD peripheral clock disabled (default after..,1: GPIOD peripheral clock enabled" bitfld.long 0x10 2. "GPIOCEN,GPIOC peripheral clock enable" "0: GPIOC peripheral clock disabled (default after..,1: GPIOC peripheral clock enabled" newline bitfld.long 0x10 1. "GPIOBEN,GPIOB peripheral clock enable" "0: GPIOB peripheral clock disabled (default after..,1: GPIOB peripheral clock enabled" bitfld.long 0x10 0. "GPIOAEN,GPIOA peripheral clock enable" "0: GPIOA peripheral clock disabled (default after..,1: GPIOA peripheral clock enabled" line.long 0x14 "RCC_APB3ENR," bitfld.long 0x14 6. "WWDGEN,WWDG clock enable" "0: WWDG peripheral clock disable (default after..,1: WWDG peripheral clock enabled" bitfld.long 0x14 3. "LTDCEN,LTDC clock enable" "0: LTDC peripheral clock disabled (default after..,1: LTDC peripheral clock provided to the LTDC block" line.long 0x18 "RCC_APB1LENR," bitfld.long 0x18 31. "UART8EN,UART8 peripheral clocks enable" "0: UART8 peripheral clocks disabled (default after..,1: UART8 peripheral clocks enabled" bitfld.long 0x18 30. "UART7EN,UART7 peripheral clocks enable" "0: UART7 peripheral clocks disabled (default after..,1: UART7 peripheral clocks enabled" newline bitfld.long 0x18 29. "DAC1EN,DAC1 (containing two converters) peripheral clock enable" "0: DAC1 peripheral clock disabled (default after..,1: DAC1 peripheral clock enabled" bitfld.long 0x18 27. "CECEN,HDMI-CEC peripheral clock enable" "0: HDMI-CEC peripheral clock disabled (default..,1: HDMI-CEC peripheral clock enabled" newline bitfld.long 0x18 23. "I2C3EN,I2C3 peripheral clocks enable" "0: I2C3 peripheral clocks disabled (default after..,1: I2C3 peripheral clocks enabled" bitfld.long 0x18 22. "I2C2EN,I2C2 peripheral clocks enable" "0: I2C2 peripheral clocks disabled (default after..,1: I2C2 peripheral clocks enabled" newline bitfld.long 0x18 21. "I2C1EN,I2C1 peripheral clocks enable" "0: I2C1 peripheral clocks disabled (default after..,1: I2C1 peripheral clocks enabled" bitfld.long 0x18 20. "UART5EN,UART5 peripheral clocks enable" "0: UART5 peripheral clocks disabled (default after..,1: UART5 peripheral clocks enabled" newline bitfld.long 0x18 19. "UART4EN,UART4 peripheral clocks enable" "0: UART4 peripheral clocks disabled (default after..,1: UART4 peripheral clocks enabled" bitfld.long 0x18 18. "USART3EN,USART3 peripheral clocks enable" "0: USART3 peripheral clocks disabled (default after..,1: USART3 peripheral clocks enabled" newline bitfld.long 0x18 17. "USART2EN,USART2peripheral clocks enable" "0: USART2 peripheral clocks disabled (default after..,1: USART2 peripheral clocks enabled" bitfld.long 0x18 16. "SPDIFRXEN,SPDIFRX peripheral clocks enable" "0: SPDIFRX peripheral clocks disabled (default..,1: SPDIFRX peripheral clocks enabled" newline bitfld.long 0x18 15. "SPI3EN,SPI3 peripheral clocks enable" "0: SPI3 peripheral clocks disabled (default after..,1: SPI3 peripheral clocks enabled" bitfld.long 0x18 14. "SPI2EN,SPI2 peripheral clocks enable" "0: SPI2 peripheral clocks disabled (default after..,1: SPI2 peripheral clocks enabled" newline bitfld.long 0x18 9. "LPTIM1EN,LPTIM1 peripheral clocks enable" "0: LPTIM1 peripheral clocks disabled (default after..,1: LPTIM1 peripheral clocks enabled" bitfld.long 0x18 8. "TIM14EN,TIM14 peripheral clock enable" "0: TIM14 peripheral clock disabled (default after..,1: TIM14 peripheral clock enabled" newline bitfld.long 0x18 7. "TIM13EN,TIM13 peripheral clock enable" "0: TIM13 peripheral clock disabled (default after..,1: TIM13 peripheral clock enabled" bitfld.long 0x18 6. "TIM12EN,TIM12 peripheral clock enable" "0: TIM12 peripheral clock disabled (default after..,1: TIM12 peripheral clock enabled" newline bitfld.long 0x18 5. "TIM7EN,TIM7 peripheral clock enable" "0: TIM7 peripheral clock disabled (default after..,1: TIM7 peripheral clock enabled" bitfld.long 0x18 4. "TIM6EN,TIM6 peripheral clock enable" "0: TIM6 peripheral clock disabled (default after..,1: TIM6 peripheral clock enabled" newline bitfld.long 0x18 3. "TIM5EN,TIM5 peripheral clock enable" "0: TIM5 peripheral clock disabled (default after..,1: TIM5 peripheral clock enabled" bitfld.long 0x18 2. "TIM4EN,TIM4 peripheral clock enable" "0: TIM4 peripheral clock disable (default after..,1: TIM4 peripheral clock enabled" newline bitfld.long 0x18 1. "TIM3EN,TIM3 peripheral clock enable" "0: TIM3 peripheral clock disabled (default after..,1: TIM3 peripheral clock enabled" bitfld.long 0x18 0. "TIM2EN,TIM2 peripheral clock enable" "0: TIM2 peripheral clock disabled (default after..,1: TIM2 peripheral clock enabled" line.long 0x1C "RCC_APB1HENR," bitfld.long 0x1C 8. "FDCANEN,FDCAN peripheral clocks enable" "0: FDCAN peripheral clocks disabled (default after..,1: FDCAN peripheral clocks enabled:" bitfld.long 0x1C 5. "MDIOSEN,MDIOS peripheral clock enable" "0: MDIOS peripheral clock disabled (default after..,1: MDIOS peripheral clock enabled" newline bitfld.long 0x1C 4. "OPAMPEN,OPAMP peripheral clock enable" "0: OPAMP peripheral clock disabled (default after..,1: OPAMP peripheral clock enabled" bitfld.long 0x1C 2. "SWPMIEN,SWPMI peripheral clocks enable" "0: SWPMI peripheral clocks disabled (default after..,1: SWPMI peripheral clocks enabled:" newline bitfld.long 0x1C 1. "CRSEN,clock recovery system peripheral clock enable" "0: CRS peripheral clock disabled (default after..,1: CRS peripheral clock enabled" line.long 0x20 "RCC_APB2ENR," bitfld.long 0x20 30. "DFSDM1EN,DFSDM1 peripheral clocks enable" "0: DFSDM1 peripheral clocks disabled (default after..,1: DFSDM1 peripheral clocks enabled" bitfld.long 0x20 23. "SAI2EN,SAI2 peripheral clocks enable" "0: SAI2 peripheral clocks disabled (default after..,1: SAI2 peripheral clocks enabled" newline bitfld.long 0x20 22. "SAI1EN,SAI1 peripheral clocks enable" "0: SAI1 peripheral clocks disabled (default after..,1: SAI1 peripheral clocks enabled:" bitfld.long 0x20 20. "SPI5EN,SPI5 peripheral clocks enable" "0: SPI5 peripheral clocks disabled (default after..,1: SPI5 peripheral clocks enabled:" newline bitfld.long 0x20 18. "TIM17EN,TIM17 peripheral clock enable" "0: TIM17 peripheral clock disabled (default after..,1: TIM17 peripheral clock enabled" bitfld.long 0x20 17. "TIM16EN,TIM16 peripheral clock enable" "0: TIM16 peripheral clock disabled (default after..,1: TIM16 peripheral clock enabled" newline bitfld.long 0x20 16. "TIM15EN,TIM15 peripheral clock enable" "0: TIM15 peripheral clock disabled (default after..,1: TIM15 peripheral clock enabled" bitfld.long 0x20 13. "SPI4EN,SPI4 Peripheral Clocks Enable" "0: SPI4 peripheral clocks disabled (default after..,1: SPI4 peripheral clocks enabled:" newline bitfld.long 0x20 12. "SPI1EN,SPI1 Peripheral Clocks Enable" "0: SPI1 peripheral clocks disabled (default after..,1: SPI1 peripheral clocks enabled:" bitfld.long 0x20 7. "USART10EN,USART10 peripheral clocks enable" "0: USART10 peripheral clocks disabled (default..,1: USART10 peripheral clocks enabled:" newline bitfld.long 0x20 6. "UART9EN,UART9 peripheral clocks enable" "0: UART9 peripheral clocks disabled (default after..,1: UART9 peripheral clocks enabled:" bitfld.long 0x20 5. "USART6EN,USART6 peripheral clocks enable" "0: USART6 peripheral clocks disabled (default after..,1: USART6 peripheral clocks enabled:" newline bitfld.long 0x20 4. "USART1EN,USART1 peripheral clocks enable" "0: USART1 peripheral clocks disabled (default after..,1: USART1 peripheral clocks enabled:" bitfld.long 0x20 1. "TIM8EN,TIM8 peripheral clock enable" "0: TIM8 peripheral clock disabled (default after..,1: TIM8 peripheral clock enabled" newline bitfld.long 0x20 0. "TIM1EN,TIM1 peripheral clock enable" "0: TIM1 peripheral clock disabled (default after..,1: TIM1 peripheral clock enabled" line.long 0x24 "RCC_APB4ENR," bitfld.long 0x24 27. "DFSDM2EN,DFSDM2peripheral clock enable" "0: DFSDM2peripheral peripheral clock disabled..,1: DFSDM2peripheral peripheral clock enabled" bitfld.long 0x24 26. "DTSEN,Digital temperature sensor peripheral clock enable" "0: DTS peripheral clock disabled (default after..,1: DTS peripheral clock enabled" newline bitfld.long 0x24 16. "RTCAPBEN,RTC APB clock enable" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.." bitfld.long 0x24 15. "VREFEN,VREF peripheral clock enable" "0: VREF peripheral clock disabled (default after..,1: VREF peripheral clock enabled" newline bitfld.long 0x24 14. "COMP12EN,COMP1 and 2 peripheral clock enable" "0: COMP1 and 2 peripheral clock disabled (default..,1: COMP1 and 2 peripheral clock enabled" bitfld.long 0x24 13. "DAC2EN,DAC2 (containing one converter) peripheral clock enable" "0: DAC2 peripheral clock disabled (default after..,1: DAC2 peripheral clock enabled" newline bitfld.long 0x24 10. "LPTIM3EN,LPTIM3 peripheral clocks enable" "0: LPTIM3 peripheral clocks disabled (default after..,1: LPTIM3 peripheral clocks enabled" bitfld.long 0x24 9. "LPTIM2EN,LPTIM2 peripheral clocks enable" "0: LPTIM2 peripheral clocks disabled (default after..,1: LPTIM2 peripheral clocks enabled" newline bitfld.long 0x24 7. "I2C4EN,I2C4 peripheral clocks enable" "0: I2C4 peripheral clocks disabled (default after..,1: I2C4 peripheral clocks enabled" bitfld.long 0x24 5. "SPI6EN,SPI6 peripheral clocks enable" "0: SPI6 peripheral clocks disabled (default after..,1: SPI6 peripheral clocks enabled" newline bitfld.long 0x24 3. "LPUART1EN,LPUART1 peripheral clocks enable" "0: LPUART1 peripheral clocks disabled (default..,1: LPUART1 peripheral clocks enabled" bitfld.long 0x24 1. "SYSCFGEN,SYSCFG peripheral clock enable" "0: SYSCFG peripheral clock disabled (default after..,1: SYSCFG peripheral clock enabled" group.long 0x15C++0x23 line.long 0x0 "RCC_AHB3LPENR," bitfld.long 0x0 31. "AXISRAM1LPEN,AXISRAM1 block clock enable during CSleep mode" "0: AXISRAM1 interface clock disabled during CSleep..,1: AXISRAM1 interface clock enabled during CSleep.." bitfld.long 0x0 30. "ITCMLPEN,ITCM block clock enable during CSleep mode" "0: ITCM interface clock disabled during CSleep mode,1: ITCM interface clock enabled during CSleep mode.." newline bitfld.long 0x0 29. "DTCM2LPEN,DTCM2 block clock enable during CSleep mode" "0: DTCM2 interface clock disabled during CSleep mode,1: DTCM2 interface clock enabled during CSleep mode.." bitfld.long 0x0 28. "DTCM1LPEN,DTCM1 block clock enable during CSleep mode" "0: DTCM1 interface clock disabled during CSleep mode,1: DTCM1 interface clock enabled during CSleep mode.." newline bitfld.long 0x0 27. "AXISRAM3LPEN,AXISRAM3 block clock enable during CSleep mode" "0: AXISRAM3 interface clock disabled during CSleep..,1: AXISRAM3 interface clock enabled during CSleep.." bitfld.long 0x0 26. "AXISRAM2LPEN,AXISRAM2 block clock enable during CSleep mode" "0: AXISRAM2 interface clock disabled during CSleep..,1: AXISRAM2 interface clock enabled during CSleep.." newline bitfld.long 0x0 24. "GFXMMULPEN,GFXMMU block clock enable during CSleep mode" "0: GFXMMU interface clock disabled during CSleep mode,1: GFXMMU interface clock enabled during CSleep.." bitfld.long 0x0 23. "OTFD2LPEN,OTFD2 block clock enable during CSleep mode" "0: OTFD2 interface clock disabled during CSleep mode,1: OTFD2 interface clock enabled during CSleep mode.." newline bitfld.long 0x0 22. "OTFD1LPEN,OTFD1 block clock enable during CSleep mode" "0: OTFD1 interface clock disabled during CSleep mode,1: OTFD1 interface clock enabled during CSleep mode.." bitfld.long 0x0 21. "OCTOSPIMLPEN,OCTOSPIM block clock enable during CSleep mode" "0: OCTOSPIM interface clock disabled during CSleep..,1: OCTOSPIM interface clock enabled during CSleep.." newline bitfld.long 0x0 19. "OCTOSPI2LPEN,OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode" "0: OCTOSPI2 and OCTOSPI2 delay clock disabled..,1: OCTOSPI2 and OCTOSPI2 delay clock enabled during.." bitfld.long 0x0 16. "SDMMC1LPEN,SDMMC1 and SDMMC1 delay clock enable during CSleep mode" "0: SDMMC1 and SDMMC1 delay clock disabled during..,1: SDMMC1 and SDMMC1 delay clock enabled during.." newline bitfld.long 0x0 14. "OCTOSPI1LPEN,OCTOSPI1 and OCTOSPI1 delay clock enable during CSleep mode" "0: OCTOSPI1 and OCTOSPI1 delay clock disabled..,1: OCTOSPI1 and OCTOSPI1 delay clock enabled during.." bitfld.long 0x0 12. "FMCLPEN,FMC peripheral clocks enable during CSleep mode" "0: FMC peripheral clocks disabled during CSleep mode,1: FMC peripheral clocks enabled during CSleep mode.." newline bitfld.long 0x0 8. "FLITFLPEN,FLITF clock enable during CSleep mode" "0: FLITF clock disabled during CSleep mode,1: FLITF clock enabled during CSleep mode (default.." bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC clock enable during CSleep mode" "0: JPGDEC peripheral clock disabled during CSleep..,1: JPGDEC peripheral clock enabled during CSleep.." newline bitfld.long 0x0 4. "DMA2DLPEN,DMA2D clock enable during CSleep mode" "0: DMA2D peripheral clock disabled during CSleep mode,1: DMA2D peripheral clock enabled during CSleep.." bitfld.long 0x0 0. "MDMALPEN,MDMA clock enable during CSleep mode" "0: MDMA peripheral clock disabled during CSleep mode,1: MDMA peripheral clock enabled during CSleep mode.." line.long 0x4 "RCC_AHB1LPENR," bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep mode" "0: USB_PHY1 peripheral clock disabled during CSleep..,1: USB_PHY1 peripheral clock enabled during CSleep.." bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during CSleep mode" "0: USB1OTG peripheral clock disabled during CSleep..,1: USB1OTG peripheral clock enabled during CSleep.." newline bitfld.long 0x4 9. "CRCLPEN,CRC peripheral clock enable during CSleep mode" "0: CRC peripheral clock disabled during CSleep mode,1: CRC peripheral clock enabled during CSleep mode.." bitfld.long 0x4 5. "ADC12LPEN,ADC1 and 2 peripheral clocks enable during CSleep mode" "0: ADC1 and 2 peripheral clocks disabled during..,1: ADC1 and 2 peripheral clocks enabled during.." newline bitfld.long 0x4 1. "DMA2LPEN,DMA2 clock enable during CSleep mode" "0: DMA2 clock disabled during CSleep mode,1: DMA2 clock enabled during CSleep mode (default.." bitfld.long 0x4 0. "DMA1LPEN,DMA1 clock enable during CSleep mode" "0: DMA1 clock disabled during CSleep mode,1: DMA1 clock enabled during CSleep mode (default.." line.long 0x8 "RCC_AHB2LPENR," bitfld.long 0x8 30. "AHBSRAM2LPEN,AHBSRAM2 clock enable during CSleep mode" "0: AHBSRAM2 clock disabled during CSleep mode,1: AHBSRAM2 clock enabled during CSleep mode.." bitfld.long 0x8 29. "AHBSRAM1LPEN,AHBSRAM1 clock enable during CSleep mode" "0: AHBSRAM1 clock disabled during CSleep mode,1: AHBSRAM1 clock enabled during CSleep mode.." newline bitfld.long 0x8 11. "DFSDMDMALPEN,DFSDMDMA clock enable during CSleep mode" "0: DFSDMDMA clock disabled during CSleep mode,1: DFSDMDMA clock enabled during CSleep mode.." bitfld.long 0x8 9. "SDMMC2LPEN,SDMMC2 and SDMMC2 delay clock enable during CSleep mode" "0: SDMMC2 and SDMMC2 delay clock disabled during..,1: SDMMC2 and SDMMC2 delay clock enabled during.." newline bitfld.long 0x8 6. "RNGLPEN,RNG peripheral clock enable during CSleep mode" "0: RNG peripheral clocks disabled during CSleep mode,1: RNG peripheral clock enabled during CSleep mode.." bitfld.long 0x8 5. "HASHLPEN,HASH peripheral clock enable during CSleep mode" "0: HASH peripheral clock disabled during CSleep mode,1: HASH peripheral clock enabled during CSleep mode.." newline bitfld.long 0x8 4. "CRYPTLPEN,CRYPT peripheral clock enable during CSleep mode" "0: CRYPT peripheral clock disabled during CSleep mode,1: CRYPT peripheral clock enabled during CSleep.." bitfld.long 0x8 0. "DCMI_PSSILPEN,digital camera interface peripheral clock enable during CSleep mode (DCMI or PSSI depending which IP is active)" "0: DCMI/PSSI peripheral clock disabled during..,1: DCMI/PSSI peripheral clock enabled during CSleep.." line.long 0xC "RCC_AHB4LPENR," bitfld.long 0xC 29. "SRDSRAMLPEN,SmartRun domain SRAM clock enable during CSleep mode" "0: SRDSRAM clock disabled during CSleep mode,1: SRDSRAM clock enabled during CSleep mode.." bitfld.long 0xC 28. "BKPRAMLPEN,Backup RAM clock enable during CSleep mode" "0: Backup RAM clock disabled during CSleep mode,1: Backup RAM clock enabled during CSleep mode.." newline bitfld.long 0xC 21. "BDMA2LPEN,SmartRun domain DMA and DMAMUX clock enable during CSleep mode" "0: BDMA2 and DMAMUX2 clock disabled during CSleep..,1: BDMA2 and DMAMUX2 clock enabled during CSleep.." bitfld.long 0xC 10. "GPIOKLPEN,GPIOK peripheral clock enable during CSleep mode" "0: GPIOK peripheral clock disabled during CSleep mode,1: GPIOK peripheral clock enabled during CSleep.." newline bitfld.long 0xC 9. "GPIOJLPEN,GPIOJ peripheral clock enable during CSleep mode" "0: GPIOJ peripheral clock disabled during CSleep mode,1: GPIOJ peripheral clock enabled during CSleep.." bitfld.long 0xC 8. "GPIOILPEN,GPIOI peripheral clock enable during CSleep mode" "0: GPIOI peripheral clock disabled during CSleep mode,1: GPIOI peripheral clock enabled during CSleep.." newline bitfld.long 0xC 7. "GPIOHLPEN,GPIOH peripheral clock enable during CSleep mode" "0: GPIOH peripheral clock disabled during CSleep mode,1: GPIOH peripheral clock enabled during CSleep.." bitfld.long 0xC 6. "GPIOGLPEN,GPIOG peripheral clock enable during CSleep mode" "0: GPIOG peripheral clock disabled during CSleep mode,1: GPIOG peripheral clock enabled during CSleep.." newline bitfld.long 0xC 5. "GPIOFLPEN,GPIOF peripheral clock enable during CSleep mode" "0: GPIOF peripheral clock disabled during CSleep mode,1: GPIOF peripheral clock enabled during CSleep.." bitfld.long 0xC 4. "GPIOELPEN,GPIOE peripheral clock enable during CSleep mode" "0: GPIOE peripheral clock disabled during CSleep mode,1: GPIOE peripheral clock enabled during CSleep.." newline bitfld.long 0xC 3. "GPIODLPEN,GPIOD peripheral clock enable during CSleep mode" "0: GPIOD peripheral clock disabled during CSleep mode,1: GPIOD peripheral clock enabled during CSleep.." bitfld.long 0xC 2. "GPIOCLPEN,GPIOC peripheral clock enable during CSleep mode" "0: GPIOC peripheral clock disabled during CSleep mode,1: GPIOC peripheral clock enabled during CSleep.." newline bitfld.long 0xC 1. "GPIOBLPEN,GPIOB peripheral clock enable during CSleep mode" "0: GPIOB peripheral clock disabled during CSleep mode,1: GPIOB peripheral clock enabled during CSleep.." bitfld.long 0xC 0. "GPIOALPEN,GPIOA peripheral clock enable during CSleep mode" "0: GPIOA peripheral clock disabled during CSleep mode,1: GPIOA peripheral clock enabled during CSleep.." line.long 0x10 "RCC_APB3LPENR," bitfld.long 0x10 6. "WWDGLPEN,WWDG clock enable during CSleep mode" "0: WWDG clock disable during CSleep mode,1: WWDG clock enabled during CSleep mode (default.." bitfld.long 0x10 3. "LTDCLPEN,LTDC peripheral clock enable during CSleep mode" "0: LTDC clock disabled during CSleep mode,1: LTDC clock provided to the LTDC during CSleep.." line.long 0x14 "RCC_APB1LLPENR," bitfld.long 0x14 31. "UART8LPEN,UART8 peripheral clocks enable during CSleep mode" "0: UART8 peripheral clocks disabled during CSleep..,1: UART8 peripheral clocks enabled during CSleep.." bitfld.long 0x14 30. "UART7LPEN,UART7 peripheral clocks enable during CSleep mode" "0: UART7 peripheral clocks disabled during CSleep..,1: UART7 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 29. "DAC1LPEN,DAC1 (containing two converters) peripheral clock enable during CSleep mode" "0: DAC1 peripheral clock disabled during CSleep mode,1: DAC1 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 27. "CECLPEN,HDMI-CEC peripheral clocks enable during CSleep mode" "0: HDMI-CEC peripheral clocks disabled during..,1: HDMI-CEC peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 23. "I2C3LPEN,I2C3 peripheral clocks enable during CSleep mode" "0: I2C3 peripheral clocks disabled during CSleep mode,1: I2C3 peripheral clocks enabled during CSleep.." bitfld.long 0x14 22. "I2C2LPEN,I2C2 peripheral clocks enable during CSleep mode" "0: I2C2 peripheral clocks disabled during CSleep mode,1: I2C2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 21. "I2C1LPEN,I2C1 peripheral clocks enable during CSleep mode" "0: I2C1 peripheral clocks disabled during CSleep mode,1: I2C1 peripheral clocks enabled during CSleep.." bitfld.long 0x14 20. "UART5LPEN,UART5 peripheral clocks enable during CSleep mode" "0: UART5 peripheral clocks disabled during CSleep..,1: UART5 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 19. "UART4LPEN,UART4 peripheral clocks enable during CSleep mode" "0: UART4 peripheral clocks disabled during CSleep..,1: UART4 peripheral clocks enabled during CSleep.." bitfld.long 0x14 18. "USART3LPEN,USART3 peripheral clocks enable during CSleep mode" "0: USART3 peripheral clocks disabled during CSleep..,1: USART3 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 17. "USART2LPEN,USART2 peripheral clocks enable during CSleep mode" "0: USART2 peripheral clocks disabled during CSleep..,1: USART2 peripheral clocks enabled during CSleep.." bitfld.long 0x14 16. "SPDIFRXLPEN,SPDIFRX peripheral clocks enable during CSleep mode" "0: SPDIFRX peripheral clocks disabled during CSleep..,1: SPDIFRX peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 15. "SPI3LPEN,SPI3 peripheral clocks enable during CSleep mode" "0: SPI3 peripheral clocks disabled during CSleep mode,1: SPI3 peripheral clocks enabled during CSleep.." bitfld.long 0x14 14. "SPI2LPEN,SPI2 peripheral clocks enable during CSleep mode" "0: SPI2 peripheral clocks disabled during CSleep mode,1: SPI2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 9. "LPTIM1LPEN,LPTIM1 peripheral clocks enable during CSleep mode" "0: LPTIM1 peripheral clocks disabled during CSleep..,1: LPTIM1 peripheral clocks enabled during CSleep.." bitfld.long 0x14 8. "TIM14LPEN,TIM14 peripheral clock enable during CSleep mode" "0: TIM14 peripheral clock disabled during CSleep mode,1: TIM14 peripheral clock enabled during CSleep.." newline bitfld.long 0x14 7. "TIM13LPEN,TIM13 peripheral clock enable during CSleep mode" "0: TIM13 peripheral clock disabled during CSleep mode,1: TIM13 peripheral clock enabled during CSleep.." bitfld.long 0x14 6. "TIM12LPEN,TIM12 peripheral clock enable during CSleep mode" "0: TIM12 peripheral clock disabled during CSleep mode,1: TIM12 peripheral clock enabled during CSleep.." newline bitfld.long 0x14 5. "TIM7LPEN,TIM7 peripheral clock enable during CSleep mode" "0: TIM7 peripheral clock disabled during CSleep mode,1: TIM7 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 4. "TIM6LPEN,TIM6 peripheral clock enable during CSleep mode" "0: TIM6 peripheral clock disabled during CSleep mode,1: TIM6 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x14 3. "TIM5LPEN,TIM5 peripheral clock enable during CSleep mode" "0: TIM5 peripheral clock disabled during CSleep mode,1: TIM5 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 2. "TIM4LPEN,TIM4 peripheral clock enable during CSleep mode" "0: TIM4 peripheral clock disabled during CSleep mode,1: TIM4 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x14 1. "TIM3LPEN,TIM3 peripheral clock enable during CSleep mode" "0: TIM3 peripheral clock disabled during CSleep mode,1: TIM3 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 0. "TIM2LPEN,TIM2 peripheral clock enable during CSleep mode" "0: TIM2 peripheral clock disabled during CSleep mode,1: TIM2 peripheral clock enabled during CSleep mode.." line.long 0x18 "RCC_APB1HLPENR," bitfld.long 0x18 8. "FDCANLPEN,FDCAN peripheral clocks enable during CSleep mode" "0: FDCAN peripheral clocks disabled during CSleep..,1: FDCAN peripheral clocks enabled during CSleep.." bitfld.long 0x18 5. "MDIOSLPEN,MDIOS peripheral clock enable during CSleep mode" "0: MDIOS peripheral clock disabled during CSleep mode,1: MDIOS peripheral clock enabled during CSleep.." newline bitfld.long 0x18 4. "OPAMPLPEN,OPAMP peripheral clock enable during CSleep mode" "0: OPAMP peripheral clock disabled during CSleep mode,1: OPAMP peripheral clock enabled during CSleep.." bitfld.long 0x18 2. "SWPMILPEN,SWPMI peripheral clocks enable during CSleep mode" "0: SWPMI peripheral clocks disabled during CSleep..,1: SWPMI peripheral clocks enabled during CSleep.." newline bitfld.long 0x18 1. "CRSLPEN,clock recovery system peripheral clock enable during CSleep mode" "0: CRS peripheral clock disabled during CSleep mode,1: CRS peripheral clock enabled during CSleep mode.." line.long 0x1C "RCC_APB2LPENR," bitfld.long 0x1C 30. "DFSDM1LPEN,DFSDM1 peripheral clocks enable during CSleep mode" "0: DFSDM1 peripheral clocks disabled during CSleep..,1: DFSDM1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 23. "SAI2LPEN,SAI2 peripheral clocks enable during CSleep mode" "0: SAI2 peripheral clocks disabled during CSleep mode,1: SAI2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 22. "SAI1LPEN,SAI1 peripheral clocks enable during CSleep mode" "0: SAI1 peripheral clocks disabled during CSleep mode,1: SAI1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 20. "SPI5LPEN,SPI5 peripheral clocks enable during CSleep mode" "0: SPI5 peripheral clocks disabled during CSleep mode,1: SPI5 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 18. "TIM17LPEN,TIM17 peripheral clock enable during CSleep mode" "0: TIM17 peripheral clock disabled during CSleep mode,1: TIM17 peripheral clock enabled during CSleep.." bitfld.long 0x1C 17. "TIM16LPEN,TIM16 peripheral clock enable during CSleep mode" "0: TIM16 peripheral clock disabled during CSleep mode,1: TIM16 peripheral clock enabled during CSleep.." newline bitfld.long 0x1C 16. "TIM15LPEN,TIM15 peripheral clock enable during CSleep mode" "0: TIM15 peripheral clock disabled during CSleep mode,1: TIM15 peripheral clock enabled during CSleep.." bitfld.long 0x1C 13. "SPI4LPEN,SPI4 peripheral clock enable during CSleep mode" "0: SPI4 peripheral clocks disabled during CSleep mode,1: SPI4 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 12. "SPI1LPEN,SPI1 peripheral clock enable during CSleep mode" "0: SPI1 peripheral clocks disabled during CSleep mode,1: SPI1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 7. "USART10LPEN,USART10 peripheral clock enable during CSleep mode" "0: USART10 peripheral clocks disabled during CSleep..,1: USART10 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 6. "UART9LPEN,UART9 peripheral clock enable during CSleep mode" "0: UART9 peripheral clocks disabled during CSleep..,1: UART9 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 5. "USART6LPEN,USART6 peripheral clock enable during CSleep mode" "0: USART6 peripheral clocks disabled during CSleep..,1: USART6 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 4. "USART1LPEN,USART1 peripheral clock enable during CSleep mode" "0: USART1 peripheral clocks disabled during CSleep..,1: USART1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 1. "TIM8LPEN,TIM8 peripheral clock enable during CSleep mode" "0: TIM8 peripheral clock disabled during CSleep mode,1: TIM8 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x1C 0. "TIM1LPEN,TIM1 peripheral clock enable during CSleep mode" "0: TIM1 peripheral clock disabled during CSleep mode,1: TIM1 peripheral clock enabled during CSleep mode.." line.long 0x20 "RCC_APB4LPENR," bitfld.long 0x20 27. "DFSDM2LPEN,DFSDM2 peripheral clock enable during CSleep mode" "0: DFSDM2 peripheral clock disabled during CSleep..,1: DFSDM2 peripheral clock enabled during CSleep.." bitfld.long 0x20 26. "DTSLPEN,temperature sensor peripheral clock enable during CSleep mode" "0: DTS peripheral clock disabled during CSleep mode,1: DTS peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 16. "RTCAPBLPEN,RTC APB clock enable during CSleep mode" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.." bitfld.long 0x20 15. "VREFLPEN,VREF peripheral clock enable during CSleep mode" "0: VREF peripheral clock disabled during CSleep mode,1: VREF peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 14. "COMP12LPEN,COMP1 and 2 peripheral clock enable during CSleep mode" "0: COMP1 and 2 peripheral clock disabled during..,1: COMP1 and 2 peripheral clock enabled during.." bitfld.long 0x20 13. "DAC2LPEN,DAC2 (containing one converter) peripheral clock enable during CSleep mode" "0: DAC2 peripheral clock disabled during CSleep mode,1: DAC2 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 10. "LPTIM3LPEN,LPTIM3 peripheral clocks enable during CSleep mode" "0: LPTIM3 peripheral clocks disabled during CSleep..,1: LPTIM3 peripheral clocks enabled during CSleep.." bitfld.long 0x20 9. "LPTIM2LPEN,LPTIM2 peripheral clocks enable during CSleep mode" "0: LPTIM2 peripheral clocks disabled during CSleep..,1: LPTIM2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x20 7. "I2C4LPEN,I2C4 peripheral clocks enable during CSleep mode" "0: I2C4 peripheral clocks disabled during CSleep mode,1: I2C4 peripheral clocks enabled during CSleep.." bitfld.long 0x20 5. "SPI6LPEN,SPI6 peripheral clocks enable during CSleep mode" "0: SPI6 peripheral clocks disabled during CSleep mode,1: SPI6 peripheral clocks enabled during CSleep.." newline bitfld.long 0x20 3. "LPUART1LPEN,LPUART1 peripheral clocks enable during CSleep mode" "0: LPUART1 peripheral clocks disabled during CSleep..,1: LPUART1 peripheral clocks enabled during CSleep.." bitfld.long 0x20 1. "SYSCFGLPEN,SYSCFG peripheral clock enable during CSleep mode" "0: SYSCFG peripheral clock disabled during CSleep..,1: SYSCFG peripheral clock enabled during CSleep.." endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x7 line.long 0x0 "RCC_CR," rbitfld.long 0x0 29. "PLL3RDY,PLL3 clock ready flag" "0: PLL3 unlocked (default after reset),1: PLL3 locked" bitfld.long 0x0 28. "PLL3ON,PLL3 enable" "0: PLL3 OFF (default after reset),1: PLL3 ON" newline rbitfld.long 0x0 27. "PLL2RDY,PLL2 clock ready flag" "0: PLL2 unlocked (default after reset),1: PLL2 locked" bitfld.long 0x0 26. "PLL2ON,PLL2 enable" "0: PLL2 OFF (default after reset),1: PLL2 ON" newline rbitfld.long 0x0 25. "PLL1RDY,PLL1 clock ready flag" "0: PLL1 unlocked (default after reset),1: PLL1 locked" bitfld.long 0x0 24. "PLL1ON,PLL1 enable" "0: PLL1 OFF (default after reset),1: PLL1 ON" newline bitfld.long 0x0 20. "HSEEXT,external high speed clock type in Bypass mode" "0: HSE in analog mode (default after reset),1: HSE in digital mode" bitfld.long 0x0 19. "HSECSSON,HSE clock security system enable" "0: CSS on HSE OFF (clock detector OFF) (default..,1: CSS on HSE ON (clock detector ON if the HSE.." newline bitfld.long 0x0 18. "HSEBYP,HSE clock bypass" "0: HSE oscillator not bypassed (default after reset),1: HSE oscillator bypassed with an external clock" rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE clock is not ready (default after reset),1: HSE clock is ready" newline bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE is OFF (default after reset),1: HSE is ON" rbitfld.long 0x0 15. "CDCKRDY,CPU domain clocks ready flag" "0: CPU domain clocks are not available (default..,1: CPU domain clocks are available" newline rbitfld.long 0x0 14. "CPUCKRDY,CPU related clocks ready flag" "0: CPU related clocks are not available (default..,1: CPU related clocks are available" rbitfld.long 0x0 13. "HSI48RDY,HSI48 clock ready flag" "0: HSI48 clock is not ready (default after reset),1: HSI48 clock is ready" newline bitfld.long 0x0 12. "HSI48ON,HSI48 clock enable" "0: HSI48 is OFF (default after reset),1: HSI48 is ON" bitfld.long 0x0 9. "CSIKERON,CSI clock enable in Stop mode" "0: no effect on CSI (default after reset),1: CSI is forced to ON even in Stop mode" newline rbitfld.long 0x0 8. "CSIRDY,CSI clock ready flag" "0: CSI clock is not ready (default after reset),1: CSI clock is ready" bitfld.long 0x0 7. "CSION,CSI clock enable" "0: CSI is OFF (default after reset),1: CSI is ON" newline rbitfld.long 0x0 5. "HSIDIVF,HSI divider flag" "0: new division ratio not yet propagated to..,1: hsi(_ker)_ck clock frequency reflects the new.." bitfld.long 0x0 3.--4. "HSIDIV,HSI clock divider" "0: division by 1 hsi(_ker)_ck = 64 MHz (default..,1: division by 2 hsi(_ker)_ck = 32 MHz,2: division by 4 hsi(_ker)_ck = 16 MHz,3: division by 8 hsi(_ker)_ck = 8 MHz" newline rbitfld.long 0x0 2. "HSIRDY,HSI clock ready flag" "0: HSI clock is not ready (default after reset),1: HSI clock is ready" bitfld.long 0x0 1. "HSIKERON,HSI clock enable in Stop mode" "0: no effect on HSI (default after reset),1: HSI is forced to ON even in Stop mode" newline bitfld.long 0x0 0. "HSION,HSI clock enable" "0: HSI is OFF,1: HSI is ON (default after reset)" line.long 0x4 "RCC_HSICFGR,RCC HSI calibration register" hexmask.long.byte 0x4 24.--30. 1. "HSITRIM,HSI clock trimming" hexmask.long.word 0x4 0.--11. 1. "HSICAL,HSI clock calibration" rgroup.long 0x8++0x3 line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register" hexmask.long.word 0x0 0.--9. 1. "HSI48CAL,Internal RC 48 MHz clock calibration" group.long 0xC++0x7 line.long 0x0 "RCC_CSICFGR,RCC CSI calibration register" hexmask.long.byte 0x0 24.--29. 1. "CSITRIM,CSI clock trimming" hexmask.long.byte 0x0 0.--7. 1. "CSICAL,CSI clock calibration" line.long 0x4 "RCC_CFGR," bitfld.long 0x4 29.--31. "MCO2SEL,microcontroller clock output 2" "0: system clock selected (sys_ck) (default after..,1: PLL2 oscillator clock selected (pll2_p_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_p_ck),4: CSI clock selected (csi_ck),5: LSI clock selected (lsi_ck),?,?" hexmask.long.byte 0x4 25.--28. 1. "MCO2PRE,MCO2 prescaler" newline bitfld.long 0x4 22.--24. "MCO1SEL,Microcontroller clock output 1" "0: HSI clock selected (hsi_ck) (default after reset),1: LSE oscillator clock selected (lse_ck),2: HSE clock selected (hse_ck),3: PLL1 clock selected (pll1_q_ck),4: HSI48 clock selected (hsi48_ck),?,?,?" hexmask.long.byte 0x4 18.--21. 1. "MCO1PRE,MCO1 prescaler" newline bitfld.long 0x4 15. "TIMPRE,timers clocks prescaler selection" "0: The timers kernel clock is equal to rcc_hclk1 if..,1: The timers kernel clock is equal to 2 x.." hexmask.long.byte 0x4 8.--13. 1. "RTCPRE,HSE division factor for RTC clock" newline bitfld.long 0x4 7. "STOPKERWUCK,kernel clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" bitfld.long 0x4 6. "STOPWUCK,system clock selection after a wake up from system Stop" "0: HSI selected as wake up clock from system Stop..,1: CSI selected as wake up clock from system Stop" newline rbitfld.long 0x4 3.--5. "SWS,system clock switch status" "0: HSI used as system clock (hsi_ck) (default after..,1: CSI used as system clock (csi_ck),2: HSE used as system clock (hse_ck),3: PLL1 used as system clock (pll1_p_ck),?,?,?,?" bitfld.long 0x4 0.--2. "SW,system clock and trace clock switch" "0: HSI selected as system clock (hsi_ck) (default..,1: CSI selected as system clock (csi_ck),2: HSE selected as system clock (hse_ck),3: PLL1 selected as system clock (pll1_p_ck for..,?,?,?,?" group.long 0x18++0xB line.long 0x0 "RCC_CDCFGR1," hexmask.long.byte 0x0 8.--11. 1. "CDCPRE,CPU domain core prescaler" bitfld.long 0x0 4.--6. "CDPPRE,CPU domain APB3 prescaler" "?,?,?,?,4: rcc_pclk3 = rcc_hclk3 / 2,5: rcc_pclk3 = rcc_hclk3 / 4,6: rcc_pclk3 = rcc_hclk3 / 8,7: rcc_pclk3 = rcc_hclk3 / 16" newline hexmask.long.byte 0x0 0.--3. 1. "HPRE,CPU domain AHB prescaler" line.long 0x4 "RCC_CDCFGR2," bitfld.long 0x4 8.--10. "CDPPRE2,CPU domain APB2 prescaler" "?,?,?,?,4: rcc_pclk2 = rcc_hclk1 / 2,5: rcc_pclk2 = rcc_hclk1 / 4,6: rcc_pclk2 = rcc_hclk1 / 8,7: rcc_pclk2 = rcc_hclk1 / 16" bitfld.long 0x4 4.--6. "CDPPRE1,CPU domain APB1 prescaler" "?,?,?,?,4: rcc_pclk1 = rcc_hclk1 / 2,5: rcc_pclk1 = rcc_hclk1 / 4,6: rcc_pclk1 = rcc_hclk1 / 8,7: rcc_pclk1 = rcc_hclk1 / 16" line.long 0x8 "RCC_SRDCFGR," bitfld.long 0x8 4.--6. "SRDPPRE,SmartRun domain APB4 prescaler" "?,?,?,?,4: rcc_pclk4 = rcc_hclk4 / 2,5: rcc_pclk4 = rcc_hclk4 / 4,6: rcc_pclk4 = rcc_hclk4 / 8,7: rcc_pclk4 = rcc_hclk4 / 16" group.long 0x28++0x1F line.long 0x0 "RCC_PLLCKSELR," hexmask.long.byte 0x0 20.--25. 1. "DIVM3,prescaler for PLL3" hexmask.long.byte 0x0 12.--17. 1. "DIVM2,prescaler for PLL2" newline hexmask.long.byte 0x0 4.--9. 1. "DIVM1,prescaler for PLL1" bitfld.long 0x0 0.--1. "PLLSRC,DIVMx and PLLs clock source selection" "0: HSI selected as PLL clock (hsi_ck) (default..,1: CSI selected as PLL clock (csi_ck),2: HSE selected as PLL clock (hse_ck),3: no clock send to DIVMx divider and PLLs" line.long 0x4 "RCC_PLLCFGR," bitfld.long 0x4 24. "DIVR3EN,PLL3 DIVR divider output enable" "0: pll3_r_ck output disabled,1: pll3_r_ck output enabled (default after reset)" bitfld.long 0x4 23. "DIVQ3EN,PLL3 DIVQ divider output enable" "0: pll3_q_ck output disabled,1: pll3_q_ck output enabled (default after reset)" newline bitfld.long 0x4 22. "DIVP3EN,PLL3 DIVP divider output enable" "0: pll3_p_ck output disabled,1: pll3_p_ck output enabled (default after reset)" bitfld.long 0x4 21. "DIVR2EN,PLL2 DIVR divider output enable" "0: pll2_r_ck output disabled,1: pll2_r_ck output enabled (default after reset)" newline bitfld.long 0x4 20. "DIVQ2EN,PLL2 DIVQ divider output enable" "0: pll2_q_ck output disabled,1: pll2_q_ck output enabled (default after reset)" bitfld.long 0x4 19. "DIVP2EN,PLL2 DIVP divider output enable" "0: pll2_p_ck output disabled,1: pll2_p_ck output enabled (default after reset)" newline bitfld.long 0x4 18. "DIVR1EN,PLL1 DIVR divider output enable" "0: pll1_r_ck output disabled,1: pll1_r_ck output enabled (default after reset)" bitfld.long 0x4 17. "DIVQ1EN,PLL1 DIVQ divider output enable" "0: pll1_q_ck output disabled,1: pll1_q_ck output enabled (default after reset)" newline bitfld.long 0x4 16. "DIVP1EN,PLL1 DIVP divider output enable" "0: pll1_p_ck output disabled,1: pll1_p_ck output enabled (default after reset)" bitfld.long 0x4 10.--11. "PLL3RGE,PLL3 input frequency range" "0: PLL3 input (ref3_ck) clock range frequency..,1: PLL3 input (ref3_ck) clock range frequency..,2: PLL3 input (ref3_ck) clock range frequency..,3: PLL3 input (ref3_ck) clock range frequency.." newline bitfld.long 0x4 9. "PLL3VCOSEL,PLL3 VCO selection" "0: wide VCO range 128 to 560 MHz (default after..,1: medium VCO range 150 to 420 MHz" bitfld.long 0x4 8. "PLL3FRACEN,PLL3 fractional latch enable" "0,1" newline bitfld.long 0x4 6.--7. "PLL2RGE,PLL2 input frequency range" "0: PLL2 input (ref2_ck) clock range frequency..,1: PLL2 input (ref2_ck) clock range frequency..,2: PLL2 input (ref2_ck) clock range frequency..,3: PLL2 input (ref2_ck) clock range frequency.." bitfld.long 0x4 5. "PLL2VCOSEL,PLL2 VCO selection" "0: wide VCO range 128 to 560 MHz (default after..,1: medium VCO range 150 to 420 MHz" newline bitfld.long 0x4 4. "PLL2FRACEN,PLL2 fractional latch enable" "0,1" bitfld.long 0x4 2.--3. "PLL1RGE,PLL1 input frequency range" "0: PLL1 input (ref1_ck) clock range frequency..,1: PLL1 input (ref1_ck) clock range frequency..,2: PLL1 input (ref1_ck) clock range frequency..,3: PLL1 input (ref1_ck) clock range frequency.." newline bitfld.long 0x4 1. "PLL1VCOSEL,PLL1 VCO selection" "0: wide VCO range from 128 to 560 MHz (default..,1: medium VCO range from 150 to 420 MHz" bitfld.long 0x4 0. "PLL1FRACEN,PLL1 fractional latch enable" "0,1" line.long 0x8 "RCC_PLL1DIVR," hexmask.long.byte 0x8 24.--30. 1. "DIVR1,PLL1 DIVR division factor" hexmask.long.byte 0x8 16.--22. 1. "DIVQ1,PLL1 DIVQ division factor" newline hexmask.long.byte 0x8 9.--15. 1. "DIVP1,PLL1 DIVP division factor" hexmask.long.word 0x8 0.--8. 1. "DIVN1,multiplication factor for PLL1 VCO" line.long 0xC "RCC_PLL1FRACR," hexmask.long.word 0xC 3.--15. 1. "FRACN1,fractional part of the multiplication factor for PLL1 VCO" line.long 0x10 "RCC_PLL2DIVR," hexmask.long.byte 0x10 24.--30. 1. "DIVR2,PLL2 DIVR division factor" hexmask.long.byte 0x10 16.--22. 1. "DIVQ2,PLL2 DIVQ division factor" newline hexmask.long.byte 0x10 9.--15. 1. "DIVP2,PLL2 DIVP division factor" hexmask.long.word 0x10 0.--8. 1. "DIVN2,multiplication factor for PLL2 VCO" line.long 0x14 "RCC_PLL2FRACR," hexmask.long.word 0x14 3.--15. 1. "FRACN2,fractional part of the multiplication factor for PLL2 VCO" line.long 0x18 "RCC_PLL3DIVR," hexmask.long.byte 0x18 24.--30. 1. "DIVR3,PLL3 DIVR division factor" hexmask.long.byte 0x18 16.--22. 1. "DIVQ3,PLL3 DIVQ division factor" newline hexmask.long.byte 0x18 9.--15. 1. "DIVP3,PLL3 DIVP division factor" hexmask.long.word 0x18 0.--8. 1. "DIVN3,Multiplication factor for PLL3 VCO" line.long 0x1C "RCC_PLL3FRACR," hexmask.long.word 0x1C 3.--15. 1. "FRACN3,fractional part of the multiplication factor for PLL3 VCO" group.long 0x4C++0xF line.long 0x0 "RCC_CDCCIPR,RCC CPU domain kernel clock configuration register" bitfld.long 0x0 28.--29. "CKPERSEL,per_ck clock source selection" "0: hsi_ker_ck selected as per_ck clock (default..,1: csi_ker_ck selected as per_ck clock,2: hse_ck selected as per_ck clock,3: reserved the per_ck clock is disabled" bitfld.long 0x0 16. "SDMMCSEL,SDMMC kernel clock source selection" "0: pll1_q_ck selected as kernel peripheral clock..,1: pll2_r_ck selected as kernel peripheral clock" newline bitfld.long 0x0 4.--5. "OCTOSPISEL,OCTOSPI kernel clock source selection" "0: rcc_hclk3 selected as kernel peripheral clock..,1: pll1_q_ck selected as kernel peripheral clock,2: pll2_r_ck selected as kernel peripheral clock,3: per_ck selected as kernel peripheral clock" bitfld.long 0x0 0.--1. "FMCSEL,FMC kernel clock source selection" "0: rcc_hclk3 selected as kernel peripheral clock..,1: pll1_q_ck selected as kernel peripheral clock,2: pll2_r_ck selected as kernel peripheral clock,3: per_ck selected as kernel peripheral clock" line.long 0x4 "RCC_CDCCIP1R,RCC CPU domain kernel clock configuration register" bitfld.long 0x4 31. "SWPMISEL,SWPMI kernel clock source selection" "0: rcc_pclk1 selected as SWPMI kernel clock..,1: hsi_ker_ck selected as SWPMI kernel clock" bitfld.long 0x4 28.--29. "FDCANSEL,FDCAN kernel clock source selection" "0: hse_ck clock selected as FDCAN kernel clock..,1: pll1_q_ck selected as FDCAN kernel clock,2: pll2_q_ck selected as FDCAN kernel clock,3: reserved the kernel clock is disabled" newline bitfld.long 0x4 24. "DFSDM1SEL,DFSDM1 kernel clock Clk source selection" "0: rcc_pclk2 selected as DFSDM1 Clk kernel clock..,1: sys_ck selected as DFSDM1 Clk kernel clock" bitfld.long 0x4 20.--21. "SPDIFRXSEL,SPDIFRX kernel clock source selection" "0: pll1_q_ck selected as SPDIFRX kernel clock..,1: pll2_r_ck selected as SPDIFRX kernel clock,2: pll3_r_ck selected as SPDIFRX kernel clock,3: hsi_ker_ck selected as SPDIFRX kernel clock" newline bitfld.long 0x4 16.--18. "SPI45SEL,SPI4 and 5 kernel clock source selection" "0: rcc_pclk2 clock selected as kernel clock..,1: pll2_q_ck is selected as kernel clock,2: pll3_q_ck is selected as kernel clock,3: hsi_ker_ck is selected as kernel clock,4: csi_ker_ck is selected as kernel clock,5: hse_ck is selected as kernel clock,?,?" bitfld.long 0x4 12.--14. "SPI123SEL,SPI/I2S1 2 and 3 kernel clock source selection" "0: pll1_q_ck selected as SPI/I2S1 2 and 3 kernel..,1: pll2_p_ck selected as SPI/I2S1 2 and 3 kernel..,2: pll3_p_ck selected as SPI/I2S1 2 and 3 kernel..,3: I2S_CKIN selected as SPI/I2S1 2 and 3 kernel clock,4: per_ck selected as SPI/I2S1 2 and 3 kernel clock,?,?,?" newline bitfld.long 0x4 9.--11. "SAI2BSEL,SAI2 kernel clock B source selection" "0: pll1_q_ck selected as SAI2 kernel clock B..,1: pll2_p_ck selected as SAI2 kernel clock B,2: pll3_p_ck selected as SAI2 kernel clock B,3: I2S_CKIN selected as SAI2 kernel clock B,4: per_ck selected as SAI2 kernel clock B,5: spdifrx_symb_ck selected as SAI2 kernel clock B,?,?" bitfld.long 0x4 6.--8. "SAI2ASEL,SAI2 kernel clock source A selection" "0: pll1_q_ck selected as SAI2 kernel clock A..,1: pll2_p_ck selected as SAI2 kernel clock A,2: pll3_p_ck selected as SAI2 kernel clock A,3: I2S_CKIN selected as SAI2 kernel clock A,4: per_ck selected as SAI2 kernel clock A,5: spdifrx_symb_ck selected as SAI2 kernel clock A,?,?" newline bitfld.long 0x4 0.--2. "SAI1SEL,SAI1 and DFSDM1 kernel Aclk clock source selection" "0: pll1_q_ck selected as SAI1 and DFSDM1 Aclk..,1: pll2_p_ck selected as SAI1 and DFSDM1 Aclk..,2: pll3_p_ck selected as SAI1 and DFSDM1 Aclk..,3: I2S_CKIN selected as SAI1 and DFSDM1 Aclk kernel..,4: per_ck selected as SAI1 and DFSDM1 Aclk kernel..,?,?,?" line.long 0x8 "RCC_CDCCIP2R,RCC CPU domain kernel clock configuration register" bitfld.long 0x8 28.--30. "LPTIM1SEL,LPTIM1 kernel clock source selection" "0: rcc_pclk1 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" bitfld.long 0x8 22.--23. "CECSEL,HDMI-CEC kernel clock source selection" "0: lse_ck selected as kernel clock (default after..,1: lsi_ck selected as kernel clock,2: csi_ker_ck divided by 122 selected as kernel..,3: reserved the kernel clock is disabled" newline bitfld.long 0x8 20.--21. "USBSEL,USBOTG 1 and 2 kernel clock source selection" "0: Disable the kernel clock (default after reset),1: pll1_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi48_ck selected as kernel clock" bitfld.long 0x8 12.--13. "I2C123SEL,I2C1 2 3 kernel clock source selection" "0: rcc_pclk1 selected as kernel clock (default..,1: pll3_r_ck selected as kernel clock,2: hsi_ker_ck selected as kernel clock,3: csi_ker_ck selected as kernel clock" newline bitfld.long 0x8 8.--9. "RNGSEL,RNG kernel clock source selection" "0: hsi48_ck selected as kernel clock (default after..,1: pll1_q_ck selected as kernel clock,2: lse_ck selected as kernel clock,3: lsi_ck selected as kernel clock" bitfld.long 0x8 3.--5. "USART16910SEL,USART1 6 9 and 10 kernel clock source selection" "0: rcc_pclk2 selected as kernel clock (default..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?" newline bitfld.long 0x8 0.--2. "USART234578SEL,USART2/3 UART4 5 7 and 8 (APB1) kernel clock source selection" "0: rcc_pclk1 selected as kernel clock (default..,1: pll2_q_ck selected as kernel clock,2: pll3_q_ck selected as kernel clock,3: hsi_ker_ck selected as kernel clock,4: csi_ker_ck selected as kernel clock,5: lse_ck selected as kernel clock,?,?" line.long 0xC "RCC_SRDCCIPR,RCC SmartRun domain kernel clock configuration register" bitfld.long 0xC 28.--30. "SPI6SEL,SPI6 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: hse_ck selected as kernel peripheral clock,6: I2S_CKIN selected as kernel peripheral clock,?" bitfld.long 0xC 27. "DFSDM2SEL,DFSDM2 kernel Clk clock source selection" "0: rcc_pclk4 selected as DFSDM2 Clk kernel clock..,1: sys_ck selected as DFSDM2 Clk kernel clock" newline bitfld.long 0xC 16.--17. "ADCSEL,SAR ADC kernel clock source selection" "0: pll2_p_ck selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: per_ck selected as kernel peripheral clock,?" bitfld.long 0xC 13.--15. "LPTIM3SEL,LPTIM3 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" newline bitfld.long 0xC 10.--12. "LPTIM2SEL,LPTIM2 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_p_ck selected as kernel peripheral clock,2: pll3_r_ck selected as kernel peripheral clock,3: lse_ck selected as kernel peripheral clock,4: lsi_ck selected as kernel peripheral clock,5: per_ck selected as kernel peripheral clock,?,?" bitfld.long 0xC 8.--9. "I2C4SEL,I2C4 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll3_r_ck selected as kernel peripheral clock,2: hsi_ker_ck selected as kernel peripheral clock,3: csi_ker_ck selected as kernel peripheral clock" newline bitfld.long 0xC 0.--2. "LPUART1SEL,LPUART1 kernel clock source selection" "0: rcc_pclk4 selected as kernel peripheral clock..,1: pll2_q_ck selected as kernel peripheral clock,2: pll3_q_ck selected as kernel peripheral clock,3: hsi_ker_ck selected as kernel peripheral clock,4: csi_ker_ck selected as kernel peripheral clock,5: lse_ck selected as kernel peripheral clock,?,?" group.long 0x60++0x3 line.long 0x0 "RCC_CIER," bitfld.long 0x0 9. "LSECSSIE,LSE clock security system interrupt enable" "0: LSE CSS interrupt disabled (default after reset),1: LSE CSS interrupt enabled" bitfld.long 0x0 8. "PLL3RDYIE,PLL3 ready interrupt enable" "0: PLL3 lock interrupt disabled (default after reset),1: PLL3 lock interrupt enabled" newline bitfld.long 0x0 7. "PLL2RDYIE,PLL2 ready interrupt enable" "0: PLL2 lock interrupt disabled (default after reset),1: PLL2 lock interrupt enabled" bitfld.long 0x0 6. "PLL1RDYIE,PLL1 ready interrupt enable" "0: PLL1 lock interrupt disabled (default after reset),1: PLL1 lock interrupt enabled" newline bitfld.long 0x0 5. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled (default after..,1: HSI48 ready interrupt enabled" bitfld.long 0x0 4. "CSIRDYIE,CSI ready interrupt enable" "0: CSI ready interrupt disabled (default after reset),1: CSI ready interrupt enabled" newline bitfld.long 0x0 3. "HSERDYIE,HSE ready interrupt enable" "0: HSE ready interrupt disabled (default after reset),1: HSE ready interrupt enabled" bitfld.long 0x0 2. "HSIRDYIE,HSI ready interrupt enable" "0: HSI ready interrupt disabled (default after reset),1: HSI ready interrupt enabled" newline bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: LSE ready interrupt disabled (default after reset),1: LSE ready interrupt enabled" bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: LSI ready interrupt disabled (default after reset),1: LSI ready interrupt enabled" rgroup.long 0x64++0x3 line.long 0x0 "RCC_CIFR," bitfld.long 0x0 10. "HSECSSF,HSE clock security system interrupt flag" "0: no clock security interrupt caused by HSE clock..,1: clock security interrupt caused by HSE clock.." bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: no failure detected on the external 32 kHz..,1: failure detected on the external 32 kHz oscillator" newline bitfld.long 0x0 8. "PLL3RDYF,PLL3 ready interrupt flag" "0: no clock ready interrupt caused by PLL3 lock..,1: clock ready interrupt caused by PLL3 lock" bitfld.long 0x0 7. "PLL2RDYF,PLL2 ready interrupt flag" "0: no clock ready interrupt caused by PLL2 lock..,1: clock ready interrupt caused by PLL2 lock" newline bitfld.long 0x0 6. "PLL1RDYF,PLL1 ready interrupt flag" "0: no clock ready interrupt caused by PLL1 lock..,1: clock ready interrupt caused by PLL1 lock" bitfld.long 0x0 5. "HSI48RDYF,HSI48 ready interrupt flag" "0: no clock ready interrupt caused by the HSI48..,1: clock ready interrupt caused by the HSI48.." newline bitfld.long 0x0 4. "CSIRDYF,CSI ready interrupt flag" "0: no clock ready interrupt caused by the CSI..,1: clock ready interrupt caused by the CSI" bitfld.long 0x0 3. "HSERDYF,HSE ready interrupt flag" "0: no clock ready interrupt caused by the HSE..,1: clock ready interrupt caused by the HSE" newline bitfld.long 0x0 2. "HSIRDYF,HSI ready interrupt flag" "0: no clock ready interrupt caused by the HSI..,1: clock ready interrupt caused by the HSI" bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: no clock ready interrupt caused by the LSE..,1: clock ready interrupt caused by the LSE" newline bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: no clock ready interrupt caused by the LSI..,1: clock ready interrupt caused by the LSI" group.long 0x68++0x3 line.long 0x0 "RCC_CICR," bitfld.long 0x0 10. "HSECSSC,HSE clock security system interrupt clear" "0: HSECSSF no effect (default after reset),1: HSECSSF cleared" bitfld.long 0x0 9. "LSECSSC,LSE clock security system interrupt clear" "0: LSECSSF no effect (default after reset),1: LSECSSF cleared" newline bitfld.long 0x0 8. "PLL3RDYC,PLL3 ready interrupt clear" "0: PLL3RDYF no effect (default after reset),1: PLL3RDYF cleared" bitfld.long 0x0 7. "PLL2RDYC,PLL2 ready interrupt clear" "0: PLL2RDYF no effect (default after reset),1: PLL2RDYF cleared" newline bitfld.long 0x0 6. "PLL1RDYC,PLL1 ready interrupt clear" "0: PLL1RDYF no effect (default after reset),1: PLL1RDYF cleared" bitfld.long 0x0 5. "HSI48RDYC,HSI48 ready interrupt clear" "0: HSI48RDYF no effect (default after reset),1: HSI48RDYF cleared" newline bitfld.long 0x0 4. "CSIRDYC,CSI ready interrupt clear" "0: CSIRDYF no effect (default after reset),1: CSIRDYF cleared" bitfld.long 0x0 3. "HSERDYC,HSE ready interrupt clear" "0: HSERDYF no effect (default after reset),1: HSERDYF cleared" newline bitfld.long 0x0 2. "HSIRDYC,HSI ready interrupt clear" "0: HSIRDYF no effect (default after reset),1: HSIRDYF cleared" bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: LSERDYF no effect (default after reset),1: LSERDYF cleared" newline bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: LSIRDYF no effect (default after reset),1: LSIRDYF cleared" group.long 0x70++0x7 line.long 0x0 "RCC_BDCR,RCC Backup domain control register" bitfld.long 0x0 16. "VSWRST,VSwitch domain software reset" "0: reset not activated (default after Backup domain..,1: resets the entire VSW domain" bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0: rtc_ck disabled (default after Backup domain..,1: rtc_ck enabled" newline bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0: no clock (default after Backup domain reset),1: LSE selected as RTC clock,2: LSI selected as RTC clock,3: HSE divided by RTCPRE value selected as RTC clock" bitfld.long 0x0 7. "LSEEXT,low-speed external clock type in Bypass mode" "0: LSE in analog mode (default after Backup domain..,1: LSE in digital mode (do not use if RTC is active)." newline rbitfld.long 0x0 6. "LSECSSD,LSE clock security system failure detection" "0: no failure detected on 32 kHz oscillator..,1: failure detected on 32 kHz oscillator" bitfld.long 0x0 5. "LSECSSON,LSE clock security system enable" "0: CSS on 32 kHz oscillator OFF (default after..,1: CSS on 32 kHz oscillator ON" newline bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator driving capability" "0: lowest drive (default after Backup domain reset),1: medium-low drive,2: medium-high drive,3: highest drive" bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: LSE oscillator not bypassed (default after..,1: LSE oscillator bypassed" newline rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: LSE oscillator not ready (default after Backup..,1: LSE oscillator ready" bitfld.long 0x0 0. "LSEON,LSE oscillator enabled" "0: LSE oscillator OFF (default after Backup domain..,1: LSE oscillator ON" line.long 0x4 "RCC_CSR,RCC clock control and status register" rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: LSI clock is not ready (default after reset),1: LSI clock is ready" bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0: LSI is OFF (default after reset),1: LSI is ON" group.long 0x7C++0x23 line.long 0x0 "RCC_AHB3RSTR," bitfld.long 0x0 24. "GFXMMURST,GFXMMU reset" "0: does not reset the GFXMMU (default after reset),1: resets the GFXMMU" bitfld.long 0x0 23. "OTFD2RST,OTFD2 reset" "0: does not reset the OTFD2 (default after reset),1: resets the OTFD2" newline bitfld.long 0x0 22. "OTFD1RST,OTFD1 reset" "0: does not reset the OTFD1 (default after reset),1: resets the OTFD1" bitfld.long 0x0 21. "OCTOSPIMRST,OCTOSPIM reset" "0: does not reset the OCTOSPIM (default after reset),1: resets the OCTOSPIM" newline bitfld.long 0x0 19. "OCTOSPI2RST,OCTOSPI2 and OCTOSPI2 delay block reset" "0: does not reset the OCTOSPI2 and OCTOSPI2 delay..,1: resets the OCTOSPI2 and OCTOSPI2 delay block" bitfld.long 0x0 16. "SDMMC1RST,SDMMC1 and SDMMC1 delay blocks reset" "0: does not reset SDMMC1 and SDMMC1 delay blocks..,1: resets SDMMC1 and SDMMC1 delay blocks" newline bitfld.long 0x0 14. "OCTOSPI1RST,OCTOSPI1 and OCTOSPI1 delay blocks reset" "0: does not reset OCTOSPI1 and OCTOSPI1 delay..,1: resets OCTOSPI1 and OCTOSPI1 delay blocks" bitfld.long 0x0 12. "FMCRST,FMC block reset" "0: does not reset FMC block (default after reset),1: resets FMC block" newline bitfld.long 0x0 5. "JPGDECRST,JPGDEC block reset" "0: does not reset JPGDEC block (default after reset),1: resets JPGDEC block" bitfld.long 0x0 4. "DMA2DRST,DMA2D block reset" "0: does not reset DMA2D block (default after reset),1: resets DMA2D block" newline bitfld.long 0x0 0. "MDMARST,MDMA block reset" "0: does not reset MDMA block (default after reset),1: resets MDMA block" line.long 0x4 "RCC_AHB1RSTR," bitfld.long 0x4 25. "USB1OTGRST,USB1OTG block reset" "0: does not reset USB1OTG block (default after reset),1: resets USB1OTG block" bitfld.long 0x4 9. "CRCRST,CRC block reset" "0: does not reset CRC block (default after reset),1: resets CRC block" newline bitfld.long 0x4 5. "ADC12RST,ADC1 and 2 blocks reset" "0: does not reset ADC1 and 2 blocks (default after..,1: resets ADC1 and 2 blocks" bitfld.long 0x4 1. "DMA2RST,DMA2 and DMAMUX2 blocks reset" "0: does not reset DMA2 and DMAMUX2 blocks (default..,1: resets DMA2 and DMAMUX2 blocks" newline bitfld.long 0x4 0. "DMA1RST,DMA1 and DMAMUX1 blocks reset" "0: does not reset DMA1 and DMAMUX1 blocks (default..,1: resets DMA1 and DMAMUX1 blocks" line.long 0x8 "RCC_AHB2RSTR," bitfld.long 0x8 11. "BDMA1RST,BDMA1 reset (DFSDM dedicated DMA)" "0: does not reset DMA block (default after reset),1: resets DMA block" bitfld.long 0x8 9. "SDMMC2RST,SDMMC2 and SDMMC2 delay blocks reset" "0: does not reset SDMMC2 and SDMMC2 delay blocks..,1: resets SDMMC2 and SDMMC2 delay blocks" newline bitfld.long 0x8 6. "RNGRST,random number generator block reset" "0: does not reset RNG block (default after reset),1: resets RNG block" bitfld.long 0x8 5. "HASHRST,hash block reset" "0: does not reset hash block (default after reset),1: resets hash block" newline bitfld.long 0x8 4. "CRYPTRST,cryptography block reset" "0: does not reset cryptography block (default after..,1: resets cryptography block" bitfld.long 0x8 2. "HSEMRST,HSEM block reset" "0: does not reset HSEM block (default after reset),1: resets HSEM block" newline bitfld.long 0x8 0. "DCMI_PSSIRST,digital camera interface block reset (DCMI or PSSI depending which IP is active)" "0: does not reset the DCMI/PSSI block (default..,1: resets the DCMI/PSSI block" line.long 0xC "RCC_AHB4RSTR," bitfld.long 0xC 21. "BDMA2RST,SmartRun domain DMA and DMAMUX blocks reset" "0: does not reset the DMA and DMAMUX blocks..,1: resets the DMA and DMAMUX blocks" bitfld.long 0xC 10. "GPIOKRST,GPIOK block reset" "0: does not reset the GPIOK block (default after..,1: resets the GPIOK block" newline bitfld.long 0xC 9. "GPIOJRST,GPIOJ block reset" "0: does not reset the GPIOJ block (default after..,1: resets the GPIOJ block" bitfld.long 0xC 8. "GPIOIRST,GPIOI block reset" "0: does not reset the GPIOI block (default after..,1: resets the GPIOI block" newline bitfld.long 0xC 7. "GPIOHRST,GPIOH block reset" "0: does not reset the GPIOH block (default after..,1: resets the GPIOH block" bitfld.long 0xC 6. "GPIOGRST,GPIOG block reset" "0: does not reset the GPIOG block (default after..,1: resets the GPIOG block" newline bitfld.long 0xC 5. "GPIOFRST,GPIOF block reset" "0: does not reset the GPIOF block (default after..,1: resets the GPIOF block" bitfld.long 0xC 4. "GPIOERST,GPIOE block reset" "0: does not reset the GPIOE block (default after..,1: resets the GPIOE block" newline bitfld.long 0xC 3. "GPIODRST,GPIOD block reset" "0: does not reset the GPIOD block (default after..,1: resets the GPIOD block" bitfld.long 0xC 2. "GPIOCRST,GPIOC block reset" "0: does not reset the GPIOC block (default after..,1: resets the GPIOC block" newline bitfld.long 0xC 1. "GPIOBRST,GPIOB block reset" "0: does not reset the GPIOB block (default after..,1: resets the GPIOB block" bitfld.long 0xC 0. "GPIOARST,GPIOA block reset" "0: does not reset the GPIOA block (default after..,1: resets the GPIOA block" line.long 0x10 "RCC_APB3RSTR," bitfld.long 0x10 3. "LTDCRST,LTDC block reset" "0: does not reset the LTDC block (default after..,1: resets the LTDC block" line.long 0x14 "RCC_APB1LRSTR," bitfld.long 0x14 31. "UART8RST,UART8 block reset" "0: does not reset the UART8 block (default after..,1: resets the UART8 block" bitfld.long 0x14 30. "UART7RST,UART7 block reset" "0: does not reset the UART7 block (default after..,1: resets the UART7 block" newline bitfld.long 0x14 29. "DAC1RST,DAC1 (containing two converters) reset" "0: does not reset the DAC1 (default after reset),1: resets the DAC1" bitfld.long 0x14 27. "CECRST,HDMI-CEC block reset" "0: does not reset the HDMI-CEC block (default after..,1: resets the HDMI-CEC block" newline bitfld.long 0x14 23. "I2C3RST,I2C3 block reset" "0: does not reset the I2C3 block (default after..,1: resets the I2C3 block" bitfld.long 0x14 22. "I2C2RST,I2C2 block reset" "0: does not reset the I2C2 block (default after..,1: resets the I2C2 block" newline bitfld.long 0x14 21. "I2C1RST,I2C1 block reset" "0: does not reset the I2C1 block (default after..,1: resets the I2C1 block" bitfld.long 0x14 20. "UART5RST,UART5 block reset" "0: does not reset the UART5 block (default after..,1: resets the UART5 block" newline bitfld.long 0x14 19. "UART4RST,UART4 block reset" "0: does not reset the UART4 block (default after..,1: resets the UART4 block" bitfld.long 0x14 18. "USART3RST,USART3 block reset" "0: does not reset the USART3 block (default after..,1: resets the USART3 block" newline bitfld.long 0x14 17. "USART2RST,USART2 block reset" "0: does not reset the USART2 block (default after..,1: resets the USART2 block" bitfld.long 0x14 16. "SPDIFRXRST,SPDIFRX block reset" "0: does not reset the SPDIFRX block (default after..,1: resets the SPDIFRX block" newline bitfld.long 0x14 15. "SPI3RST,SPI3 block reset" "0: does not reset the SPI3 block (default after..,1: resets the SPI3 block" bitfld.long 0x14 14. "SPI2RST,SPI2 block reset" "0: does not reset the SPI2 block (default after..,1: resets the SPI2 block" newline bitfld.long 0x14 9. "LPTIM1RST,LPTIM1 block reset" "0: does not reset the LPTIM1 block (default after..,1: resets the LPTIM1 block" bitfld.long 0x14 8. "TIM14RST,TIM14 block reset" "0: does not reset the TIM14 block (default after..,1: resets the TIM14 block" newline bitfld.long 0x14 7. "TIM13RST,TIM13 block reset" "0: does not reset the TIM13 block (default after..,1: resets the TIM13 block" bitfld.long 0x14 6. "TIM12RST,TIM12 block reset" "0: does not reset the TIM12 block (default after..,1: resets the TIM12 block" newline bitfld.long 0x14 5. "TIM7RST,TIM7 block reset" "0: does not reset the TIM7 block (default after..,1: resets the TIM7 block" bitfld.long 0x14 4. "TIM6RST,TIM6 block reset" "0: does not reset the TIM6 block (default after..,1: resets the TIM6 block" newline bitfld.long 0x14 3. "TIM5RST,TIM5 block reset" "0: does not reset the TIM5 block (default after..,1: resets the TIM5 block" bitfld.long 0x14 2. "TIM4RST,TIM4 block reset" "0: does not reset the TIM4 block (default after..,1: resets the TIM4 block" newline bitfld.long 0x14 1. "TIM3RST,TIM3 block reset" "0: does not reset the TIM3 block (default after..,1: resets the TIM3 block" bitfld.long 0x14 0. "TIM2RST,TIM2 block reset" "0: does not reset the TIM2 block (default after..,1: resets the TIM2 block" line.long 0x18 "RCC_APB1HRSTR," bitfld.long 0x18 8. "FDCANRST,FDCAN block reset" "0: does not reset the FDCAN block (default after..,1: resets the FDCAN block" bitfld.long 0x18 5. "MDIOSRST,MDIOS block reset" "0: does not reset the MDIOS block (default after..,1: resets the MDIOS block" newline bitfld.long 0x18 4. "OPAMPRST,OPAMP block reset" "0: does not reset the OPAMP block (default after..,1: resets the OPAMP block" bitfld.long 0x18 2. "SWPMIRST,SWPMI block reset" "0: does not reset the SWPMI block (default after..,1: resets the SWPMI block" newline bitfld.long 0x18 1. "CRSRST,clock recovery system reset" "0: does not reset CRS (default after reset),1: resets CRS" line.long 0x1C "RCC_APB2RSTR," bitfld.long 0x1C 30. "DFSDM1RST,DFSDM1 block reset" "0: does not reset DFSDM1 block (default after reset),1: resets DFSDM1 block" bitfld.long 0x1C 23. "SAI2RST,SAI2 block reset" "0: does not reset the SAI2 block (default after..,1: resets the SAI2 block" newline bitfld.long 0x1C 22. "SAI1RST,SAI1 block reset" "0: does not reset the SAI1 (default after reset),1: resets the SAI1" bitfld.long 0x1C 20. "SPI5RST,SPI5 block reset" "0: does not reset the SPI5 block (default after..,1: resets the SPI5 block" newline bitfld.long 0x1C 18. "TIM17RST,TIM17 block reset" "0: does not reset the TIM17 block (default after..,1: resets the TIM17 block" bitfld.long 0x1C 17. "TIM16RST,TIM16 block reset" "0: does not reset the TIM16 block (default after..,1: resets the TIM16 block" newline bitfld.long 0x1C 16. "TIM15RST,TIM15 block reset" "0: does not reset the TIM15 block (default after..,1: resets the TIM15 block" bitfld.long 0x1C 13. "SPI4RST,SPI4 block reset" "0: does not reset the SPI4 block (default after..,1: resets the SPI4 block" newline bitfld.long 0x1C 12. "SPI1RST,SPI1 block reset" "0: does not reset the SPI1 block (default after..,1: resets the SPI1 block" bitfld.long 0x1C 7. "USART10RST,USART10 block reset" "0: does not reset the USART10 block (default after..,1: resets the USART10 block" newline bitfld.long 0x1C 6. "UART9RST,UART9 block reset" "0: does not reset the UART9 block (default after..,1: resets the UART9 block" bitfld.long 0x1C 5. "USART6RST,USART6 block reset" "0: does not reset the USART6 block (default after..,1: resets the USART6 block" newline bitfld.long 0x1C 4. "USART1RST,USART1 block reset" "0: does not reset the USART1 block (default after..,1: resets the USART1 block" bitfld.long 0x1C 1. "TIM8RST,TIM8 block reset" "0: does not reset the TIM8 block (default after..,1: resets the TIM8 block" newline bitfld.long 0x1C 0. "TIM1RST,TIM1 block reset" "0: does not reset the TIM1 block (default after..,1: resets the TIM1 block" line.long 0x20 "RCC_APB4RSTR," bitfld.long 0x20 27. "DFSDM2RST,DFSDM2 block reset" "0: does not reset the DFSDM2 block (default after..,1: resets the DFSDM2 block" bitfld.long 0x20 26. "DTSRST,Digital temperature sensor block reset" "0: does not reset the DTS block (default after reset),1: resets the DTS block" newline bitfld.long 0x20 15. "VREFRST,VREF block reset" "0: does not reset the VREF block (default after..,1: resets the VREF block" bitfld.long 0x20 14. "COMP12RST,COMP1 and 2 blocks reset" "0: does not reset the COMP1 and 2 blocks (default..,1: resets the COMP1 and 2 blocks" newline bitfld.long 0x20 13. "DAC2RST,DAC2 (containing one converter) reset" "0: does not reset the DAC2 (default after reset),1: resets the DAC2" bitfld.long 0x20 10. "LPTIM3RST,LPTIM3 block reset" "0: does not reset the LPTIM3 block (default after..,1: resets the LPTIM3 block" newline bitfld.long 0x20 9. "LPTIM2RST,LPTIM2 block reset" "0: does not reset the LPTIM2 block (default after..,1: resets the LPTIM2 block" bitfld.long 0x20 7. "I2C4RST,I2C4 block reset" "0: does not reset the I2C4 block (default after..,1: resets the I2C4 block" newline bitfld.long 0x20 5. "SPI6RST,SPI6 block reset" "0: does not reset the SPI6 block (default after..,1: resets the SPI6 block" bitfld.long 0x20 3. "LPUART1RST,LPUART1 block reset" "0: does not reset the LPUART1 block (default after..,1: resets the LPUART1 block" newline bitfld.long 0x20 1. "SYSCFGRST,SYSCFG block reset" "0: does not reset the SYSCFG block (default after..,1: resets the SYSCFG block" group.long 0xA8++0x3 line.long 0x0 "RCC_SRDAMR,RCC SmartRun domain Autonomous mode register" bitfld.long 0x0 29. "SRDSRAMAMEN,SmartRun domain SRAM Autonomous mode enable" "0: SRDSRAM clock disabled when the CPU is in CStop..,1: SRDSRAM bus clock enabled when the SmartRun.." bitfld.long 0x0 28. "BKPRAMAMEN,Backup RAM Autonomous mode enable" "0: Backup RAM clock disabled when the CPU is in..,1: Backup RAM clock enabling is controlled by the.." newline bitfld.long 0x0 27. "DFSDM2AMEN,DFSDM2 Autonomous mode enable" "0: DFSDM2 clock disabled when the CPU is in CStop..,1: DFSDM2 peripheral clocks enabled when the.." bitfld.long 0x0 26. "DTSAMEN,Digital temperature sensor Autonomous mode enable" "0: DTS clocks disabled when the CPU is in CStop..,1: DTS clocks enabled when the SmartRun domain is.." newline bitfld.long 0x0 16. "RTCAMEN,RTC Autonomous mode enable" "0: RTC bus clocks disabled when the CPU is in CStop..,1: RTC bus clocks enabled when the SmartRun domain.." bitfld.long 0x0 15. "VREFAMEN,VREF Autonomous mode enable" "0: VREF clocks disabled when the CPU is in CStop..,1: VREF clocks enabled when the SmartRun domain is.." newline bitfld.long 0x0 14. "COMP12AMEN,COMP1 and 2 Autonomous mode enable" "0: COMP1 and 2 peripheral clocks disabled when the..,1: COMP1 and 2 peripheral clocks enabled when the.." bitfld.long 0x0 13. "DAC2AMEN,DAC2 (containing one converter) Autonomous mode enable" "0: DAC2 peripheral clocks disabled when the CPU is..,1: DAC2 peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 10. "LPTIM3AMEN,LPTIM3 Autonomous mode enable" "0: LPTIM3 peripheral clocks disabled when the CPU..,1: LPTIM3 peripheral clocks enabled when the.." bitfld.long 0x0 9. "LPTIM2AMEN,LPTIM2 Autonomous mode enable" "0: LPTIM2 peripheral clocks are disabled when the..,1: LPTIM2 peripheral clocks enabled when the.." newline bitfld.long 0x0 7. "I2C4AMEN,I2C4 Autonomous mode enable" "0: I2C4 peripheral clocks disabled when the CPU is..,1: I2C4 peripheral clocks enabled when the SmartRun.." bitfld.long 0x0 5. "SPI6AMEN,SPI6 Autonomous mode enable" "0: SPI6 peripheral clocks disabled when the CPU is..,1: SPI6 peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 3. "LPUART1AMEN,LPUART1 Autonomous mode enable" "0: LPUART1 peripheral clocks disabled when the CPU..,1: LPUART1 peripheral clocks enabled when the.." bitfld.long 0x0 1. "GPIOAMEN,GPIO Autonomous mode enable" "0: GPIO peripheral clocks disabled when the CPU is..,1: GPIO peripheral clocks enabled when the SmartRun.." newline bitfld.long 0x0 0. "BDMA2AMEN,SmartRun domain DMA and DMAMUX Autonomous mode enable" "0: BDMA2 and DMAMUX2 peripheral clocks disabled..,1: BDMA2 and DMAMUX2 peripheral clocks enabled when.." group.long 0xB0++0x3 line.long 0x0 "RCC_CKGAENR,RCC AXI clocks gating enable register" bitfld.long 0x0 31. "JTAGCKG,JTAG automatic clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The clock is.." bitfld.long 0x0 30. "EXTICKG,EXTI clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The clock is.." newline bitfld.long 0x0 29. "ECCRAMCKG,RAM error code correction (ECC) clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The ECC clock is.." bitfld.long 0x0 17. "GFXMMUSCKG,AXI matrix slave GFXMMU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 16. "AXIRAM3CKG,AXI matrix slave SRAM3 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 15. "AXIRAM2CKG,AXI matrix slave SRAM2 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 14. "AXIRAM1CKG,AXI slave SRAM1 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 13. "OCTOSPI1CKG,AXI slave OCTOSPI1 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 12. "FMCCKG,AXI slave FMC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 11. "OCTOSPI2CKG,AXI slave OCTOSPI2 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 10. "FLIFTCKG,AXI slave Flash interface (FLIFT) clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 9. "AHB34CKG,AXI slave AHB34 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 8. "AHB12CKG,AXI slave AHB12 clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 7. "GFXMMUMCKG,AXI master GFXMMU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 6. "LTDCCKG,AXI master LTDC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 5. "DMA2DCKG,AXI master DMA2D clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 4. "MDMACKG,AXI master MDMA clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 3. "SDMMCCKG,AXI master SDMMC clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 2. "CPUCKG,AXI master CPU clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." bitfld.long 0x0 1. "AHBCKG,AXI master AHB clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI matrix.." newline bitfld.long 0x0 0. "AXICKG,AXI interconnect matrix clock gating" "0: The clock gating is disabled. The clock is..,1: The clock gating is enabled. The AXI.." group.long 0x130++0x27 line.long 0x0 "RCC_RSR,RCC reset status register" rbitfld.long 0x0 30. "LPWRRSTF,reset due to illegal CD DStop or CD DStop2 or CPU CStop flag" "0: no illegal reset occurred (default after..,1: illegal CD DStop or CD DStop2 or CPU CStop reset.." rbitfld.long 0x0 28. "WWDGRSTF,window watchdog reset flag" "0: no window watchdog reset occurred from WWDG..,1: window watchdog reset occurred from WWDG" newline rbitfld.long 0x0 26. "IWDGRSTF,independent watchdog reset flag" "0: no independent watchdog reset occurred (default..,1: independent watchdog reset occurred" rbitfld.long 0x0 24. "SFTRSTF,system reset from CPU reset flag" "0: no CPU software reset occurred (default after..,1: a system reset has been generated by the CPU" newline rbitfld.long 0x0 23. "PORRSTF,POR/PDR reset flag" "0: no POR/PDR reset occurred,1: POR/PDR reset occurred (default after power-on.." rbitfld.long 0x0 22. "PINRSTF,pin reset flag (NRST)" "0: no reset from pin occurred,1: reset from pin occurred (default after power-on.." newline rbitfld.long 0x0 21. "BORRSTF,BOR reset flag" "0: no BOR reset occurred,1: BOR reset occurred (default after power-on reset)" rbitfld.long 0x0 19. "CDRSTF,CPU domain power-switch reset flag" "0: no CPU domain power-switch reset occurred,1: CPU domain power-switch (ePOD2) reset occurred.." newline bitfld.long 0x0 16. "RMVF,remove reset flag" "0: reset of the reset flags not activated (default..,1: resets the value of the reset flags" line.long 0x4 "RCC_AHB3ENR," bitfld.long 0x4 24. "GFXMMUEN,GFXMMU clock enable" "0: GFXMMU clock disabled (default after reset),1: GFXMMU clock enabled" bitfld.long 0x4 23. "OTFD2EN,OTFD2 clock enable" "0: OTFD2 clock disabled (default after reset),1: OTFD2 clock enabled" newline bitfld.long 0x4 22. "OTFD1EN,OTFD1 clock enable" "0: OTFD1 clock disabled (default after reset),1: OTFD1 clock enabled" bitfld.long 0x4 21. "OCTOSPIMEN,OCTOSPIM clock enable" "0: OCTOSPIM clock disabled (default after reset),1: OCTOSPIM clock enabled" newline bitfld.long 0x4 19. "OCTOSPI2EN,OCTOSPI2 clock enable" "0: OCTOSPI2 and OCTOSPI2 delay clock disabled..,1: OCTOSPI2 OCTOSPI2 delay clock enabled" bitfld.long 0x4 16. "SDMMC1EN,SDMMC1 and SDMMC1 delay clock enable" "0: SDMMC1 and SDMMC1 delay clock disabled (default..,1: SDMMC1 and SDMMC1 delay clock enabled" newline bitfld.long 0x4 14. "OCTOSPI1EN,OCTOSPI1 and OCTOSPI1 delay clock enable" "0: OCTOSPI1 and OCTOSPI1 delay clock disabled..,1: OCTOSPI1 and OCTOSPI1 delay clock enabled" bitfld.long 0x4 12. "FMCEN,FMC peripheral clocks enable" "0: FMC peripheral clocks disabled (default after..,1: FMC peripheral clocks enabled" newline bitfld.long 0x4 5. "JPGDECEN,JPGDEC peripheral clock enable" "0: JPGDEC peripheral clock disabled (default after..,1: JPGDEC peripheral clock enabled" bitfld.long 0x4 4. "DMA2DEN,DMA2D peripheral clock enable" "0: DMA2D peripheral clock disabled (default after..,1: DMA2D peripheral clock enabled" newline bitfld.long 0x4 0. "MDMAEN,MDMA peripheral clock enable" "0: MDMA peripheral clock disabled (default after..,1: MDMA peripheral clock enabled" line.long 0x8 "RCC_AHB1ENR," bitfld.long 0x8 26. "USB1ULPIEN,USB_PHY1 clocks enable" "0: USB1ULPI PHY clocks disabled (default after reset),1: USB1ULPI PHY clocks enabled" bitfld.long 0x8 25. "USB1OTGEN,USB1OTG peripheral clocks enable" "0: USB1OTG peripheral clocks disabled (default..,1: USB1OTG peripheral clocks enabled" newline bitfld.long 0x8 9. "CRCEN,CRC peripheral clock enable" "0: CRC peripheral clock disabled (default after..,1: CRC peripheral clock enabled" bitfld.long 0x8 5. "ADC12EN,ADC1 and 2 peripheral clocks enable" "0: ADC1 and 2 peripheral clocks disabled (default..,1: ADC1 and 2 peripheral clocks enabled" newline bitfld.long 0x8 1. "DMA2EN,DMA2 clock enable" "0: DMA2 clock disabled (default after reset),1: DMA2 clock enabled" bitfld.long 0x8 0. "DMA1EN,DMA1 clock enable" "0: DMA1 clock disabled (default after reset),1: DMA1 clock enabled" line.long 0xC "RCC_AHB2ENR," bitfld.long 0xC 30. "AHBSRAM2EN,AHBSRAM2 block enable" "0: AHBSRAM2 interface clock is disabled. (default..,1: AHBSRAM2 interface clock is enabled." bitfld.long 0xC 29. "AHBSRAM1EN,AHBSRAM1 block enable" "0: AHBSRAM1 interface clock is disabled. (default..,1: AHBSRAM1 interface clock is enabled." newline bitfld.long 0xC 11. "BDMA1EN,DMA clock enable (DFSDM dedicated DMA)" "0: DMA clock disabled (default after reset),1: DMA clock enabled" bitfld.long 0xC 9. "SDMMC2EN,SDMMC2 and SDMMC2 delay clock enable" "0: SDMMC2 and SDMMC2 delay clock disabled (default..,1: SDMMC2 and SDMMC2 delay clock enabled" newline bitfld.long 0xC 6. "RNGEN,RNG peripheral clocks enable" "0: RNG peripheral clocks disabled (default after..,1: RNG peripheral clocks enabled:" bitfld.long 0xC 5. "HASHEN,HASH peripheral clock enable" "0: HASH peripheral clock disabled (default after..,1: HASH peripheral clock enabled" newline bitfld.long 0xC 4. "CRYPTEN,CRYPT peripheral clock enable" "0: CRYPT peripheral clock disabled (default after..,1: CRYPT peripheral clock enabled" bitfld.long 0xC 2. "HSEMEN,HSEM peripheral clock enable" "0: HSEM peripheral clock disabled (default after..,1: HSEM peripheral clock enabled" newline bitfld.long 0xC 0. "DCMI_PSSIEN,digital camera interface peripheral clock enable (DCMI or PSSI depending which IP is active)" "0: DCMI/PSSI peripheral clock disabled (default..,1: DCMI/PSSI peripheral clock enabled" line.long 0x10 "RCC_AHB4ENR," bitfld.long 0x10 29. "SRDSRAMEN,SmartRun domain SRAM clock enable" "0: SRDSRAM clock disabled (default after reset),1: SRDSRAM clock enabled" bitfld.long 0x10 28. "BKPRAMEN,Backup RAM clock enable" "0: Backup RAM clock disabled (default after reset),1: Backup RAM clock enabled" newline bitfld.long 0x10 21. "BDMA2EN,SmartRun domain DMA and DMAMUX clock enable" "0: BDMA2 and DMAMUX2 clock disabled (default after..,1: BDMA2 and DMAMUX2 clock enabled" bitfld.long 0x10 10. "GPIOKEN,GPIOK peripheral clock enable" "0: GPIOK peripheral clock disabled (default after..,1: GPIOK peripheral clock enabled" newline bitfld.long 0x10 9. "GPIOJEN,GPIOJ peripheral clock enable" "0: GPIOJ peripheral clock disabled (default after..,1: GPIOJ peripheral clock enabled" bitfld.long 0x10 8. "GPIOIEN,GPIOI peripheral clock enable" "0: GPIOI peripheral clock disabled (default after..,1: GPIOI peripheral clock enabled" newline bitfld.long 0x10 7. "GPIOHEN,GPIOH peripheral clock enable" "0: GPIOH peripheral clock disabled (default after..,1: GPIOH peripheral clock enabled" bitfld.long 0x10 6. "GPIOGEN,GPIOG peripheral clock enable" "0: GPIOG peripheral clock disabled (default after..,1: GPIOG peripheral clock enabled" newline bitfld.long 0x10 5. "GPIOFEN,GPIOF peripheral clock enable" "0: GPIOF peripheral clock disabled (default after..,1: GPIOF peripheral clock enabled" bitfld.long 0x10 4. "GPIOEEN,GPIOE peripheral clock enable" "0: GPIOE peripheral clock disabled (default after..,1: GPIOE peripheral clock enabled" newline bitfld.long 0x10 3. "GPIODEN,GPIOD peripheral clock enable" "0: GPIOD peripheral clock disabled (default after..,1: GPIOD peripheral clock enabled" bitfld.long 0x10 2. "GPIOCEN,GPIOC peripheral clock enable" "0: GPIOC peripheral clock disabled (default after..,1: GPIOC peripheral clock enabled" newline bitfld.long 0x10 1. "GPIOBEN,GPIOB peripheral clock enable" "0: GPIOB peripheral clock disabled (default after..,1: GPIOB peripheral clock enabled" bitfld.long 0x10 0. "GPIOAEN,GPIOA peripheral clock enable" "0: GPIOA peripheral clock disabled (default after..,1: GPIOA peripheral clock enabled" line.long 0x14 "RCC_APB3ENR," bitfld.long 0x14 6. "WWDGEN,WWDG clock enable" "0: WWDG peripheral clock disable (default after..,1: WWDG peripheral clock enabled" bitfld.long 0x14 3. "LTDCEN,LTDC clock enable" "0: LTDC peripheral clock disabled (default after..,1: LTDC peripheral clock provided to the LTDC block" line.long 0x18 "RCC_APB1LENR," bitfld.long 0x18 31. "UART8EN,UART8 peripheral clocks enable" "0: UART8 peripheral clocks disabled (default after..,1: UART8 peripheral clocks enabled" bitfld.long 0x18 30. "UART7EN,UART7 peripheral clocks enable" "0: UART7 peripheral clocks disabled (default after..,1: UART7 peripheral clocks enabled" newline bitfld.long 0x18 29. "DAC1EN,DAC1 (containing two converters) peripheral clock enable" "0: DAC1 peripheral clock disabled (default after..,1: DAC1 peripheral clock enabled" bitfld.long 0x18 27. "CECEN,HDMI-CEC peripheral clock enable" "0: HDMI-CEC peripheral clock disabled (default..,1: HDMI-CEC peripheral clock enabled" newline bitfld.long 0x18 23. "I2C3EN,I2C3 peripheral clocks enable" "0: I2C3 peripheral clocks disabled (default after..,1: I2C3 peripheral clocks enabled" bitfld.long 0x18 22. "I2C2EN,I2C2 peripheral clocks enable" "0: I2C2 peripheral clocks disabled (default after..,1: I2C2 peripheral clocks enabled" newline bitfld.long 0x18 21. "I2C1EN,I2C1 peripheral clocks enable" "0: I2C1 peripheral clocks disabled (default after..,1: I2C1 peripheral clocks enabled" bitfld.long 0x18 20. "UART5EN,UART5 peripheral clocks enable" "0: UART5 peripheral clocks disabled (default after..,1: UART5 peripheral clocks enabled" newline bitfld.long 0x18 19. "UART4EN,UART4 peripheral clocks enable" "0: UART4 peripheral clocks disabled (default after..,1: UART4 peripheral clocks enabled" bitfld.long 0x18 18. "USART3EN,USART3 peripheral clocks enable" "0: USART3 peripheral clocks disabled (default after..,1: USART3 peripheral clocks enabled" newline bitfld.long 0x18 17. "USART2EN,USART2peripheral clocks enable" "0: USART2 peripheral clocks disabled (default after..,1: USART2 peripheral clocks enabled" bitfld.long 0x18 16. "SPDIFRXEN,SPDIFRX peripheral clocks enable" "0: SPDIFRX peripheral clocks disabled (default..,1: SPDIFRX peripheral clocks enabled" newline bitfld.long 0x18 15. "SPI3EN,SPI3 peripheral clocks enable" "0: SPI3 peripheral clocks disabled (default after..,1: SPI3 peripheral clocks enabled" bitfld.long 0x18 14. "SPI2EN,SPI2 peripheral clocks enable" "0: SPI2 peripheral clocks disabled (default after..,1: SPI2 peripheral clocks enabled" newline bitfld.long 0x18 9. "LPTIM1EN,LPTIM1 peripheral clocks enable" "0: LPTIM1 peripheral clocks disabled (default after..,1: LPTIM1 peripheral clocks enabled" bitfld.long 0x18 8. "TIM14EN,TIM14 peripheral clock enable" "0: TIM14 peripheral clock disabled (default after..,1: TIM14 peripheral clock enabled" newline bitfld.long 0x18 7. "TIM13EN,TIM13 peripheral clock enable" "0: TIM13 peripheral clock disabled (default after..,1: TIM13 peripheral clock enabled" bitfld.long 0x18 6. "TIM12EN,TIM12 peripheral clock enable" "0: TIM12 peripheral clock disabled (default after..,1: TIM12 peripheral clock enabled" newline bitfld.long 0x18 5. "TIM7EN,TIM7 peripheral clock enable" "0: TIM7 peripheral clock disabled (default after..,1: TIM7 peripheral clock enabled" bitfld.long 0x18 4. "TIM6EN,TIM6 peripheral clock enable" "0: TIM6 peripheral clock disabled (default after..,1: TIM6 peripheral clock enabled" newline bitfld.long 0x18 3. "TIM5EN,TIM5 peripheral clock enable" "0: TIM5 peripheral clock disabled (default after..,1: TIM5 peripheral clock enabled" bitfld.long 0x18 2. "TIM4EN,TIM4 peripheral clock enable" "0: TIM4 peripheral clock disable (default after..,1: TIM4 peripheral clock enabled" newline bitfld.long 0x18 1. "TIM3EN,TIM3 peripheral clock enable" "0: TIM3 peripheral clock disabled (default after..,1: TIM3 peripheral clock enabled" bitfld.long 0x18 0. "TIM2EN,TIM2 peripheral clock enable" "0: TIM2 peripheral clock disabled (default after..,1: TIM2 peripheral clock enabled" line.long 0x1C "RCC_APB1HENR," bitfld.long 0x1C 8. "FDCANEN,FDCAN peripheral clocks enable" "0: FDCAN peripheral clocks disabled (default after..,1: FDCAN peripheral clocks enabled:" bitfld.long 0x1C 5. "MDIOSEN,MDIOS peripheral clock enable" "0: MDIOS peripheral clock disabled (default after..,1: MDIOS peripheral clock enabled" newline bitfld.long 0x1C 4. "OPAMPEN,OPAMP peripheral clock enable" "0: OPAMP peripheral clock disabled (default after..,1: OPAMP peripheral clock enabled" bitfld.long 0x1C 2. "SWPMIEN,SWPMI peripheral clocks enable" "0: SWPMI peripheral clocks disabled (default after..,1: SWPMI peripheral clocks enabled:" newline bitfld.long 0x1C 1. "CRSEN,clock recovery system peripheral clock enable" "0: CRS peripheral clock disabled (default after..,1: CRS peripheral clock enabled" line.long 0x20 "RCC_APB2ENR," bitfld.long 0x20 30. "DFSDM1EN,DFSDM1 peripheral clocks enable" "0: DFSDM1 peripheral clocks disabled (default after..,1: DFSDM1 peripheral clocks enabled" bitfld.long 0x20 23. "SAI2EN,SAI2 peripheral clocks enable" "0: SAI2 peripheral clocks disabled (default after..,1: SAI2 peripheral clocks enabled" newline bitfld.long 0x20 22. "SAI1EN,SAI1 peripheral clocks enable" "0: SAI1 peripheral clocks disabled (default after..,1: SAI1 peripheral clocks enabled:" bitfld.long 0x20 20. "SPI5EN,SPI5 peripheral clocks enable" "0: SPI5 peripheral clocks disabled (default after..,1: SPI5 peripheral clocks enabled:" newline bitfld.long 0x20 18. "TIM17EN,TIM17 peripheral clock enable" "0: TIM17 peripheral clock disabled (default after..,1: TIM17 peripheral clock enabled" bitfld.long 0x20 17. "TIM16EN,TIM16 peripheral clock enable" "0: TIM16 peripheral clock disabled (default after..,1: TIM16 peripheral clock enabled" newline bitfld.long 0x20 16. "TIM15EN,TIM15 peripheral clock enable" "0: TIM15 peripheral clock disabled (default after..,1: TIM15 peripheral clock enabled" bitfld.long 0x20 13. "SPI4EN,SPI4 Peripheral Clocks Enable" "0: SPI4 peripheral clocks disabled (default after..,1: SPI4 peripheral clocks enabled:" newline bitfld.long 0x20 12. "SPI1EN,SPI1 Peripheral Clocks Enable" "0: SPI1 peripheral clocks disabled (default after..,1: SPI1 peripheral clocks enabled:" bitfld.long 0x20 7. "USART10EN,USART10 peripheral clocks enable" "0: USART10 peripheral clocks disabled (default..,1: USART10 peripheral clocks enabled:" newline bitfld.long 0x20 6. "UART9EN,UART9 peripheral clocks enable" "0: UART9 peripheral clocks disabled (default after..,1: UART9 peripheral clocks enabled:" bitfld.long 0x20 5. "USART6EN,USART6 peripheral clocks enable" "0: USART6 peripheral clocks disabled (default after..,1: USART6 peripheral clocks enabled:" newline bitfld.long 0x20 4. "USART1EN,USART1 peripheral clocks enable" "0: USART1 peripheral clocks disabled (default after..,1: USART1 peripheral clocks enabled:" bitfld.long 0x20 1. "TIM8EN,TIM8 peripheral clock enable" "0: TIM8 peripheral clock disabled (default after..,1: TIM8 peripheral clock enabled" newline bitfld.long 0x20 0. "TIM1EN,TIM1 peripheral clock enable" "0: TIM1 peripheral clock disabled (default after..,1: TIM1 peripheral clock enabled" line.long 0x24 "RCC_APB4ENR," bitfld.long 0x24 27. "DFSDM2EN,DFSDM2peripheral clock enable" "0: DFSDM2peripheral peripheral clock disabled..,1: DFSDM2peripheral peripheral clock enabled" bitfld.long 0x24 26. "DTSEN,Digital temperature sensor peripheral clock enable" "0: DTS peripheral clock disabled (default after..,1: DTS peripheral clock enabled" newline bitfld.long 0x24 16. "RTCAPBEN,RTC APB clock enable" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.." bitfld.long 0x24 15. "VREFEN,VREF peripheral clock enable" "0: VREF peripheral clock disabled (default after..,1: VREF peripheral clock enabled" newline bitfld.long 0x24 14. "COMP12EN,COMP1 and 2 peripheral clock enable" "0: COMP1 and 2 peripheral clock disabled (default..,1: COMP1 and 2 peripheral clock enabled" bitfld.long 0x24 13. "DAC2EN,DAC2 (containing one converter) peripheral clock enable" "0: DAC2 peripheral clock disabled (default after..,1: DAC2 peripheral clock enabled" newline bitfld.long 0x24 10. "LPTIM3EN,LPTIM3 peripheral clocks enable" "0: LPTIM3 peripheral clocks disabled (default after..,1: LPTIM3 peripheral clocks enabled" bitfld.long 0x24 9. "LPTIM2EN,LPTIM2 peripheral clocks enable" "0: LPTIM2 peripheral clocks disabled (default after..,1: LPTIM2 peripheral clocks enabled" newline bitfld.long 0x24 7. "I2C4EN,I2C4 peripheral clocks enable" "0: I2C4 peripheral clocks disabled (default after..,1: I2C4 peripheral clocks enabled" bitfld.long 0x24 5. "SPI6EN,SPI6 peripheral clocks enable" "0: SPI6 peripheral clocks disabled (default after..,1: SPI6 peripheral clocks enabled" newline bitfld.long 0x24 3. "LPUART1EN,LPUART1 peripheral clocks enable" "0: LPUART1 peripheral clocks disabled (default..,1: LPUART1 peripheral clocks enabled" bitfld.long 0x24 1. "SYSCFGEN,SYSCFG peripheral clock enable" "0: SYSCFG peripheral clock disabled (default after..,1: SYSCFG peripheral clock enabled" group.long 0x15C++0x23 line.long 0x0 "RCC_AHB3LPENR," bitfld.long 0x0 31. "AXISRAM1LPEN,AXISRAM1 block clock enable during CSleep mode" "0: AXISRAM1 interface clock disabled during CSleep..,1: AXISRAM1 interface clock enabled during CSleep.." bitfld.long 0x0 30. "ITCMLPEN,ITCM block clock enable during CSleep mode" "0: ITCM interface clock disabled during CSleep mode,1: ITCM interface clock enabled during CSleep mode.." newline bitfld.long 0x0 29. "DTCM2LPEN,DTCM2 block clock enable during CSleep mode" "0: DTCM2 interface clock disabled during CSleep mode,1: DTCM2 interface clock enabled during CSleep mode.." bitfld.long 0x0 28. "DTCM1LPEN,DTCM1 block clock enable during CSleep mode" "0: DTCM1 interface clock disabled during CSleep mode,1: DTCM1 interface clock enabled during CSleep mode.." newline bitfld.long 0x0 27. "AXISRAM3LPEN,AXISRAM3 block clock enable during CSleep mode" "0: AXISRAM3 interface clock disabled during CSleep..,1: AXISRAM3 interface clock enabled during CSleep.." bitfld.long 0x0 26. "AXISRAM2LPEN,AXISRAM2 block clock enable during CSleep mode" "0: AXISRAM2 interface clock disabled during CSleep..,1: AXISRAM2 interface clock enabled during CSleep.." newline bitfld.long 0x0 24. "GFXMMULPEN,GFXMMU block clock enable during CSleep mode" "0: GFXMMU interface clock disabled during CSleep mode,1: GFXMMU interface clock enabled during CSleep.." bitfld.long 0x0 23. "OTFD2LPEN,OTFD2 block clock enable during CSleep mode" "0: OTFD2 interface clock disabled during CSleep mode,1: OTFD2 interface clock enabled during CSleep mode.." newline bitfld.long 0x0 22. "OTFD1LPEN,OTFD1 block clock enable during CSleep mode" "0: OTFD1 interface clock disabled during CSleep mode,1: OTFD1 interface clock enabled during CSleep mode.." bitfld.long 0x0 21. "OCTOSPIMLPEN,OCTOSPIM block clock enable during CSleep mode" "0: OCTOSPIM interface clock disabled during CSleep..,1: OCTOSPIM interface clock enabled during CSleep.." newline bitfld.long 0x0 19. "OCTOSPI2LPEN,OCTOSPI2 and OCTOSPI2 delay clock enable during CSleep mode" "0: OCTOSPI2 and OCTOSPI2 delay clock disabled..,1: OCTOSPI2 and OCTOSPI2 delay clock enabled during.." bitfld.long 0x0 16. "SDMMC1LPEN,SDMMC1 and SDMMC1 delay clock enable during CSleep mode" "0: SDMMC1 and SDMMC1 delay clock disabled during..,1: SDMMC1 and SDMMC1 delay clock enabled during.." newline bitfld.long 0x0 14. "OCTOSPI1LPEN,OCTOSPI1 and OCTOSPI1 delay clock enable during CSleep mode" "0: OCTOSPI1 and OCTOSPI1 delay clock disabled..,1: OCTOSPI1 and OCTOSPI1 delay clock enabled during.." bitfld.long 0x0 12. "FMCLPEN,FMC peripheral clocks enable during CSleep mode" "0: FMC peripheral clocks disabled during CSleep mode,1: FMC peripheral clocks enabled during CSleep mode.." newline bitfld.long 0x0 8. "FLITFLPEN,FLITF clock enable during CSleep mode" "0: FLITF clock disabled during CSleep mode,1: FLITF clock enabled during CSleep mode (default.." bitfld.long 0x0 5. "JPGDECLPEN,JPGDEC clock enable during CSleep mode" "0: JPGDEC peripheral clock disabled during CSleep..,1: JPGDEC peripheral clock enabled during CSleep.." newline bitfld.long 0x0 4. "DMA2DLPEN,DMA2D clock enable during CSleep mode" "0: DMA2D peripheral clock disabled during CSleep mode,1: DMA2D peripheral clock enabled during CSleep.." bitfld.long 0x0 0. "MDMALPEN,MDMA clock enable during CSleep mode" "0: MDMA peripheral clock disabled during CSleep mode,1: MDMA peripheral clock enabled during CSleep mode.." line.long 0x4 "RCC_AHB1LPENR," bitfld.long 0x4 26. "USB1ULPILPEN,USB_PHY1 clock enable during CSleep mode" "0: USB_PHY1 peripheral clock disabled during CSleep..,1: USB_PHY1 peripheral clock enabled during CSleep.." bitfld.long 0x4 25. "USB1OTGLPEN,USB1OTG peripheral clock enable during CSleep mode" "0: USB1OTG peripheral clock disabled during CSleep..,1: USB1OTG peripheral clock enabled during CSleep.." newline bitfld.long 0x4 9. "CRCLPEN,CRC peripheral clock enable during CSleep mode" "0: CRC peripheral clock disabled during CSleep mode,1: CRC peripheral clock enabled during CSleep mode.." bitfld.long 0x4 5. "ADC12LPEN,ADC1 and 2 peripheral clocks enable during CSleep mode" "0: ADC1 and 2 peripheral clocks disabled during..,1: ADC1 and 2 peripheral clocks enabled during.." newline bitfld.long 0x4 1. "DMA2LPEN,DMA2 clock enable during CSleep mode" "0: DMA2 clock disabled during CSleep mode,1: DMA2 clock enabled during CSleep mode (default.." bitfld.long 0x4 0. "DMA1LPEN,DMA1 clock enable during CSleep mode" "0: DMA1 clock disabled during CSleep mode,1: DMA1 clock enabled during CSleep mode (default.." line.long 0x8 "RCC_AHB2LPENR," bitfld.long 0x8 30. "AHBSRAM2LPEN,AHBSRAM2 clock enable during CSleep mode" "0: AHBSRAM2 clock disabled during CSleep mode,1: AHBSRAM2 clock enabled during CSleep mode.." bitfld.long 0x8 29. "AHBSRAM1LPEN,AHBSRAM1 clock enable during CSleep mode" "0: AHBSRAM1 clock disabled during CSleep mode,1: AHBSRAM1 clock enabled during CSleep mode.." newline bitfld.long 0x8 11. "DFSDMDMALPEN,DFSDMDMA clock enable during CSleep mode" "0: DFSDMDMA clock disabled during CSleep mode,1: DFSDMDMA clock enabled during CSleep mode.." bitfld.long 0x8 9. "SDMMC2LPEN,SDMMC2 and SDMMC2 delay clock enable during CSleep mode" "0: SDMMC2 and SDMMC2 delay clock disabled during..,1: SDMMC2 and SDMMC2 delay clock enabled during.." newline bitfld.long 0x8 6. "RNGLPEN,RNG peripheral clock enable during CSleep mode" "0: RNG peripheral clocks disabled during CSleep mode,1: RNG peripheral clock enabled during CSleep mode.." bitfld.long 0x8 5. "HASHLPEN,HASH peripheral clock enable during CSleep mode" "0: HASH peripheral clock disabled during CSleep mode,1: HASH peripheral clock enabled during CSleep mode.." newline bitfld.long 0x8 4. "CRYPTLPEN,CRYPT peripheral clock enable during CSleep mode" "0: CRYPT peripheral clock disabled during CSleep mode,1: CRYPT peripheral clock enabled during CSleep.." bitfld.long 0x8 0. "DCMI_PSSILPEN,digital camera interface peripheral clock enable during CSleep mode (DCMI or PSSI depending which IP is active)" "0: DCMI/PSSI peripheral clock disabled during..,1: DCMI/PSSI peripheral clock enabled during CSleep.." line.long 0xC "RCC_AHB4LPENR," bitfld.long 0xC 29. "SRDSRAMLPEN,SmartRun domain SRAM clock enable during CSleep mode" "0: SRDSRAM clock disabled during CSleep mode,1: SRDSRAM clock enabled during CSleep mode.." bitfld.long 0xC 28. "BKPRAMLPEN,Backup RAM clock enable during CSleep mode" "0: Backup RAM clock disabled during CSleep mode,1: Backup RAM clock enabled during CSleep mode.." newline bitfld.long 0xC 21. "BDMA2LPEN,SmartRun domain DMA and DMAMUX clock enable during CSleep mode" "0: BDMA2 and DMAMUX2 clock disabled during CSleep..,1: BDMA2 and DMAMUX2 clock enabled during CSleep.." bitfld.long 0xC 10. "GPIOKLPEN,GPIOK peripheral clock enable during CSleep mode" "0: GPIOK peripheral clock disabled during CSleep mode,1: GPIOK peripheral clock enabled during CSleep.." newline bitfld.long 0xC 9. "GPIOJLPEN,GPIOJ peripheral clock enable during CSleep mode" "0: GPIOJ peripheral clock disabled during CSleep mode,1: GPIOJ peripheral clock enabled during CSleep.." bitfld.long 0xC 8. "GPIOILPEN,GPIOI peripheral clock enable during CSleep mode" "0: GPIOI peripheral clock disabled during CSleep mode,1: GPIOI peripheral clock enabled during CSleep.." newline bitfld.long 0xC 7. "GPIOHLPEN,GPIOH peripheral clock enable during CSleep mode" "0: GPIOH peripheral clock disabled during CSleep mode,1: GPIOH peripheral clock enabled during CSleep.." bitfld.long 0xC 6. "GPIOGLPEN,GPIOG peripheral clock enable during CSleep mode" "0: GPIOG peripheral clock disabled during CSleep mode,1: GPIOG peripheral clock enabled during CSleep.." newline bitfld.long 0xC 5. "GPIOFLPEN,GPIOF peripheral clock enable during CSleep mode" "0: GPIOF peripheral clock disabled during CSleep mode,1: GPIOF peripheral clock enabled during CSleep.." bitfld.long 0xC 4. "GPIOELPEN,GPIOE peripheral clock enable during CSleep mode" "0: GPIOE peripheral clock disabled during CSleep mode,1: GPIOE peripheral clock enabled during CSleep.." newline bitfld.long 0xC 3. "GPIODLPEN,GPIOD peripheral clock enable during CSleep mode" "0: GPIOD peripheral clock disabled during CSleep mode,1: GPIOD peripheral clock enabled during CSleep.." bitfld.long 0xC 2. "GPIOCLPEN,GPIOC peripheral clock enable during CSleep mode" "0: GPIOC peripheral clock disabled during CSleep mode,1: GPIOC peripheral clock enabled during CSleep.." newline bitfld.long 0xC 1. "GPIOBLPEN,GPIOB peripheral clock enable during CSleep mode" "0: GPIOB peripheral clock disabled during CSleep mode,1: GPIOB peripheral clock enabled during CSleep.." bitfld.long 0xC 0. "GPIOALPEN,GPIOA peripheral clock enable during CSleep mode" "0: GPIOA peripheral clock disabled during CSleep mode,1: GPIOA peripheral clock enabled during CSleep.." line.long 0x10 "RCC_APB3LPENR," bitfld.long 0x10 6. "WWDGLPEN,WWDG clock enable during CSleep mode" "0: WWDG clock disable during CSleep mode,1: WWDG clock enabled during CSleep mode (default.." bitfld.long 0x10 3. "LTDCLPEN,LTDC peripheral clock enable during CSleep mode" "0: LTDC clock disabled during CSleep mode,1: LTDC clock provided to the LTDC during CSleep.." line.long 0x14 "RCC_APB1LLPENR," bitfld.long 0x14 31. "UART8LPEN,UART8 peripheral clocks enable during CSleep mode" "0: UART8 peripheral clocks disabled during CSleep..,1: UART8 peripheral clocks enabled during CSleep.." bitfld.long 0x14 30. "UART7LPEN,UART7 peripheral clocks enable during CSleep mode" "0: UART7 peripheral clocks disabled during CSleep..,1: UART7 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 29. "DAC1LPEN,DAC1 (containing two converters) peripheral clock enable during CSleep mode" "0: DAC1 peripheral clock disabled during CSleep mode,1: DAC1 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 27. "CECLPEN,HDMI-CEC peripheral clocks enable during CSleep mode" "0: HDMI-CEC peripheral clocks disabled during..,1: HDMI-CEC peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 23. "I2C3LPEN,I2C3 peripheral clocks enable during CSleep mode" "0: I2C3 peripheral clocks disabled during CSleep mode,1: I2C3 peripheral clocks enabled during CSleep.." bitfld.long 0x14 22. "I2C2LPEN,I2C2 peripheral clocks enable during CSleep mode" "0: I2C2 peripheral clocks disabled during CSleep mode,1: I2C2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 21. "I2C1LPEN,I2C1 peripheral clocks enable during CSleep mode" "0: I2C1 peripheral clocks disabled during CSleep mode,1: I2C1 peripheral clocks enabled during CSleep.." bitfld.long 0x14 20. "UART5LPEN,UART5 peripheral clocks enable during CSleep mode" "0: UART5 peripheral clocks disabled during CSleep..,1: UART5 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 19. "UART4LPEN,UART4 peripheral clocks enable during CSleep mode" "0: UART4 peripheral clocks disabled during CSleep..,1: UART4 peripheral clocks enabled during CSleep.." bitfld.long 0x14 18. "USART3LPEN,USART3 peripheral clocks enable during CSleep mode" "0: USART3 peripheral clocks disabled during CSleep..,1: USART3 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 17. "USART2LPEN,USART2 peripheral clocks enable during CSleep mode" "0: USART2 peripheral clocks disabled during CSleep..,1: USART2 peripheral clocks enabled during CSleep.." bitfld.long 0x14 16. "SPDIFRXLPEN,SPDIFRX peripheral clocks enable during CSleep mode" "0: SPDIFRX peripheral clocks disabled during CSleep..,1: SPDIFRX peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 15. "SPI3LPEN,SPI3 peripheral clocks enable during CSleep mode" "0: SPI3 peripheral clocks disabled during CSleep mode,1: SPI3 peripheral clocks enabled during CSleep.." bitfld.long 0x14 14. "SPI2LPEN,SPI2 peripheral clocks enable during CSleep mode" "0: SPI2 peripheral clocks disabled during CSleep mode,1: SPI2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x14 9. "LPTIM1LPEN,LPTIM1 peripheral clocks enable during CSleep mode" "0: LPTIM1 peripheral clocks disabled during CSleep..,1: LPTIM1 peripheral clocks enabled during CSleep.." bitfld.long 0x14 8. "TIM14LPEN,TIM14 peripheral clock enable during CSleep mode" "0: TIM14 peripheral clock disabled during CSleep mode,1: TIM14 peripheral clock enabled during CSleep.." newline bitfld.long 0x14 7. "TIM13LPEN,TIM13 peripheral clock enable during CSleep mode" "0: TIM13 peripheral clock disabled during CSleep mode,1: TIM13 peripheral clock enabled during CSleep.." bitfld.long 0x14 6. "TIM12LPEN,TIM12 peripheral clock enable during CSleep mode" "0: TIM12 peripheral clock disabled during CSleep mode,1: TIM12 peripheral clock enabled during CSleep.." newline bitfld.long 0x14 5. "TIM7LPEN,TIM7 peripheral clock enable during CSleep mode" "0: TIM7 peripheral clock disabled during CSleep mode,1: TIM7 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 4. "TIM6LPEN,TIM6 peripheral clock enable during CSleep mode" "0: TIM6 peripheral clock disabled during CSleep mode,1: TIM6 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x14 3. "TIM5LPEN,TIM5 peripheral clock enable during CSleep mode" "0: TIM5 peripheral clock disabled during CSleep mode,1: TIM5 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 2. "TIM4LPEN,TIM4 peripheral clock enable during CSleep mode" "0: TIM4 peripheral clock disabled during CSleep mode,1: TIM4 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x14 1. "TIM3LPEN,TIM3 peripheral clock enable during CSleep mode" "0: TIM3 peripheral clock disabled during CSleep mode,1: TIM3 peripheral clock enabled during CSleep mode.." bitfld.long 0x14 0. "TIM2LPEN,TIM2 peripheral clock enable during CSleep mode" "0: TIM2 peripheral clock disabled during CSleep mode,1: TIM2 peripheral clock enabled during CSleep mode.." line.long 0x18 "RCC_APB1HLPENR," bitfld.long 0x18 8. "FDCANLPEN,FDCAN peripheral clocks enable during CSleep mode" "0: FDCAN peripheral clocks disabled during CSleep..,1: FDCAN peripheral clocks enabled during CSleep.." bitfld.long 0x18 5. "MDIOSLPEN,MDIOS peripheral clock enable during CSleep mode" "0: MDIOS peripheral clock disabled during CSleep mode,1: MDIOS peripheral clock enabled during CSleep.." newline bitfld.long 0x18 4. "OPAMPLPEN,OPAMP peripheral clock enable during CSleep mode" "0: OPAMP peripheral clock disabled during CSleep mode,1: OPAMP peripheral clock enabled during CSleep.." bitfld.long 0x18 2. "SWPMILPEN,SWPMI peripheral clocks enable during CSleep mode" "0: SWPMI peripheral clocks disabled during CSleep..,1: SWPMI peripheral clocks enabled during CSleep.." newline bitfld.long 0x18 1. "CRSLPEN,clock recovery system peripheral clock enable during CSleep mode" "0: CRS peripheral clock disabled during CSleep mode,1: CRS peripheral clock enabled during CSleep mode.." line.long 0x1C "RCC_APB2LPENR," bitfld.long 0x1C 30. "DFSDM1LPEN,DFSDM1 peripheral clocks enable during CSleep mode" "0: DFSDM1 peripheral clocks disabled during CSleep..,1: DFSDM1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 23. "SAI2LPEN,SAI2 peripheral clocks enable during CSleep mode" "0: SAI2 peripheral clocks disabled during CSleep mode,1: SAI2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 22. "SAI1LPEN,SAI1 peripheral clocks enable during CSleep mode" "0: SAI1 peripheral clocks disabled during CSleep mode,1: SAI1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 20. "SPI5LPEN,SPI5 peripheral clocks enable during CSleep mode" "0: SPI5 peripheral clocks disabled during CSleep mode,1: SPI5 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 18. "TIM17LPEN,TIM17 peripheral clock enable during CSleep mode" "0: TIM17 peripheral clock disabled during CSleep mode,1: TIM17 peripheral clock enabled during CSleep.." bitfld.long 0x1C 17. "TIM16LPEN,TIM16 peripheral clock enable during CSleep mode" "0: TIM16 peripheral clock disabled during CSleep mode,1: TIM16 peripheral clock enabled during CSleep.." newline bitfld.long 0x1C 16. "TIM15LPEN,TIM15 peripheral clock enable during CSleep mode" "0: TIM15 peripheral clock disabled during CSleep mode,1: TIM15 peripheral clock enabled during CSleep.." bitfld.long 0x1C 13. "SPI4LPEN,SPI4 peripheral clock enable during CSleep mode" "0: SPI4 peripheral clocks disabled during CSleep mode,1: SPI4 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 12. "SPI1LPEN,SPI1 peripheral clock enable during CSleep mode" "0: SPI1 peripheral clocks disabled during CSleep mode,1: SPI1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 7. "USART10LPEN,USART10 peripheral clock enable during CSleep mode" "0: USART10 peripheral clocks disabled during CSleep..,1: USART10 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 6. "UART9LPEN,UART9 peripheral clock enable during CSleep mode" "0: UART9 peripheral clocks disabled during CSleep..,1: UART9 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 5. "USART6LPEN,USART6 peripheral clock enable during CSleep mode" "0: USART6 peripheral clocks disabled during CSleep..,1: USART6 peripheral clocks enabled during CSleep.." newline bitfld.long 0x1C 4. "USART1LPEN,USART1 peripheral clock enable during CSleep mode" "0: USART1 peripheral clocks disabled during CSleep..,1: USART1 peripheral clocks enabled during CSleep.." bitfld.long 0x1C 1. "TIM8LPEN,TIM8 peripheral clock enable during CSleep mode" "0: TIM8 peripheral clock disabled during CSleep mode,1: TIM8 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x1C 0. "TIM1LPEN,TIM1 peripheral clock enable during CSleep mode" "0: TIM1 peripheral clock disabled during CSleep mode,1: TIM1 peripheral clock enabled during CSleep mode.." line.long 0x20 "RCC_APB4LPENR," bitfld.long 0x20 27. "DFSDM2LPEN,DFSDM2 peripheral clock enable during CSleep mode" "0: DFSDM2 peripheral clock disabled during CSleep..,1: DFSDM2 peripheral clock enabled during CSleep.." bitfld.long 0x20 26. "DTSLPEN,temperature sensor peripheral clock enable during CSleep mode" "0: DTS peripheral clock disabled during CSleep mode,1: DTS peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 16. "RTCAPBLPEN,RTC APB clock enable during CSleep mode" "0: The register clock interface of the RTC (APB) is..,1: The register clock interface of the RTC (APB) is.." bitfld.long 0x20 15. "VREFLPEN,VREF peripheral clock enable during CSleep mode" "0: VREF peripheral clock disabled during CSleep mode,1: VREF peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 14. "COMP12LPEN,COMP1 and 2 peripheral clock enable during CSleep mode" "0: COMP1 and 2 peripheral clock disabled during..,1: COMP1 and 2 peripheral clock enabled during.." bitfld.long 0x20 13. "DAC2LPEN,DAC2 (containing one converter) peripheral clock enable during CSleep mode" "0: DAC2 peripheral clock disabled during CSleep mode,1: DAC2 peripheral clock enabled during CSleep mode.." newline bitfld.long 0x20 10. "LPTIM3LPEN,LPTIM3 peripheral clocks enable during CSleep mode" "0: LPTIM3 peripheral clocks disabled during CSleep..,1: LPTIM3 peripheral clocks enabled during CSleep.." bitfld.long 0x20 9. "LPTIM2LPEN,LPTIM2 peripheral clocks enable during CSleep mode" "0: LPTIM2 peripheral clocks disabled during CSleep..,1: LPTIM2 peripheral clocks enabled during CSleep.." newline bitfld.long 0x20 7. "I2C4LPEN,I2C4 peripheral clocks enable during CSleep mode" "0: I2C4 peripheral clocks disabled during CSleep mode,1: I2C4 peripheral clocks enabled during CSleep.." bitfld.long 0x20 5. "SPI6LPEN,SPI6 peripheral clocks enable during CSleep mode" "0: SPI6 peripheral clocks disabled during CSleep mode,1: SPI6 peripheral clocks enabled during CSleep.." newline bitfld.long 0x20 3. "LPUART1LPEN,LPUART1 peripheral clocks enable during CSleep mode" "0: LPUART1 peripheral clocks disabled during CSleep..,1: LPUART1 peripheral clocks enabled during CSleep.." bitfld.long 0x20 1. "SYSCFGLPEN,SYSCFG peripheral clock enable during CSleep mode" "0: SYSCFG peripheral clock disabled during CSleep..,1: SYSCFG peripheral clock enabled during CSleep.." endif tree.end tree "RNG (Random Number Generator)" base ad:0x48021800 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H750*")) group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H753*")) group.long 0x0++0x7 line.long 0x0 "CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x7 line.long 0x0 "CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x7 line.long 0x0 "CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x7 line.long 0x0 "CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x7 line.long 0x0 "RNG_CR,RNG control register" bitfld.long 0x0 5. "CED,Clock error detection Note: The clock" "0,1" bitfld.long 0x0 3. "IE,Interrupt enable" "0,1" newline bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1" line.long 0x4 "RNG_SR,RNG status register" bitfld.long 0x4 6. "SEIS,Seed error interrupt status This bit is" "0,1" bitfld.long 0x4 5. "CEIS,Clock error interrupt status This bit is" "0,1" newline rbitfld.long 0x4 2. "SECS,Seed error current status ** More than" "0,1" rbitfld.long 0x4 1. "CECS,Clock error current status Note: This" "0,1" newline rbitfld.long 0x4 0. "DRDY,Data ready Note: If IE=1 in RNG_CR an" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "RNG_DR,The RNG_DR register is a read-only register" hexmask.long 0x0 0.--31. 1. "RNDATA,Random data 32-bit random data which are" endif tree.end tree "RTC (Real-Time Counter)" base ad:0x58004000 group.long 0x0++0x7 line.long 0x0 "RTC_TR,The RTC_TR is the calendar time shadow" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline endif bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format" newline endif hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format" newline endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format" endif hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "RTC_DR,The RTC_DR is the calendar date shadow" hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format" hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7A3*")) bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4 13.--16. 1. "WDU,Week day units" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x4 13.--16. 1. "WDU,Week day units" newline endif bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" newline bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) group.long 0x8++0x7 line.long 0x0 "RTC_CR,RTC control register" bitfld.long 0x0 24. "ITSE,timestamp on internal event" "0,1" bitfld.long 0x0 23. "COE,Calibration output enable This bit" "0,1" newline bitfld.long 0x0 21.--22. "OSEL,Output selection These bits are used to" "0,1,2,3" bitfld.long 0x0 20. "POL,Output polarity This bit is used to" "0,1" newline bitfld.long 0x0 19. "COSEL,Calibration output selection When COE=1 " "?,?" bitfld.long 0x0 18. "BKP,Backup This bit can be written by the" "0,1" newline bitfld.long 0x0 17. "SUB1H,Subtract 1 hour (winter time change)" "0,1" bitfld.long 0x0 16. "ADD1H,Add 1 hour (summer time change) When" "0,1" newline bitfld.long 0x0 15. "TSIE,Time-stamp interrupt" "0,1" bitfld.long 0x0 14. "WUTIE,Wakeup timer interrupt" "0,1" newline bitfld.long 0x0 13. "ALRBIE,Alarm B interrupt enable" "0,1" bitfld.long 0x0 12. "ALRAIE,Alarm A interrupt enable" "0,1" newline bitfld.long 0x0 11. "TSE,timestamp enable" "0,1" bitfld.long 0x0 10. "WUTE,Wakeup timer enable" "0,1" newline bitfld.long 0x0 9. "ALRBE,Alarm B enable" "0,1" bitfld.long 0x0 8. "ALRAE,Alarm A enable" "0,1" newline bitfld.long 0x0 6. "FMT,Hour format" "0,1" bitfld.long 0x0 5. "BYPSHAD,Bypass the shadow registers Note: If the" "0,1" newline bitfld.long 0x0 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0,1" bitfld.long 0x0 3. "TSEDGE,Time-stamp event active edge TSE must be" "0,1" newline bitfld.long 0x0 0.--2. "WUCKSEL,Wakeup clock selection" "0,1,2,3,4,5,6,7" line.long 0x4 "RTC_ISR,This register is write protected (except for" bitfld.long 0x4 17. "ITSF,Internal tTime-stamp flag" "0,1" rbitfld.long 0x4 16. "RECALPF,Recalibration pending Flag The RECALPF" "0,1" newline bitfld.long 0x4 15. "TAMP3F,RTC_TAMP3 detection flag This flag is" "0,1" bitfld.long 0x4 14. "TAMP2F,RTC_TAMP2 detection flag This flag is" "0,1" newline bitfld.long 0x4 13. "TAMP1F,RTC_TAMP1 detection flag This flag is" "0,1" bitfld.long 0x4 12. "TSOVF,Time-stamp overflow flag This flag is" "0,1" newline bitfld.long 0x4 11. "TSF,Time-stamp flag This flag is set by" "0,1" bitfld.long 0x4 10. "WUTF,Wakeup timer flag This flag is set by" "0,1" newline bitfld.long 0x4 9. "ALRBF,Alarm B flag This flag is set by" "0,1" bitfld.long 0x4 8. "ALRAF,Alarm A flag This flag is set by" "0,1" newline bitfld.long 0x4 7. "INIT,Initialization mode" "0,1" rbitfld.long 0x4 6. "INITF,Initialization flag When this bit is set" "0,1" newline bitfld.long 0x4 5. "RSF,Registers synchronization flag This bit" "0,1" rbitfld.long 0x4 4. "INITS,Initialization status flag This bit is" "0,1" newline rbitfld.long 0x4 3. "SHPF,Shift operation pending This flag is set" "0,1" rbitfld.long 0x4 2. "WUTWF,Wakeup timer write flag This bit is set" "0,1" newline rbitfld.long 0x4 1. "ALRBWF,Alarm B write flag This bit is set by" "0,1" rbitfld.long 0x4 0. "ALRAWF,Alarm A write flag This bit is set by" "0,1" group.long 0x1C++0x7 line.long 0x0 "RTC_ALRMAR,This register can be written only when" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1" bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1" newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format." "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD" newline bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1" bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format." newline bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1" newline bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD" line.long 0x4 "RTC_ALRMBR,This register can be written only when" bitfld.long 0x4 31. "MSK4,Alarm B date mask" "0,1" bitfld.long 0x4 30. "WDSEL,Week day selection" "0,1" newline bitfld.long 0x4 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 24.--27. 1. "DU,Date units or day in BCD" newline bitfld.long 0x4 23. "MSK3,Alarm B hours mask" "0,1" bitfld.long 0x4 22. "PM,AM/PM notation" "0,1" newline bitfld.long 0x4 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x4 15. "MSK2,Alarm B minutes mask" "0,1" bitfld.long 0x4 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x4 7. "MSK1,Alarm B seconds mask" "0,1" newline bitfld.long 0x4 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--3. 1. "SU,Second units in BCD format" rgroup.long 0x28++0x3 line.long 0x0 "RTC_SSR,RTC sub second register" hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value SS[15:0] is the value" group.long 0x3C++0x7 line.long 0x0 "RTC_CALR,This register is write protected. The write" bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5ppm" "0,1" bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "?,?" newline bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "?,?" hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus The frequency of the" line.long 0x4 "RTC_TAMPCR,RTC tamper and alternate function" bitfld.long 0x4 24. "TAMP3MF,Tamper 3 mask flag" "0,1" bitfld.long 0x4 23. "TAMP3NOERASE,Tamper 3 no erase" "0,1" newline bitfld.long 0x4 22. "TAMP3IE,Tamper 3 interrupt enable" "0,1" bitfld.long 0x4 21. "TAMP2MF,Tamper 2 mask flag" "0,1" newline bitfld.long 0x4 20. "TAMP2NOERASE,Tamper 2 no erase" "0,1" bitfld.long 0x4 19. "TAMP2IE,Tamper 2 interrupt enable" "0,1" newline bitfld.long 0x4 18. "TAMP1MF,Tamper 1 mask flag" "0,1" bitfld.long 0x4 17. "TAMP1NOERASE,Tamper 1 no erase" "0,1" newline bitfld.long 0x4 16. "TAMP1IE,Tamper 1 interrupt enable" "0,1" bitfld.long 0x4 15. "TAMPPUDIS,RTC_TAMPx pull-up disable This bit" "0,1" newline bitfld.long 0x4 13.--14. "TAMPPRCH,RTC_TAMPx precharge duration These bit" "0,1,2,3" bitfld.long 0x4 11.--12. "TAMPFLT,RTC_TAMPx filter count These bits" "0,1,2,3" newline bitfld.long 0x4 8.--10. "TAMPFREQ,Tamper sampling frequency Determines the" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "TAMPTS,Activate timestamp on tamper detection" "0,1" newline bitfld.long 0x4 6. "TAMP3TRG,Active level for RTC_TAMP3 input if" "0: if TAMPFLT =,?" bitfld.long 0x4 5. "TAMP3E,RTC_TAMP3 detection enable" "0,1" newline bitfld.long 0x4 4. "TAMP2TRG,Active level for RTC_TAMP2 input if" "0: if TAMPFLT =,?" bitfld.long 0x4 3. "TAMP2E,RTC_TAMP2 input detection" "0,1" newline bitfld.long 0x4 2. "TAMPIE,Tamper interrupt enable" "0,1" bitfld.long 0x4 1. "TAMP1TRG,Active level for RTC_TAMP1 input If" "0,1" newline bitfld.long 0x4 0. "TAMP1E,RTC_TAMP1 input detection" "0,1" group.long 0x48++0x3 line.long 0x0 "RTC_ALRMBSSR,This register can be written only when ALRBE" hexmask.long.byte 0x0 24.--27. 1. "MASKSS,Mask the most-significant bits starting" hexmask.long.word 0x0 0.--14. 1. "SS,Sub seconds value This value is compared" group.long 0x50++0x3F line.long 0x0 "RTC_BKP0R,RTC backup registers" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data" line.long 0x4 "RTC_BKP1R,RTC backup registers" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data" line.long 0x8 "RTC_BKP2R,RTC backup registers" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data" line.long 0xC "RTC_BKP3R,RTC backup registers" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data" line.long 0x10 "RTC_BKP4R,RTC backup registers" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data" line.long 0x14 "RTC_BKP5R,RTC backup registers" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data" line.long 0x18 "RTC_BKP6R,RTC backup registers" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data" line.long 0x1C "RTC_BKP7R,RTC backup registers" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data" line.long 0x20 "RTC_BKP8R,RTC backup registers" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data" line.long 0x24 "RTC_BKP9R,RTC backup registers" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data" line.long 0x28 "RTC_BKP10R,RTC backup registers" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data" line.long 0x2C "RTC_BKP11R,RTC backup registers" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data" line.long 0x30 "RTC_BKP12R,RTC backup registers" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data" line.long 0x34 "RTC_BKP13R,RTC backup registers" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data" line.long 0x38 "RTC_BKP14R,RTC backup registers" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data" line.long 0x3C "RTC_BKP15R,RTC backup registers" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data" group.long 0x4C++0x3 line.long 0x0 "RTC_OR,RTC option register" bitfld.long 0x0 1. "RTC_OUT_RMP,RTC_OUT remap" "0,1" bitfld.long 0x0 0. "RTC_ALARM_TYPE,RTC_ALARM output type on" "0,1" group.long 0x90++0x3F line.long 0x0 "RTC_BKP16R,RTC backup registers" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data" line.long 0x4 "RTC_BKP17R,RTC backup registers" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data" line.long 0x8 "RTC_BKP18R,RTC backup registers" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data" line.long 0xC "RTC_BKP19R,RTC backup registers" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data" line.long 0x10 "RTC_BKP20R,RTC backup registers" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data" line.long 0x14 "RTC_BKP21R,RTC backup registers" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data" line.long 0x18 "RTC_BKP22R,RTC backup registers" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data" line.long 0x1C "RTC_BKP23R,RTC backup registers" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data" line.long 0x20 "RTC_BKP24R,RTC backup registers" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data" line.long 0x24 "RTC_BKP25R,RTC backup registers" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data" line.long 0x28 "RTC_BKP26R,RTC backup registers" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data" line.long 0x2C "RTC_BKP27R,RTC backup registers" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data" line.long 0x30 "RTC_BKP28R,RTC backup registers" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data" line.long 0x34 "RTC_BKP29R,RTC backup registers" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data" line.long 0x38 "RTC_BKP30R,RTC backup registers" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data" line.long 0x3C "RTC_BKP31R,RTC backup registers" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x8++0x3 line.long 0x0 "RTC_SSR,RTC sub second register" hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value" group.long 0xC++0x3 line.long 0x0 "RTC_ICSR,RTC initialization control and status register" rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1" bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.." newline rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed" bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized" newline rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized" rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending" newline rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed" rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed" newline rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed" group.long 0x18++0x3 line.long 0x0 "RTC_CR,RTC control register" bitfld.long 0x0 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.." bitfld.long 0x0 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output" newline bitfld.long 0x0 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output" bitfld.long 0x0 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.." newline bitfld.long 0x0 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event" bitfld.long 0x0 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled" newline bitfld.long 0x0 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled" bitfld.long 0x0 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled" newline bitfld.long 0x0 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.." bitfld.long 0x0 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz" newline bitfld.long 0x0 18. "BKP,Backup" "0,1" bitfld.long 0x0 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.." newline bitfld.long 0x0 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.." bitfld.long 0x0 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable" newline bitfld.long 0x0 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled" bitfld.long 0x0 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable" newline bitfld.long 0x0 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled" bitfld.long 0x0 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable" newline bitfld.long 0x0 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled" bitfld.long 0x0 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled" newline bitfld.long 0x0 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled" bitfld.long 0x0 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format" newline bitfld.long 0x0 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.." bitfld.long 0x0 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled" newline bitfld.long 0x0 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.." bitfld.long 0x0 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?" endif sif (cpuis("STM32H7B0*")) rgroup.long 0x8++0x3 line.long 0x0 "RTC_SSR,RTC sub second register" hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value" group.long 0xC++0x3 line.long 0x0 "RTC_ICSR,RTC initialization control and status register" rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1" bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.." newline rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed" bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized" newline rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized" rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending" newline rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed" rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed" newline rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed" group.long 0x18++0x3 line.long 0x0 "RTC_CR,RTC control register" bitfld.long 0x0 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.." bitfld.long 0x0 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output" newline bitfld.long 0x0 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output" bitfld.long 0x0 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.." newline bitfld.long 0x0 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event" bitfld.long 0x0 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled" newline bitfld.long 0x0 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled" bitfld.long 0x0 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled" newline bitfld.long 0x0 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.." bitfld.long 0x0 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz" newline bitfld.long 0x0 18. "BKP,Backup" "0,1" bitfld.long 0x0 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.." newline bitfld.long 0x0 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.." bitfld.long 0x0 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable" newline bitfld.long 0x0 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled" bitfld.long 0x0 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable" newline bitfld.long 0x0 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled" bitfld.long 0x0 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable" newline bitfld.long 0x0 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled" bitfld.long 0x0 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled" newline bitfld.long 0x0 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled" bitfld.long 0x0 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format" newline bitfld.long 0x0 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.." bitfld.long 0x0 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled" newline bitfld.long 0x0 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.." hexmask.long.byte 0x0 0.--3. 1. "WUCKSEL,ck_wut wakeup clock selection" endif sif (cpuis("STM32H7B3*")) rgroup.long 0x8++0x3 line.long 0x0 "RTC_SSR,RTC sub second register" hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value" group.long 0xC++0x3 line.long 0x0 "RTC_ICSR,RTC initialization control and status register" rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1" bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.." newline rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed" bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized" newline rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized" rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending" newline rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed" rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed" newline rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed" group.long 0x18++0x3 line.long 0x0 "RTC_CR,RTC control register" bitfld.long 0x0 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.." bitfld.long 0x0 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output" newline bitfld.long 0x0 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output" bitfld.long 0x0 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.." newline bitfld.long 0x0 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event" bitfld.long 0x0 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled" newline bitfld.long 0x0 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled" bitfld.long 0x0 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled" newline bitfld.long 0x0 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.." bitfld.long 0x0 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz" newline bitfld.long 0x0 18. "BKP,Backup" "0,1" bitfld.long 0x0 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.." newline bitfld.long 0x0 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.." bitfld.long 0x0 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable" newline bitfld.long 0x0 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled" bitfld.long 0x0 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable" newline bitfld.long 0x0 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled" bitfld.long 0x0 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable" newline bitfld.long 0x0 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled" bitfld.long 0x0 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled" newline bitfld.long 0x0 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled" bitfld.long 0x0 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format" newline bitfld.long 0x0 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.." bitfld.long 0x0 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled" newline bitfld.long 0x0 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.." hexmask.long.byte 0x0 0.--3. 1. "WUCKSEL,ck_wut wakeup clock selection" endif group.long 0x10++0x7 line.long 0x0 "RTC_PRER,This register must be written in" hexmask.long.byte 0x0 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor This is" hexmask.long.word 0x0 0.--14. 1. "PREDIV_S,Synchronous prescaler factor This is the" line.long 0x4 "RTC_WUTR,This register can be written only when WUTWF" hexmask.long.word 0x4 0.--15. 1. "WUT,Wakeup auto-reload value bits When the" wgroup.long 0x24++0x3 line.long 0x0 "RTC_WPR,RTC write protection register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key This byte is" endif sif (cpuis("STM32H7A3*")) hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key" endif wgroup.long 0x2C++0x3 line.long 0x0 "RTC_SHIFTR,This register is write protected. The write" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 31. "ADD1S,Add one second This bit is write only" "0,1" hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second These" newline endif sif (cpuis("STM32H7A3*")) bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar" endif sif (cpuis("STM32H7B0*")) bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar" newline endif sif (cpuis("STM32H7B3*")) bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar" endif sif (cpuis("STM32H7A3*")) hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second" endif sif (cpuis("STM32H7B3*")) hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second" endif rgroup.long 0x30++0xB line.long 0x0 "RTC_TSTR,The content of this register is valid only" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x0 22. "PM,AM/PM notation" "0,1" bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format." bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD" bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD" endif sif (cpuis("STM32H7A3*")) rbitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline rbitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format." newline endif sif (cpuis("STM32H7B0*")) rbitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" rbitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format." hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format." newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format." hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format." newline hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." endif sif (cpuis("STM32H7B3*")) rbitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline rbitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format." newline hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format." hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format." newline hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format." hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." newline endif sif (cpuis("STM32H7A3*")) rbitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format." newline endif sif (cpuis("STM32H7A3*")) rbitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." endif line.long 0x4 "RTC_TSDR,The content of this register is valid only" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" endif sif (cpuis("STM32H7A3*")) rbitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4 13.--16. 1. "WDU,Week day units" rbitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x4 13.--16. 1. "WDU,Week day units" newline rbitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1" hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format" newline endif sif (cpuis("STM32H7A3*")) rbitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" newline endif sif (cpuis("STM32H7B0*")) rbitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" newline endif sif (cpuis("STM32H7B3*")) rbitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format" endif line.long 0x8 "RTC_TSSSR,The content of this register is valid only" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value SS[15:0] is the value" endif sif (cpuis("STM32H7A3*")) hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value" endif sif (cpuis("STM32H7B3*")) hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value" endif group.long 0x44++0x3 line.long 0x0 "RTC_ALRMASSR,This register can be written only when ALRAE" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) hexmask.long.byte 0x0 24.--27. 1. "MASKSS,Mask the most-significant bits starting" endif sif (cpuis("STM32H7A3*")) hexmask.long.byte 0x0 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit" newline endif hexmask.long.word 0x0 0.--14. 1. "SS,Sub seconds value This value is compared" sif (cpuis("STM32H7A3*")) group.long 0x24++0x7 line.long 0x0 "RTC_WPR,RTC write protection register" line.long 0x4 "RTC_CALR,RTC calibration register" bitfld.long 0x4 15. "CALP,Increase frequency of RTC by 488.5ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.." bitfld.long 0x4 14. "CALW8,Use an 8-second calibration cycle period" "0,1" newline bitfld.long 0x4 13. "CALW16,Use a 16-second calibration cycle period" "0,1" hexmask.long.word 0x4 0.--8. 1. "CALM,Calibration minus" endif sif (cpuis("STM32H7A3*")) group.long 0x2C++0x3 line.long 0x0 "RTC_SHIFTR,RTC shift control register" endif sif (cpuis("STM32H7A3*")) group.long 0x30++0x3 line.long 0x0 "RTC_TSTR,RTC timestamp time register" endif sif (cpuis("STM32H7A3*")) group.long 0x34++0x3 line.long 0x0 "RTC_TSDR,RTC timestamp date register" endif sif (cpuis("STM32H7A3*")) group.long 0x38++0x3 line.long 0x0 "RTC_TSSSR,RTC timestamp sub second register" group.long 0x40++0x3 line.long 0x0 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison" newline bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." group.long 0x48++0x7 line.long 0x0 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x0 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison" bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison" newline bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "RTC_ALRMBSSR,RTC alarm B sub second register" hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit" hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value" rgroup.long 0x50++0x7 line.long 0x0 "RTC_SR,RTC status register" bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1" bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1" newline bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1" bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1" newline bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1" bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1" line.long 0x4 "RTC_MISR,RTC masked interrupt status register" bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1" bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1" newline bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1" bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1" newline bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1" bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "RTC_SCR,RTC status clear register" bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1" bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1" newline bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1" bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1" newline bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1" bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1" group.long 0x60++0x3 line.long 0x0 "RTC_CFGR,RTC configuration register" bitfld.long 0x0 0. "OUT2_RMP,RTC_OUT2 mapping" "0: RTC_OUT2 is mapped on PB2,1: RTC_OUT2 is mapped on PI8" endif sif (cpuis("STM32H7B0*")) group.long 0x24++0x7 line.long 0x0 "RTC_WPR,RTC write protection register" line.long 0x4 "RTC_CALR,RTC calibration register" bitfld.long 0x4 15. "CALP,Increase frequency of RTC by 488.5ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.." bitfld.long 0x4 14. "CALW8,Use an 8-second calibration cycle period" "0,1" newline bitfld.long 0x4 13. "CALW16,Use a 16-second calibration cycle period" "0,1" hexmask.long.word 0x4 0.--8. 1. "CALM,Calibration minus" endif sif (cpuis("STM32H7B0*")) group.long 0x2C++0x3 line.long 0x0 "RTC_SHIFTR,RTC shift control register" endif sif (cpuis("STM32H7B0*")) group.long 0x30++0x3 line.long 0x0 "RTC_TSTR,RTC timestamp time register" endif sif (cpuis("STM32H7B0*")) group.long 0x34++0x3 line.long 0x0 "RTC_TSDR,RTC timestamp date register" endif sif (cpuis("STM32H7B0*")) group.long 0x38++0x3 line.long 0x0 "RTC_TSSSR,RTC timestamp sub second register" group.long 0x40++0x3 line.long 0x0 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison" hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison" newline hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format." hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." group.long 0x48++0x7 line.long 0x0 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x0 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison" hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison" newline hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "RTC_ALRMBSSR,RTC alarm B sub second register" hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit" hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value" rgroup.long 0x50++0x7 line.long 0x0 "RTC_SR,RTC status register" bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1" bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1" newline bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1" bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1" newline bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1" bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1" line.long 0x4 "RTC_MISR,RTC masked interrupt status register" bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1" bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1" newline bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1" bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1" newline bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1" bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "RTC_SCR,RTC status clear register" bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1" bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1" newline bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1" bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1" newline bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1" bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1" group.long 0x60++0x3 line.long 0x0 "RTC_CFGR,RTC configuration register" bitfld.long 0x0 0. "OUT2_RMP,RTC_OUT2 mapping" "0: RTC_OUT2 is mapped on PB2,1: RTC_OUT2 is mapped on PI8" endif sif (cpuis("STM32H7B3*")) group.long 0x24++0x7 line.long 0x0 "RTC_WPR,RTC write protection register" line.long 0x4 "RTC_CALR,RTC calibration register" bitfld.long 0x4 15. "CALP,Increase frequency of RTC by 488.5ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.." bitfld.long 0x4 14. "CALW8,Use an 8-second calibration cycle period" "0,1" newline bitfld.long 0x4 13. "CALW16,Use a 16-second calibration cycle period" "0,1" hexmask.long.word 0x4 0.--8. 1. "CALM,Calibration minus" endif sif (cpuis("STM32H7B3*")) group.long 0x2C++0x3 line.long 0x0 "RTC_SHIFTR,RTC shift control register" endif sif (cpuis("STM32H7B3*")) group.long 0x30++0x3 line.long 0x0 "RTC_TSTR,RTC timestamp time register" endif sif (cpuis("STM32H7B3*")) group.long 0x34++0x3 line.long 0x0 "RTC_TSDR,RTC timestamp date register" endif sif (cpuis("STM32H7B3*")) group.long 0x38++0x3 line.long 0x0 "RTC_TSSSR,RTC timestamp sub second register" group.long 0x40++0x3 line.long 0x0 "RTC_ALRMAR,RTC alarm A register" bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison" hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison" newline hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format." hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format." group.long 0x48++0x7 line.long 0x0 "RTC_ALRMBR,RTC alarm B register" bitfld.long 0x0 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison" bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.." newline bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format" newline bitfld.long 0x0 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison" bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM" newline bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3" hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format" newline bitfld.long 0x0 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison" hexmask.long.byte 0x0 12.--15. 1. "MNT,Minute tens in BCD format" newline hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format" bitfld.long 0x0 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison" newline hexmask.long.byte 0x0 4.--7. 1. "ST,Second tens in BCD format" hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format" line.long 0x4 "RTC_ALRMBSSR,RTC alarm B sub second register" hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit" hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value" rgroup.long 0x50++0x7 line.long 0x0 "RTC_SR,RTC status register" bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1" bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1" newline bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1" bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1" newline bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1" bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1" line.long 0x4 "RTC_MISR,RTC masked interrupt status register" bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1" bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1" newline bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1" bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1" newline bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1" bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1" wgroup.long 0x5C++0x3 line.long 0x0 "RTC_SCR,RTC status clear register" bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1" bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1" newline bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1" bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1" newline bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1" bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1" group.long 0x60++0x3 line.long 0x0 "RTC_CFGR,RTC configuration register" bitfld.long 0x0 0. "OUT2_RMP,RTC_OUT2 mapping" "0: RTC_OUT2 is mapped on PB2,1: RTC_OUT2 is mapped on PI8" endif tree.end tree "SAI (Serial Audio Interface)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "SAI1" base ad:0x40015800 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" endif bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" endif line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" endif bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" newline bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" newline bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" endif bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" endif line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" endif bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" newline bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 28.--31. 1. "DLYM4R,Delay line for second microphone of pair" hexmask.long.byte 0x8 24.--27. 1. "DLYM4L,Delay line for first microphone of pair" hexmask.long.byte 0x8 20.--23. 1. "DLYM3R,Delay line for second microphone of pair" hexmask.long.byte 0x8 16.--19. 1. "DLYM3L,Delay line for first microphone of pair" hexmask.long.byte 0x8 12.--15. 1. "DLYM2R,Delay line for second microphone of pair" hexmask.long.byte 0x8 8.--11. 1. "DLYM2L,Delay line for first microphone of pair" hexmask.long.byte 0x8 4.--7. 1. "DLYM1R,Delay line adjust for second microphone" hexmask.long.byte 0x8 0.--3. 1. "DLYM1L,Delay line adjust for first microphone" endif tree.end endif sif (cpuis("STM32H742*")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H743*")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H750*")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H753*")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end tree "SAI3" base ad:0x40016000 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "SAI4" base ad:0x58005400 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H7A3*")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" bitfld.long 0x4 5.--7. "DS,Data size. These bits are set and" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" bitfld.long 0x8 0.--2. "FTH,FIFO threshold. This bit is set and" "0,1,2,3,4,5,6,7" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" bitfld.long 0x0 16.--18. "FLVL,FIFO level threshold. This bit is read" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" bitfld.long 0x8 28.--30. "DLYM4R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24.--26. "DLYM4L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 20.--22. "DLYM3R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 16.--18. "DLYM3L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. "DLYM2R,Delay line for second microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 8.--10. "DLYM2L,Delay line for first microphone of pair" "0,1,2,3,4,5,6,7" bitfld.long 0x8 4.--6. "DLYM1R,Delay line adjust for second microphone" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "DLYM1L,Delay line adjust for first microphone" "0,1,2,3,4,5,6,7" tree.end endif sif (cpuis("STM32H7B0*")) tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" hexmask.long.byte 0x8 28.--31. 1. "DLYM4R,Delay line for second microphone of pair" hexmask.long.byte 0x8 24.--27. 1. "DLYM4L,Delay line for first microphone of pair" hexmask.long.byte 0x8 20.--23. 1. "DLYM3R,Delay line for second microphone of pair" hexmask.long.byte 0x8 16.--19. 1. "DLYM3L,Delay line for first microphone of pair" hexmask.long.byte 0x8 12.--15. 1. "DLYM2R,Delay line for second microphone of pair" hexmask.long.byte 0x8 8.--11. 1. "DLYM2L,Delay line for first microphone of pair" hexmask.long.byte 0x8 4.--7. 1. "DLYM1R,Delay line adjust for second microphone" hexmask.long.byte 0x8 0.--3. 1. "DLYM1L,Delay line adjust for first microphone" tree.end endif sif (cpuis("STM32H7B3*")) tree "SAI1" base ad:0x40015800 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" hexmask.long.byte 0x8 28.--31. 1. "DLYM4R,Delay line for second microphone of pair" hexmask.long.byte 0x8 24.--27. 1. "DLYM4L,Delay line for first microphone of pair" hexmask.long.byte 0x8 20.--23. 1. "DLYM3R,Delay line for second microphone of pair" hexmask.long.byte 0x8 16.--19. 1. "DLYM3L,Delay line for first microphone of pair" hexmask.long.byte 0x8 12.--15. 1. "DLYM2R,Delay line for second microphone of pair" hexmask.long.byte 0x8 8.--11. 1. "DLYM2L,Delay line for first microphone of pair" hexmask.long.byte 0x8 4.--7. 1. "DLYM1R,Delay line adjust for second microphone" hexmask.long.byte 0x8 0.--3. 1. "DLYM1L,Delay line adjust for first microphone" tree.end tree "SAI2" base ad:0x40015C00 group.long 0x0++0x17 line.long 0x0 "SAI_GCR,Global configuration register" bitfld.long 0x0 4.--5. "SYNCOUT,Synchronization outputs These bits are" "0,1,2,3" bitfld.long 0x0 0.--1. "SYNCIN,Synchronization inputs" "0,1,2,3" line.long 0x4 "SAI_ACR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_ACR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" line.long 0xC "SAI_AFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_ASLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_AIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "SAI_ASR,Status register" hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x1C++0x3 line.long 0x0 "SAI_ACLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x20++0x17 line.long 0x0 "SAI_ADR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_BCR1,Configuration register 1" bitfld.long 0x4 26. "OSR,Oversampling ratio for master" "0,1" hexmask.long.byte 0x4 20.--23. 1. "MCKDIV,Master clock divider. These bits are set" bitfld.long 0x4 19. "NOMCK,No divider" "0,1" bitfld.long 0x4 17. "DMAEN,DMA enable. This bit is set and cleared" "0,1" bitfld.long 0x4 16. "SAIXEN,Audio block enable where x is A or B." "0,1" bitfld.long 0x4 13. "OUTDRIV,Output drive. This bit is set and" "0,1" bitfld.long 0x4 12. "MONO,Mono mode. This bit is set and cleared" "0,1" bitfld.long 0x4 10.--11. "SYNCEN,Synchronization enable. These bits are" "0,1,2,3" bitfld.long 0x4 9. "CKSTR,Clock strobing edge. This bit is set and" "0,1" newline bitfld.long 0x4 8. "LSBFIRST,Least significant bit first. This bit is" "0,1" hexmask.long.byte 0x4 5.--8. 1. "DS,Data size. These bits are set and" bitfld.long 0x4 2.--3. "PRTCFG,Protocol configuration. These bits are" "0,1,2,3" bitfld.long 0x4 0.--1. "MODE,SAIx audio block mode" "0,1,2,3" line.long 0x8 "SAI_BCR2,Configuration register 2" bitfld.long 0x8 14.--15. "COMP,Companding mode. These bits are set and" "0,1,2,3" bitfld.long 0x8 13. "CPL,Complement bit. This bit is set and" "0,1" hexmask.long.byte 0x8 7.--12. 1. "MUTECNT,Mute counter. These bits are set and" bitfld.long 0x8 6. "MUTEVAL,Mute value. This bit is set and cleared" "0,1" bitfld.long 0x8 5. "MUTE,Mute. This bit is set and cleared by" "0,1" bitfld.long 0x8 4. "TRIS,Tristate management on data line. This" "0,1" bitfld.long 0x8 3. "FFLUSH,FIFO flush. This bit is set by software." "0,1" hexmask.long.byte 0x8 0.--3. 1. "FTH,FIFO threshold. This bit is set and" line.long 0xC "SAI_BFRCR,This register has no meaning in AC97 and" bitfld.long 0xC 18. "FSOFF,Frame synchronization offset. This bit" "0,1" bitfld.long 0xC 17. "FSPOL,Frame synchronization polarity. This bit" "0,1" rbitfld.long 0xC 16. "FSDEF,Frame synchronization definition. This" "0,1" hexmask.long.byte 0xC 8.--14. 1. "FSALL,Frame synchronization active level" hexmask.long.byte 0xC 0.--7. 1. "FRL,Frame length. These bits are set and" line.long 0x10 "SAI_BSLOTR,This register has no meaning in AC97 and" hexmask.long.word 0x10 16.--31. 1. "SLOTEN,Slot enable. These bits are set and" hexmask.long.byte 0x10 8.--11. 1. "NBSLOT,Number of slots in an audio frame. These" bitfld.long 0x10 6.--7. "SLOTSZ,Slot size This bits is set and cleared" "0,1,2,3" hexmask.long.byte 0x10 0.--4. 1. "FBOFF,First bit offset These bits are set and" line.long 0x14 "SAI_BIM,Interrupt mask register 2" bitfld.long 0x14 6. "LFSDETIE,Late frame synchronization detection" "0,1" bitfld.long 0x14 5. "AFSDETIE,Anticipated frame synchronization" "0,1" bitfld.long 0x14 4. "CNRDYIE,Codec not ready interrupt enable (AC97)." "0,1" bitfld.long 0x14 3. "FREQIE,FIFO request interrupt enable. This bit" "0,1" bitfld.long 0x14 2. "WCKCFGIE,Wrong clock configuration interrupt" "0,1" bitfld.long 0x14 1. "MUTEDETIE,Mute detection interrupt enable. This" "0,1" bitfld.long 0x14 0. "OVRUDRIE,Overrun/underrun interrupt enable. This" "0,1" rgroup.long 0x38++0x3 line.long 0x0 "SAI_BSR,Status register" hexmask.long.byte 0x0 16.--19. 1. "FLVL,FIFO level threshold. This bit is read" bitfld.long 0x0 6. "LFSDET,Late frame synchronization detection." "0,1" bitfld.long 0x0 5. "AFSDET,Anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CNRDY,Codec not ready. This bit is read only." "0,1" bitfld.long 0x0 3. "FREQ,FIFO request. This bit is read only. The" "0,1" bitfld.long 0x0 2. "WCKCFG,Wrong clock configuration flag. This bit" "0,1" bitfld.long 0x0 1. "MUTEDET,Mute detection. This bit is read only." "0,1" bitfld.long 0x0 0. "OVRUDR,Overrun / underrun. This bit is read" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "SAI_BCLRFR,Clear flag register" bitfld.long 0x0 6. "CLFSDET,Clear late frame synchronization" "0,1" bitfld.long 0x0 5. "CAFSDET,Clear anticipated frame synchronization" "0,1" bitfld.long 0x0 4. "CCNRDY,Clear Codec not ready flag. This bit is" "0,1" bitfld.long 0x0 2. "CWCKCFG,Clear wrong clock configuration flag." "0,1" bitfld.long 0x0 1. "CMUTEDET,Mute detection flag. This bit is write" "0,1" bitfld.long 0x0 0. "COVRUDR,Clear overrun / underrun. This bit is" "0,1" group.long 0x40++0xB line.long 0x0 "SAI_BDR,Data register" hexmask.long 0x0 0.--31. 1. "DATA,Data A write to this register loads the" line.long 0x4 "SAI_PDMCR,PDM control register" bitfld.long 0x4 11. "CKEN4,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 10. "CKEN3,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 9. "CKEN2,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 8. "CKEN1,Clock enable of bitstream clock number" "0,1" bitfld.long 0x4 4.--5. "MICNBR,Number of microphones" "0,1,2,3" bitfld.long 0x4 0. "PDMEN,PDM enable" "0,1" line.long 0x8 "SAI_PDMDLY,PDM delay register" hexmask.long.byte 0x8 28.--31. 1. "DLYM4R,Delay line for second microphone of pair" hexmask.long.byte 0x8 24.--27. 1. "DLYM4L,Delay line for first microphone of pair" hexmask.long.byte 0x8 20.--23. 1. "DLYM3R,Delay line for second microphone of pair" hexmask.long.byte 0x8 16.--19. 1. "DLYM3L,Delay line for first microphone of pair" hexmask.long.byte 0x8 12.--15. 1. "DLYM2R,Delay line for second microphone of pair" hexmask.long.byte 0x8 8.--11. 1. "DLYM2L,Delay line for first microphone of pair" hexmask.long.byte 0x8 4.--7. 1. "DLYM1R,Delay line adjust for second microphone" hexmask.long.byte 0x8 0.--3. 1. "DLYM1L,Delay line adjust for first microphone" tree.end endif tree.end tree "SDMMC (Secure Digital Input/Output and MultiMediaCard Interface)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SDMMC1" base ad:0x52007000 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" newline bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" newline bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" newline bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" endif sif (cpuis("STM32H742*")) group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" newline bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" newline bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" newline bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." endif sif (cpuis("STM32H742*")) rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SDMMC2" base ad:0x48022400 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" newline bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" newline bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" newline bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" endif sif (cpuis("STM32H742*")) group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" newline bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" newline bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" newline bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" newline bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" newline bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" newline bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" newline bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" newline bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" newline bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" newline bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" newline bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" newline bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" newline bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" newline bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" newline bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" newline bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" newline bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" newline bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" newline bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" newline bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" newline bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" newline bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" newline bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" newline bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" newline bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" newline bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" newline bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" newline bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" newline bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" newline bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" newline bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" newline bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." endif sif (cpuis("STM32H742*")) rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" endif tree.end endif sif (cpuis("STM32H743*")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H743*")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H750*")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H750*")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H753*")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H753*")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x10++0x3 line.long 0x0 "RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H7A3*")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H7A3*")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H7B0*")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H7B0*")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H7B3*")) tree "SDMMC1" base ad:0x52007000 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif sif (cpuis("STM32H7B3*")) tree "SDMMC2" base ad:0x48022400 group.long 0x0++0xF line.long 0x0 "SDMMC_POWER,SDMMC power control register" bitfld.long 0x0 4. "DIRPOL,Data and command direction signals" "0,1" bitfld.long 0x0 3. "VSWITCHEN,Voltage switch procedure enable. This" "0,1" bitfld.long 0x0 2. "VSWITCH,Voltage switch sequence start. This bit" "0,1" bitfld.long 0x0 0.--1. "PWRCTRL,SDMMC state control bits. These bits can" "0,1,2,3" line.long 0x4 "SDMMC_CLKCR,The SDMMC_CLKCR register controls the" bitfld.long 0x4 20.--21. "SELCLKRX,Receive clock selection. These bits can" "0,1,2,3" bitfld.long 0x4 19. "BUSSPEED,Bus speed mode selection between DS HS " "0,1" bitfld.long 0x4 18. "DDR,Data rate signaling selection This bit" "0,1" bitfld.long 0x4 17. "HWFC_EN,Hardware flow control enable This bit" "0,1" bitfld.long 0x4 16. "NEGEDGE,SDMMC_CK dephasing selection bit for" "0: - SDMMC_CK,1: - Data" bitfld.long 0x4 14.--15. "WIDBUS,Wide bus mode enable bit This bit can" "0,1,2,3" newline bitfld.long 0x4 12. "PWRSAV,Power saving configuration bit This bit" "0,1" hexmask.long.word 0x4 0.--9. 1. "CLKDIV,Clock divide factor This bit can only be" line.long 0x8 "SDMMC_ARGR,The SDMMC_ARGR register contains a 32-bit" hexmask.long 0x8 0.--31. 1. "CMDARG,Command argument. These bits can only be" line.long 0xC "SDMMC_CMDR,The SDMMC_CMDR register contains the command" bitfld.long 0xC 16. "CMDSUSPEND,The CPSM treats the command as a Suspend" "0,1" bitfld.long 0xC 15. "BOOTEN,Enable boot mode" "0,1" bitfld.long 0xC 14. "BOOTMODE,Select the boot mode procedure to be" "0,1" bitfld.long 0xC 13. "DTHOLD,Hold new data block transmission and" "0,1" bitfld.long 0xC 12. "CPSMEN,Command path state machine (CPSM) Enable" "0,1" bitfld.long 0xC 11. "WAITPEND,CPSM Waits for end of data transfer" "0,1" newline bitfld.long 0xC 10. "WAITINT,CPSM waits for interrupt request. If" "0,1" bitfld.long 0xC 8.--9. "WAITRESP,Wait for response bits. This bit can" "0,1,2,3" bitfld.long 0xC 7. "CMDSTOP,The CPSM treats the command as a Stop" "0,1" bitfld.long 0xC 6. "CMDTRANS,The CPSM treats the command as a data" "0,1" hexmask.long.byte 0xC 0.--5. 1. "CMDINDEX,Command index. This bit can only be" rgroup.long 0x14++0xF line.long 0x0 "SDMMC_RESP1R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x0 0.--31. 1. "CARDSTATUS1,see Table 432" line.long 0x4 "SDMMC_RESP2R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x4 0.--31. 1. "CARDSTATUS2,see Table404." line.long 0x8 "SDMMC_RESP3R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0x8 0.--31. 1. "CARDSTATUS3,see Table404." line.long 0xC "SDMMC_RESP4R,The SDMMC_RESP1/2/3/4R registers contain the" hexmask.long 0xC 0.--31. 1. "CARDSTATUS4,see Table404." group.long 0x24++0xB line.long 0x0 "SDMMC_DTIMER,The SDMMC_DTIMER register contains the data" hexmask.long 0x0 0.--31. 1. "DATATIME,Data and R1b busy timeout period This" line.long 0x4 "SDMMC_DLENR,The SDMMC_DLENR register contains the number" hexmask.long 0x4 0.--24. 1. "DATALENGTH,Data length value This register can only" line.long 0x8 "SDMMC_DCTRL,The SDMMC_DCTRL register control the data" bitfld.long 0x8 13. "FIFORST,FIFO reset will flush any remaining" "0,1" bitfld.long 0x8 12. "BOOTACKEN,Enable the reception of the boot" "0,1" bitfld.long 0x8 11. "SDIOEN,SD I/O interrupt enable functions This" "0,1" bitfld.long 0x8 10. "RWMOD,Read wait mode. This bit can only be" "0,1" bitfld.long 0x8 9. "RWSTOP,Read wait stop This bit is written by" "0,1" bitfld.long 0x8 8. "RWSTART,Read wait start. If this bit is set " "0,1" newline hexmask.long.byte 0x8 4.--7. 1. "DBLOCKSIZE,Data block size This bit can only be" bitfld.long 0x8 2.--3. "DTMODE,Data transfer mode selection. This bit" "0,1,2,3" bitfld.long 0x8 1. "DTDIR,Data transfer direction selection This" "0,1" bitfld.long 0x8 0. "DTEN,Data transfer enable bit This bit can" "0,1" rgroup.long 0x30++0x7 line.long 0x0 "SDMMC_DCNTR,The SDMMC_DCNTR register loads the value" hexmask.long 0x0 0.--24. 1. "DATACOUNT,Data count value When read the number" line.long 0x4 "SDMMC_STAR,The SDMMC_STAR register is a read-only" bitfld.long 0x4 28. "IDMABTC,IDMA buffer transfer complete. interrupt" "0,1" bitfld.long 0x4 27. "IDMATE,IDMA transfer error. Interrupt flag is" "0,1" bitfld.long 0x4 26. "CKSTOP,SDMMC_CK stopped in Voltage switch" "0,1" bitfld.long 0x4 25. "VSWEND,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUT,Boot acknowledgment timeout. Interrupt" "0,1" bitfld.long 0x4 23. "ACKFAIL,Boot acknowledgment received (boot" "0,1" newline bitfld.long 0x4 22. "SDIOIT,SDIO interrupt received. Interrupt flag" "0,1" bitfld.long 0x4 21. "BUSYD0END,end of SDMMC_D0 Busy following a CMD" "0,1" bitfld.long 0x4 20. "BUSYD0,Inverted value of SDMMC_D0 line (Busy) " "0,1" bitfld.long 0x4 19. "RXFIFOE,Receive FIFO empty This is a hardware" "0,1" bitfld.long 0x4 18. "TXFIFOE,Transmit FIFO empty This bit is cleared" "0,1" bitfld.long 0x4 17. "RXFIFOF,Receive FIFO full This bit is cleared" "0,1" newline bitfld.long 0x4 16. "TXFIFOF,Transmit FIFO full This is a hardware" "0,1" bitfld.long 0x4 15. "RXFIFOHF,Receive FIFO half full There are at" "0,1" bitfld.long 0x4 14. "TXFIFOHE,Transmit FIFO half empty At least half" "0,1" bitfld.long 0x4 13. "CPSMACT,Command path state machine active i.e." "0,1" bitfld.long 0x4 12. "DPSMACT,Data path state machine active i.e. not" "0,1" bitfld.long 0x4 11. "DABORT,Data transfer aborted by CMD12." "0,1" newline bitfld.long 0x4 10. "DBCKEND,Data block sent/received. (CRC check" "0,1" bitfld.long 0x4 9. "DHOLD,Data transfer Hold. Interrupt flag is" "0,1" bitfld.long 0x4 8. "DATAEND,Data transfer ended correctly. (data" "0,1" bitfld.long 0x4 7. "CMDSENT,Command sent (no response required)." "0,1" bitfld.long 0x4 6. "CMDREND,Command response received (CRC check" "0,1" bitfld.long 0x4 5. "RXOVERR,Received FIFO overrun error or IDMA" "0,1" newline bitfld.long 0x4 4. "TXUNDERR,Transmit FIFO underrun error or IDMA" "0,1" bitfld.long 0x4 3. "DTIMEOUT,Data timeout. Interrupt flag is cleared" "0,1" bitfld.long 0x4 2. "CTIMEOUT,Command response timeout. Interrupt flag" "0,1" bitfld.long 0x4 1. "DCRCFAIL,Data block sent/received (CRC check" "0,1" bitfld.long 0x4 0. "CCRCFAIL,Command response received (CRC check" "0,1" group.long 0x38++0xB line.long 0x0 "SDMMC_ICR,The SDMMC_ICR register is a write-only" bitfld.long 0x0 28. "IDMABTCC,IDMA buffer transfer complete clear bit" "0,1" bitfld.long 0x0 27. "IDMATEC,IDMA transfer error clear bit Set by" "0,1" bitfld.long 0x0 26. "CKSTOPC,CKSTOP flag clear bit Set by software to" "0,1" bitfld.long 0x0 25. "VSWENDC,VSWEND flag clear bit Set by software to" "0,1" bitfld.long 0x0 24. "ACKTIMEOUTC,ACKTIMEOUT flag clear bit Set by" "0,1" bitfld.long 0x0 23. "ACKFAILC,ACKFAIL flag clear bit Set by software" "0,1" newline bitfld.long 0x0 22. "SDIOITC,SDIOIT flag clear bit Set by software to" "0,1" bitfld.long 0x0 21. "BUSYD0ENDC,BUSYD0END flag clear bit Set by software" "0,1" bitfld.long 0x0 11. "DABORTC,DABORT flag clear bit Set by software to" "0,1" bitfld.long 0x0 10. "DBCKENDC,DBCKEND flag clear bit Set by software" "0,1" bitfld.long 0x0 9. "DHOLDC,DHOLD flag clear bit Set by software to" "0,1" bitfld.long 0x0 8. "DATAENDC,DATAEND flag clear bit Set by software" "0,1" newline bitfld.long 0x0 7. "CMDSENTC,CMDSENT flag clear bit Set by software" "0,1" bitfld.long 0x0 6. "CMDRENDC,CMDREND flag clear bit Set by software" "0,1" bitfld.long 0x0 5. "RXOVERRC,RXOVERR flag clear bit Set by software" "0,1" bitfld.long 0x0 4. "TXUNDERRC,TXUNDERR flag clear bit Set by software" "0,1" bitfld.long 0x0 3. "DTIMEOUTC,DTIMEOUT flag clear bit Set by software" "0,1" bitfld.long 0x0 2. "CTIMEOUTC,CTIMEOUT flag clear bit Set by software" "0,1" newline bitfld.long 0x0 1. "DCRCFAILC,DCRCFAIL flag clear bit Set by software" "0,1" bitfld.long 0x0 0. "CCRCFAILC,CCRCFAIL flag clear bit Set by software" "0,1" line.long 0x4 "SDMMC_MASKR,The interrupt mask register determines which" bitfld.long 0x4 28. "IDMABTCIE,IDMA buffer transfer complete interrupt" "0,1" bitfld.long 0x4 26. "CKSTOPIE,Voltage Switch clock stopped interrupt" "0,1" bitfld.long 0x4 25. "VSWENDIE,Voltage switch critical timing section" "0,1" bitfld.long 0x4 24. "ACKTIMEOUTIE,Acknowledgment timeout interrupt enable" "0,1" bitfld.long 0x4 23. "ACKFAILIE,Acknowledgment Fail interrupt enable Set" "0,1" bitfld.long 0x4 22. "SDIOITIE,SDIO mode interrupt received interrupt" "0,1" newline bitfld.long 0x4 21. "BUSYD0ENDIE,BUSYD0END interrupt enable Set and" "0,1" bitfld.long 0x4 18. "TXFIFOEIE,Tx FIFO empty interrupt enable Set and" "0,1" bitfld.long 0x4 17. "RXFIFOFIE,Rx FIFO full interrupt enable Set and" "0,1" bitfld.long 0x4 15. "RXFIFOHFIE,Rx FIFO half full interrupt enable Set" "0,1" bitfld.long 0x4 14. "TXFIFOHEIE,Tx FIFO half empty interrupt enable Set" "0,1" bitfld.long 0x4 11. "DABORTIE,Data transfer aborted interrupt enable" "0,1" newline bitfld.long 0x4 10. "DBCKENDIE,Data block end interrupt enable Set and" "0,1" bitfld.long 0x4 9. "DHOLDIE,Data hold interrupt enable Set and" "0,1" bitfld.long 0x4 8. "DATAENDIE,Data end interrupt enable Set and" "0,1" bitfld.long 0x4 7. "CMDSENTIE,Command sent interrupt enable Set and" "0,1" bitfld.long 0x4 6. "CMDRENDIE,Command response received interrupt" "0,1" bitfld.long 0x4 5. "RXOVERRIE,Rx FIFO overrun error interrupt enable" "0,1" newline bitfld.long 0x4 4. "TXUNDERRIE,Tx FIFO underrun error interrupt enable" "0,1" bitfld.long 0x4 3. "DTIMEOUTIE,Data timeout interrupt enable Set and" "0,1" bitfld.long 0x4 2. "CTIMEOUTIE,Command timeout interrupt enable Set and" "0,1" bitfld.long 0x4 1. "DCRCFAILIE,Data CRC fail interrupt enable Set and" "0,1" bitfld.long 0x4 0. "CCRCFAILIE,Command CRC fail interrupt enable Set" "0,1" line.long 0x8 "SDMMC_ACKTIMER,The SDMMC_ACKTIMER register contains the" hexmask.long 0x8 0.--24. 1. "ACKTIME,Boot acknowledgment timeout period This" group.long 0x50++0xF line.long 0x0 "SDMMC_IDMACTRLR,The receive and transmit FIFOs can be read" bitfld.long 0x0 2. "IDMABACT,Double buffer mode active buffer" "0,1" bitfld.long 0x0 1. "IDMABMODE,Buffer mode selection. This bit can only" "0,1" bitfld.long 0x0 0. "IDMAEN,IDMA enable This bit can only be written" "0,1" line.long 0x4 "SDMMC_IDMABSIZER,The SDMMC_IDMABSIZER register contains the" hexmask.long.byte 0x4 5.--12. 1. "IDMABNDT,Number of transfers per buffer. This" line.long 0x8 "SDMMC_IDMABASE0R,The SDMMC_IDMABASE0R register contains the" hexmask.long 0x8 0.--31. 1. "IDMABASE0,Buffer 0 memory base address bits" line.long 0xC "SDMMC_IDMABASE1R,The SDMMC_IDMABASE1R register contains the" hexmask.long 0xC 0.--31. 1. "IDMABASE1,Buffer 1 memory base address shall be" group.long 0x80++0x3 line.long 0x0 "SDMMC_FIFOR,The receive and transmit FIFOs can be only" hexmask.long 0x0 0.--31. 1. "FIFODATA,Receive and transmit FIFO data This" rgroup.long 0x3F4++0x7 line.long 0x0 "SDMMC_VER,SDMMC IP version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,IP major revision number." hexmask.long.byte 0x0 0.--3. 1. "MINREV,IP minor revision number." line.long 0x4 "SDMMC_ID,SDMMC IP identification" hexmask.long 0x4 0.--31. 1. "IP_ID,SDMMC IP identification." rgroup.long 0x10++0x3 line.long 0x0 "SDMMC_RESPCMDR,SDMMC command response" hexmask.long.byte 0x0 0.--5. 1. "RESPCMD,Response command index" tree.end endif tree.end tree "SPDIFRX (SPDIFRX Receiver Interface)" base ad:0x40004000 group.long 0x0++0x7 line.long 0x0 "CR,Control register" bitfld.long 0x0 21. "CKSBKPEN,Backup Symbol Clock Enable" "0,1" bitfld.long 0x0 20. "CKSEN,Symbol Clock Enable" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 16.--18. "INSEL,input selection" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 16.--19. 1. "INSEL,input selection" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 16.--19. 1. "INSEL,input selection" endif bitfld.long 0x0 14. "WFA,Wait For Activity" "0,1" bitfld.long 0x0 12.--13. "NBTR,Maximum allowed re-tries during" "0,1,2,3" bitfld.long 0x0 11. "CHSEL,Channel Selection" "0,1" bitfld.long 0x0 10. "CBDMAEN,Control Buffer DMA ENable for control" "0,1" bitfld.long 0x0 9. "PTMSK,Mask of Preamble Type bits" "0,1" newline bitfld.long 0x0 8. "CUMSK,Mask of channel status and user" "0,1" bitfld.long 0x0 7. "VMSK,Mask of Validity bit" "0,1" bitfld.long 0x0 6. "PMSK,Mask Parity error bit" "0,1" bitfld.long 0x0 4.--5. "DRFMT,RX Data format" "0,1,2,3" bitfld.long 0x0 3. "RXSTEO,STerEO Mode" "0,1" bitfld.long 0x0 2. "RXDMAEN,Receiver DMA ENable for data" "0,1" bitfld.long 0x0 0.--1. "SPDIFRXEN,Peripheral Block Enable" "0,1,2,3" line.long 0x4 "IMR,Interrupt mask register" bitfld.long 0x4 6. "IFEIE,Serial Interface Error Interrupt" "0,1" bitfld.long 0x4 5. "SYNCDIE,Synchronization Done" "0,1" bitfld.long 0x4 4. "SBLKIE,Synchronization Block Detected Interrupt" "0,1" bitfld.long 0x4 3. "OVRIE,Overrun error Interrupt" "0,1" bitfld.long 0x4 2. "PERRIE,Parity error interrupt" "0,1" bitfld.long 0x4 1. "CSRNEIE,Control Buffer Ready Interrupt" "0,1" bitfld.long 0x4 0. "RXNEIE,RXNE interrupt enable" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "SR,Status register" hexmask.long.word 0x0 16.--30. 1. "WIDTH5,Duration of 5 symbols counted with" bitfld.long 0x0 8. "TERR,Time-out error" "0,1" bitfld.long 0x0 7. "SERR,Synchronization error" "0,1" bitfld.long 0x0 6. "FERR,Framing error" "0,1" bitfld.long 0x0 5. "SYNCD,Synchronization Done" "0,1" bitfld.long 0x0 4. "SBD,Synchronization Block" "0,1" bitfld.long 0x0 3. "OVR,Overrun error" "0,1" bitfld.long 0x0 2. "PERR,Parity error" "0,1" bitfld.long 0x0 1. "CSRNE,Control Buffer register is not" "0,1" bitfld.long 0x0 0. "RXNE,Read data register not" "0,1" wgroup.long 0xC++0x3 line.long 0x0 "IFCR,Interrupt Flag Clear register" bitfld.long 0x0 5. "SYNCDCF,Clears the Synchronization Done" "0,1" bitfld.long 0x0 4. "SBDCF,Clears the Synchronization Block" "0,1" bitfld.long 0x0 3. "OVRCF,Clears the Overrun error" "0,1" bitfld.long 0x0 2. "PERRCF,Clears the Parity error" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) rgroup.long 0x10++0x3 line.long 0x0 "FMT0_DR,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" endif sif (cpuis("STM32H742*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" endif sif (cpuis("STM32H742*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H742*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H743*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H743*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H743*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H745??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H745??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H745??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H745??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H745??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H745??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H747??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H747??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H747??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H747??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H747??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H747??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H750*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H750*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H750*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H753*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H753*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H753*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H755??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H755??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H755??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H755??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H755??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H755??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H757??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H757??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H757??-CM4")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H757??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H757??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H757??-CM7")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H7B0*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H7B0*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H7B0*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif sif (cpuis("STM32H7B3*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_00,Data input register" bitfld.long 0x0 28.--29. "PT,Preamble Type" "0,1,2,3" bitfld.long 0x0 27. "C,Channel Status bit" "0,1" newline bitfld.long 0x0 26. "U,User bit" "0,1" bitfld.long 0x0 25. "V,Validity bit" "0,1" newline bitfld.long 0x0 24. "PE,Parity Error bit" "0,1" hexmask.long.tbyte 0x0 0.--23. 1. "DR,Parity Error bit" rgroup.long 0x3F4++0x7 line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" endif sif (cpuis("STM32H7B3*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_01,Data input register" hexmask.long.tbyte 0x0 8.--31. 1. "DR,Data value" bitfld.long 0x0 4.--5. "PT,Preamble Type" "0,1,2,3" newline bitfld.long 0x0 3. "C,Channel Status bit" "0,1" bitfld.long 0x0 2. "U,User bit" "0,1" newline bitfld.long 0x0 1. "V,Validity bit" "0,1" bitfld.long 0x0 0. "PE,Parity Error bit" "0,1" endif sif (cpuis("STM32H7B3*")) rgroup.long 0x10++0x3 line.long 0x0 "DR_10,Data input register" hexmask.long.word 0x0 16.--31. 1. "DRNL2,Data value" hexmask.long.word 0x0 0.--15. 1. "DRNL1,Data value" endif rgroup.long 0x14++0x7 line.long 0x0 "CSR,Channel Status register" bitfld.long 0x0 24. "SOB,Start Of Block" "0,1" hexmask.long.byte 0x0 16.--23. 1. "CS,Channel A status" hexmask.long.word 0x0 0.--15. 1. "USR,User data information" line.long 0x4 "DIR,Debug Information register" hexmask.long.word 0x4 16.--28. 1. "TLO,Threshold LOW" hexmask.long.word 0x4 0.--12. 1. "THI,Threshold HIGH" sif (cpuis("STM32H742*")) rgroup.long 0x3F4++0xB line.long 0x0 "VERR,SPDIFRX version register" hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major revision" hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor revision" line.long 0x4 "IDR,SPDIFRX identification" hexmask.long 0x4 0.--31. 1. "ID,SPDIFRX identifier" line.long 0x8 "SIDR,SPDIFRX size identification" hexmask.long 0x8 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H743*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H745??-CM4")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H745??-CM7")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H747??-CM4")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H747??-CM7")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H750*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H753*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H755??-CM4")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H755??-CM7")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H757??-CM4")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H757??-CM7")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H7A3*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H7B0*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif sif (cpuis("STM32H7B3*")) rgroup.long 0x3FC++0x3 line.long 0x0 "SIDR,SPDIFRX size identification" hexmask.long 0x0 0.--31. 1. "SID,Size identification" endif tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0xF line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x50++0x3 line.long 0x0 "I2SCFGR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif sif (cpuis("STM32H742*")) group.long 0x50++0x3 line.long 0x0 "CGFR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0xF line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x50++0x3 line.long 0x0 "I2SCFGR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif sif (cpuis("STM32H742*")) group.long 0x50++0x3 line.long 0x0 "CGFR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0xF line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x50++0x3 line.long 0x0 "I2SCFGR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif sif (cpuis("STM32H742*")) group.long 0x50++0x3 line.long 0x0 "CGFR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0xF line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x50++0x3 line.long 0x0 "I2SCFGR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif sif (cpuis("STM32H742*")) group.long 0x50++0x3 line.long 0x0 "CGFR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0xF line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x50++0x3 line.long 0x0 "I2SCFGR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif sif (cpuis("STM32H742*")) group.long 0x50++0x3 line.long 0x0 "CGFR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0xF line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x50++0x3 line.long 0x0 "I2SCFGR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif sif (cpuis("STM32H742*")) group.long 0x50++0x3 line.long 0x0 "CGFR,configuration register" bitfld.long 0x0 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x0 24. "ODD,Odd factor for the" "0,1" newline hexmask.long.byte 0x0 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x0 14. "DATFMT,Data format" "0,1" newline bitfld.long 0x0 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x0 12. "FIXCH,Word select inversion" "0,1" newline bitfld.long 0x0 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x0 10. "CHLEN,Channel length (number of bits per audio" "0,1" newline bitfld.long 0x0 8.--9. "DATLEN,Data length to be" "0,1,2,3" bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1" newline bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x0 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "I2SMOD,I2S mode selection" "0,1" endif tree.end endif sif (cpuis("STM32H743*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H743*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H750*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H750*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H753*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H753*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H7A3*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H7A3*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" bitfld.long 0x8 28.--30. "MBR,Master baud rate" "0,1,2,3,4,5,6,7" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline bitfld.long 0xC 19.--21. "SP,Serial Protocol" "0,1,2,3,4,5,6,7" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" bitfld.long 0x10 1.--3. "I2SCFG,I2S configuration mode" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H7B0*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H7B0*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H7B3*")) tree "SPI1" base ad:0x40013000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif sif (cpuis("STM32H7B3*")) tree "SPI2" base ad:0x40003800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI3" base ad:0x40003C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI4" base ad:0x40013400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI5" base ad:0x40015000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end tree "SPI6" base ad:0x58001400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" rbitfld.long 0x0 16. "IOLOCK,Locking the AF configuration of" "0,1" bitfld.long 0x0 15. "TCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 14. "RCRCI,CRC calculation initialization pattern" "0,1" bitfld.long 0x0 13. "CRC33_17,32-bit CRC polynomial" "0,1" bitfld.long 0x0 12. "SSI,Internal SS signal input" "0,1" bitfld.long 0x0 11. "HDDIR,Rx/Tx direction at Half-duplex" "0,1" bitfld.long 0x0 10. "CSUSP,Master SUSPend request" "0,1" rbitfld.long 0x0 9. "CSTART,Master transfer start" "0,1" bitfld.long 0x0 8. "MASRX,Master automatic SUSP in Receive" "0,1" newline bitfld.long 0x0 0. "SPE,Serial Peripheral Enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.word 0x4 16.--31. 1. "TSER,Number of data transfer extension to be" hexmask.long.word 0x4 0.--15. 1. "TSIZE,Number of data at current" line.long 0x8 "CFG1,configuration register 1" hexmask.long.byte 0x8 28.--31. 1. "MBR,Master baud rate" bitfld.long 0x8 22. "CRCEN,Hardware CRC computation" "0,1" hexmask.long.byte 0x8 16.--20. 1. "CRCSIZE,Length of CRC frame to be transacted and" bitfld.long 0x8 15. "TXDMAEN,Tx DMA stream enable" "0,1" bitfld.long 0x8 14. "RXDMAEN,Rx DMA stream enable" "0,1" bitfld.long 0x8 11.--12. "UDRDET,Detection of underrun condition at slave" "0,1,2,3" bitfld.long 0x8 9.--10. "UDRCFG,Behavior of slave transmitter at" "0,1,2,3" hexmask.long.byte 0x8 5.--8. 1. "FTHVL,threshold level" hexmask.long.byte 0x8 0.--4. 1. "DSIZE,Number of bits in at single SPI data" line.long 0xC "CFG2,configuration register 2" bitfld.long 0xC 31. "AFCNTR,Alternate function GPIOs" "0,1" bitfld.long 0xC 30. "SSOM,SS output management in master" "0,1" bitfld.long 0xC 29. "SSOE,SS output enable" "0,1" bitfld.long 0xC 28. "SSIOP,SS input/output polarity" "0,1" bitfld.long 0xC 26. "SSM,Software management of SS signal" "0,1" bitfld.long 0xC 25. "CPOL,Clock polarity" "0,1" bitfld.long 0xC 24. "CPHA,Clock phase" "0,1" bitfld.long 0xC 23. "LSBFRST,Data frame format" "0,1" bitfld.long 0xC 22. "MASTER,SPI Master" "0,1" newline hexmask.long.byte 0xC 19.--22. 1. "SP,Serial Protocol" bitfld.long 0xC 17.--18. "COMM,SPI Communication Mode" "0,1,2,3" bitfld.long 0xC 15. "IOSWP,Swap functionality of MISO and MOSI" "0,1" hexmask.long.byte 0xC 4.--7. 1. "MIDI,Master Inter-Data Idleness" hexmask.long.byte 0xC 0.--3. 1. "MSSI,Master SS Idleness" line.long 0x10 "IER,Interrupt Enable Register" bitfld.long 0x10 10. "TSERFIE,Additional number of transactions reload" "0,1" bitfld.long 0x10 9. "MODFIE,Mode Fault interrupt" "0,1" bitfld.long 0x10 8. "TIFREIE,TIFRE interrupt enable" "0,1" bitfld.long 0x10 7. "CRCEIE,CRC Interrupt enable" "0,1" bitfld.long 0x10 6. "OVRIE,OVR interrupt enable" "0,1" bitfld.long 0x10 5. "UDRIE,UDR interrupt enable" "0,1" bitfld.long 0x10 4. "TXTFIE,TXTFIE interrupt enable" "0,1" bitfld.long 0x10 3. "EOTIE,EOT SUSP and TXC interrupt" "0,1" rbitfld.long 0x10 2. "DPXPIE,DXP interrupt enabled" "0,1" newline rbitfld.long 0x10 1. "TXPIE,TXP interrupt enable" "0,1" bitfld.long 0x10 0. "RXPIE,RXP Interrupt Enable" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SR,Status Register" hexmask.long.word 0x0 16.--31. 1. "CTSIZE,Number of data frames remaining in" bitfld.long 0x0 15. "RXWNE,RxFIFO Word Not Empty" "0,1" bitfld.long 0x0 13.--14. "RXPLVL,RxFIFO Packing LeVeL" "0,1,2,3" bitfld.long 0x0 12. "TXC,TxFIFO transmission" "0,1" bitfld.long 0x0 11. "SUSP,SUSPend" "0,1" bitfld.long 0x0 10. "TSERF,Additional number of SPI data to be" "0,1" bitfld.long 0x0 9. "MODF,Mode Fault" "0,1" bitfld.long 0x0 8. "TIFRE,TI frame format error" "0,1" bitfld.long 0x0 7. "CRCE,CRC Error" "0,1" newline bitfld.long 0x0 6. "OVR,Overrun" "0,1" bitfld.long 0x0 5. "UDR,Underrun at slave transmission" "0,1" bitfld.long 0x0 4. "TXTF,Transmission Transfer" "0,1" bitfld.long 0x0 3. "EOT,End Of Transfer" "0,1" bitfld.long 0x0 2. "DXP,Duplex Packet" "0,1" bitfld.long 0x0 1. "TXP,Tx-Packet space available" "0,1" bitfld.long 0x0 0. "RXP,Rx-Packet available" "0,1" wgroup.long 0x18++0x3 line.long 0x0 "IFCR,Interrupt/Status Flags Clear" bitfld.long 0x0 11. "SUSPC,SUSPend flag clear" "0,1" bitfld.long 0x0 10. "TSERFC,TSERFC flag clear" "0,1" bitfld.long 0x0 9. "MODFC,Mode Fault flag clear" "0,1" bitfld.long 0x0 8. "TIFREC,TI frame format error flag" "0,1" bitfld.long 0x0 7. "CRCEC,CRC Error flag clear" "0,1" bitfld.long 0x0 6. "OVRC,Overrun flag clear" "0,1" bitfld.long 0x0 5. "UDRC,Underrun flag clear" "0,1" bitfld.long 0x0 4. "TXTFC,Transmission Transfer Filled flag" "0,1" bitfld.long 0x0 3. "EOTC,End Of Transfer flag clear" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "TXDR,Transmit Data Register" hexmask.long 0x0 0.--31. 1. "TXDR,Transmit data register" rgroup.long 0x30++0x3 line.long 0x0 "RXDR,Receive Data Register" hexmask.long 0x0 0.--31. 1. "RXDR,Receive data register" group.long 0x40++0x13 line.long 0x0 "CRCPOLY,Polynomial Register" hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC polynomial register" line.long 0x4 "TXCRC,Transmitter CRC Register" hexmask.long 0x4 0.--31. 1. "TXCRC,CRC register for" line.long 0x8 "RXCRC,Receiver CRC Register" hexmask.long 0x8 0.--31. 1. "RXCRC,CRC register for receiver" line.long 0xC "UDRDR,Underrun Data Register" hexmask.long 0xC 0.--31. 1. "UDRDR,Data at slave underrun" line.long 0x10 "CGFR,configuration register" bitfld.long 0x10 25. "MCKOE,Master clock output enable" "0,1" bitfld.long 0x10 24. "ODD,Odd factor for the" "0,1" hexmask.long.byte 0x10 16.--23. 1. "I2SDIV,I2S linear prescaler" bitfld.long 0x10 14. "DATFMT,Data format" "0,1" bitfld.long 0x10 13. "WSINV,Fixed channel length in" "0,1" bitfld.long 0x10 12. "FIXCH,Word select inversion" "0,1" bitfld.long 0x10 11. "CKPOL,Serial audio clock" "0,1" bitfld.long 0x10 10. "CHLEN,Channel length (number of bits per audio" "0,1" bitfld.long 0x10 8.--9. "DATLEN,Data length to be" "0,1,2,3" newline bitfld.long 0x10 7. "PCMSYNC,PCM frame synchronization" "0,1" bitfld.long 0x10 4.--5. "I2SSTD,I2S standard selection" "0,1,2,3" hexmask.long.byte 0x10 1.--4. 1. "I2SCFG,I2S configuration mode" bitfld.long 0x10 0. "I2SMOD,I2S mode selection" "0,1" tree.end endif tree.end tree "SWPMI (Single Wire Protocol Master interface)" base ad:0x40008800 group.long 0x0++0x7 line.long 0x0 "CR,SWPMI Configuration/Control" bitfld.long 0x0 11. "SWPTEN,Single wire protocol master transceiver" "0,1" bitfld.long 0x0 10. "DEACT,Single wire protocol master interface" "0,1" bitfld.long 0x0 5. "SWPACT,Single wire protocol master interface" "0,1" bitfld.long 0x0 4. "LPBK,Loopback mode enable" "0,1" bitfld.long 0x0 3. "TXMODE,Transmission buffering" "0,1" bitfld.long 0x0 2. "RXMODE,Reception buffering mode" "0,1" bitfld.long 0x0 1. "TXDMA,Transmission DMA enable" "0,1" bitfld.long 0x0 0. "RXDMA,Reception DMA enable" "0,1" line.long 0x4 "BRR,SWPMI Bitrate register" hexmask.long.byte 0x4 0.--7. 1. "BR,Bitrate prescaler" rgroup.long 0xC++0x3 line.long 0x0 "ISR,SWPMI Interrupt and Status" bitfld.long 0x0 11. "RDYF,transceiver ready flag" "0,1" bitfld.long 0x0 10. "DEACTF,DEACTIVATED flag" "0,1" bitfld.long 0x0 9. "SUSP,SUSPEND flag" "0,1" bitfld.long 0x0 8. "SRF,Slave resume flag" "0,1" bitfld.long 0x0 7. "TCF,Transfer complete flag" "0,1" bitfld.long 0x0 6. "TXE,Transmit data register" "0,1" bitfld.long 0x0 5. "RXNE,Receive data register not" "0,1" bitfld.long 0x0 4. "TXUNRF,Transmit underrun error" "0,1" bitfld.long 0x0 3. "RXOVRF,Receive overrun error flag" "0,1" bitfld.long 0x0 2. "RXBERF,Receive CRC error flag" "0,1" newline bitfld.long 0x0 1. "TXBEF,Transmit buffer empty flag" "0,1" bitfld.long 0x0 0. "RXBFF,Receive buffer full flag" "0,1" wgroup.long 0x10++0x3 line.long 0x0 "ICR,SWPMI Interrupt Flag Clear" bitfld.long 0x0 11. "CRDYF,Clear transceiver ready" "0,1" bitfld.long 0x0 8. "CSRF,Clear slave resume flag" "0,1" bitfld.long 0x0 7. "CTCF,Clear transfer complete" "0,1" bitfld.long 0x0 4. "CTXUNRF,Clear transmit underrun error" "0,1" bitfld.long 0x0 3. "CRXOVRF,Clear receive overrun error" "0,1" bitfld.long 0x0 2. "CRXBERF,Clear receive CRC error" "0,1" bitfld.long 0x0 1. "CTXBEF,Clear transmit buffer empty" "0,1" bitfld.long 0x0 0. "CRXBFF,Clear receive buffer full" "0,1" group.long 0x14++0x3 line.long 0x0 "IER,SWPMI Interrupt Enable" bitfld.long 0x0 11. "RDYIE,Transceiver ready interrupt" "0,1" bitfld.long 0x0 8. "SRIE,Slave resume interrupt" "0,1" bitfld.long 0x0 7. "TCIE,Transmit complete interrupt" "0,1" bitfld.long 0x0 6. "TIE,Transmit interrupt enable" "0,1" bitfld.long 0x0 5. "RIE,Receive interrupt enable" "0,1" bitfld.long 0x0 4. "TXUNRIE,Transmit underrun error interrupt" "0,1" bitfld.long 0x0 3. "RXOVRIE,Receive overrun error interrupt" "0,1" bitfld.long 0x0 2. "RXBERIE,Receive CRC error interrupt" "0,1" bitfld.long 0x0 1. "TXBEIE,Transmit buffer empty interrupt" "0,1" bitfld.long 0x0 0. "RXBFIE,Receive buffer full interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "RFL,SWPMI Receive Frame Length" hexmask.long.byte 0x0 0.--4. 1. "RFL,Receive frame length" wgroup.long 0x1C++0x3 line.long 0x0 "TDR,SWPMI Transmit data register" hexmask.long 0x0 0.--31. 1. "TD,Transmit data" rgroup.long 0x20++0x3 line.long 0x0 "RDR,SWPMI Receive data register" hexmask.long 0x0 0.--31. 1. "RD,received data" group.long 0x24++0x3 line.long 0x0 "OR,SWPMI Option register" bitfld.long 0x0 1. "SWP_CLASS,SWP class selection" "0,1" bitfld.long 0x0 0. "SWP_TBYP,SWP transceiver bypass" "0,1" tree.end tree "SYSCFG (System Configuration Controller)" base ad:0x58000400 group.long 0x4++0x13 line.long 0x0 "PMCR,peripheral mode configuration" bitfld.long 0x0 27. "PC3SO,PC3 Switch Open" "0,1" bitfld.long 0x0 26. "PC2SO,PC2 Switch Open" "0,1" bitfld.long 0x0 25. "PA1SO,PA1 Switch Open" "0,1" bitfld.long 0x0 24. "PA0SO,PA0 Switch Open" "0,1" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x0 21.--23. "EPIS,Ethernet PHY Interface" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 21.--24. 1. "EPIS,Ethernet PHY Interface" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 21.--24. 1. "EPIS,Ethernet PHY Interface" endif sif (cpuis("STM32H742*")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H743*")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" newline endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 9. "BOOSTVDDSEL,Analog switch supply voltage selection" "0,1" newline endif bitfld.long 0x0 8. "BOOSTE,Booster Enable" "0,1" bitfld.long 0x0 7. "PB9FMP,PB(9) Fm+" "0,1" bitfld.long 0x0 6. "PB8FMP,PB(8) Fast Mode Plus" "0,1" bitfld.long 0x0 5. "PB7FMP,PB(7) Fast Mode Plus" "0,1" bitfld.long 0x0 4. "PB6FMP,PB(6) Fm+" "0,1" bitfld.long 0x0 3. "I2C4FMP,I2C4 Fm+" "0,1" bitfld.long 0x0 2. "I2C3FMP,I2C3 Fm+" "0,1" newline bitfld.long 0x0 1. "I2C2FMP,I2C2 Fm+" "0,1" bitfld.long 0x0 0. "I2C1FMP,I2C1 Fm+" "0,1" line.long 0x4 "EXTICR1,external interrupt configuration register" hexmask.long.byte 0x4 12.--15. 1. "EXTI3,EXTI x configuration (x = 0 to" hexmask.long.byte 0x4 8.--11. 1. "EXTI2,EXTI x configuration (x = 0 to" hexmask.long.byte 0x4 4.--7. 1. "EXTI1,EXTI x configuration (x = 0 to" hexmask.long.byte 0x4 0.--3. 1. "EXTI0,EXTI x configuration (x = 0 to" line.long 0x8 "EXTICR2,external interrupt configuration register" hexmask.long.byte 0x8 12.--15. 1. "EXTI7,EXTI x configuration (x = 4 to" hexmask.long.byte 0x8 8.--11. 1. "EXTI6,EXTI x configuration (x = 4 to" hexmask.long.byte 0x8 4.--7. 1. "EXTI5,EXTI x configuration (x = 4 to" hexmask.long.byte 0x8 0.--3. 1. "EXTI4,EXTI x configuration (x = 4 to" line.long 0xC "EXTICR3,external interrupt configuration register" hexmask.long.byte 0xC 12.--15. 1. "EXTI11,EXTI x configuration (x = 8 to" hexmask.long.byte 0xC 8.--11. 1. "EXTI10,EXTI10" hexmask.long.byte 0xC 4.--7. 1. "EXTI9,EXTI x configuration (x = 8 to" hexmask.long.byte 0xC 0.--3. 1. "EXTI8,EXTI x configuration (x = 8 to" line.long 0x10 "EXTICR4,external interrupt configuration register" hexmask.long.byte 0x10 12.--15. 1. "EXTI15,EXTI x configuration (x = 12 to" hexmask.long.byte 0x10 8.--11. 1. "EXTI14,EXTI x configuration (x = 12 to" hexmask.long.byte 0x10 4.--7. 1. "EXTI13,EXTI x configuration (x = 12 to" hexmask.long.byte 0x10 0.--3. 1. "EXTI12,EXTI x configuration (x = 12 to" sif (cpuis("STM32H745??-CM4")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif sif (cpuis("STM32H745??-CM7")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif sif (cpuis("STM32H747??-CM4")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif sif (cpuis("STM32H747??-CM7")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif sif (cpuis("STM32H755??-CM4")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif sif (cpuis("STM32H755??-CM7")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif sif (cpuis("STM32H757??-CM4")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif sif (cpuis("STM32H757??-CM7")) group.long 0x18++0x3 line.long 0x0 "CFGR,configuration register" bitfld.long 0x0 15. "AXISRAML,AXISRAML" "0,1" bitfld.long 0x0 14. "ITCML,ITCML" "0,1" newline bitfld.long 0x0 13. "DTCML,DTCML" "0,1" bitfld.long 0x0 12. "SRAM1L,SRAM1L" "0,1" newline bitfld.long 0x0 11. "SRAM2L,SRAM2L" "0,1" bitfld.long 0x0 10. "SRAM3L,SRAM3L" "0,1" newline bitfld.long 0x0 9. "SRAM4L,SRAM4L" "0,1" bitfld.long 0x0 7. "BKRAML,BKRAML" "0,1" newline bitfld.long 0x0 6. "CM7L,CM7L" "0,1" bitfld.long 0x0 3. "FLASHL,FLASHL" "0,1" newline bitfld.long 0x0 2. "PVDL,PVDL" "0,1" bitfld.long 0x0 0. "CM4L,CM4L" "0,1" group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" bitfld.long 0x0 0. "ODEN,Overdrive enable" "0,1" group.long 0x304++0x3 line.long 0x0 "UR1,SYSCFG user register 1" bitfld.long 0x0 16. "BCM7,Boot Cortex-M7" "0,1" bitfld.long 0x0 0. "BCM4,Boot Cortex-M4" "0,1" endif group.long 0x20++0x3 line.long 0x0 "CCCSR,compensation cell control/status" bitfld.long 0x0 16. "HSLV,High-speed at low-voltage" "0,1" bitfld.long 0x0 8. "READY,Compensation cell ready" "0,1" bitfld.long 0x0 1. "CS,Code selection" "0,1" bitfld.long 0x0 0. "EN,enable" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "CCVR,SYSCFG compensation cell value" hexmask.long.byte 0x0 4.--7. 1. "PCV,PMOS compensation value" hexmask.long.byte 0x0 0.--3. 1. "NCV,NMOS compensation value" group.long 0x28++0x3 line.long 0x0 "CCCR,SYSCFG compensation cell code" hexmask.long.byte 0x0 4.--7. 1. "PCC,PMOS compensation code" hexmask.long.byte 0x0 0.--3. 1. "NCC,NMOS compensation code" sif (cpuis("STM32H742*")) group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" hexmask.long.byte 0x0 0.--3. 1. "ODEN,Overdrive enable" endif sif (cpuis("STM32H743*")) group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" hexmask.long.byte 0x0 0.--3. 1. "ODEN,Overdrive enable" endif sif (cpuis("STM32H753*")) group.long 0x2C++0x3 line.long 0x0 "PWRCR,SYSCFG power control register" hexmask.long.byte 0x0 0.--3. 1. "ODEN,Overdrive enable" endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) rgroup.long 0x124++0x3 line.long 0x0 "PKGR,SYSCFG package register" hexmask.long.byte 0x0 0.--3. 1. "PKG,Package" rgroup.long 0x300++0x3 line.long 0x0 "UR0,SYSCFG user register 0" hexmask.long.byte 0x0 16.--23. 1. "RDP,Readout protection" bitfld.long 0x0 0. "BKS,Bank Swap" "0,1" group.long 0x308++0x7 line.long 0x0 "UR2,SYSCFG user register 2" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD0,Boot Address 0" bitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" newline endif sif (cpuis("STM32H750*")) hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD0,Boot Address 0" endif sif (cpuis("STM32H753*")) hexmask.long.word 0x0 16.--31. 1. "BOOT_ADD0,Boot Address 0" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.word 0x0 16.--31. 1. "BCM7_ADD0,Cortex-M7 Boot Address 0" newline endif sif (cpuis("STM32H745??-CM4")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" endif sif (cpuis("STM32H745??-CM7")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" newline endif sif (cpuis("STM32H747??-CM4")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" endif sif (cpuis("STM32H747??-CM7")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" newline endif sif (cpuis("STM32H750*")) bitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" endif sif (cpuis("STM32H753*")) bitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" newline endif sif (cpuis("STM32H755??-CM4")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" endif sif (cpuis("STM32H755??-CM7")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" newline endif sif (cpuis("STM32H757??-CM4")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" endif sif (cpuis("STM32H757??-CM7")) rbitfld.long 0x0 0.--1. "BORH,BOR_LVL Brownout Reset Threshold" "0,1,2,3" endif line.long 0x4 "UR3,SYSCFG user register 3" sif (cpuis("STM32H745??-CM4")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" newline endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot Address 1" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" newline hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" endif sif (cpuis("STM32H747??-CM4")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" newline hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" newline hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" endif sif (cpuis("STM32H750*")) hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot Address 1" newline endif sif (cpuis("STM32H753*")) hexmask.long.word 0x4 16.--31. 1. "BOOT_ADD1,Boot Address 1" endif sif (cpuis("STM32H755??-CM4")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" newline hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" newline hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" endif sif (cpuis("STM32H757??-CM4")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" newline hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.word 0x4 16.--31. 1. "BCM7_ADD1,Cortex-M7 Boot Address 1" newline hexmask.long.word 0x4 0.--15. 1. "BCM4_ADD1,Cortex-M4 Boot Address 0" endif rgroup.long 0x310++0x27 line.long 0x0 "UR4,SYSCFG user register 4" sif (cpuis("STM32H745??-CM4")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" newline endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x0 16. "MEPAD_1,Mass Erase Protected Area Disabled for" "0,1" endif sif (cpuis("STM32H745??-CM7")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" endif sif (cpuis("STM32H747??-CM4")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" endif sif (cpuis("STM32H747??-CM7")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 16. "MEPAD_1,Mass Erase Protected Area Disabled for" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 16. "MEPAD_1,Mass Erase Protected Area Disabled for" "0,1" endif sif (cpuis("STM32H755??-CM4")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" endif sif (cpuis("STM32H755??-CM7")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" endif sif (cpuis("STM32H757??-CM4")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" endif sif (cpuis("STM32H757??-CM7")) rbitfld.long 0x0 16. "MEPAD_1,Boot Cortex-M4 Address 1" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "BCM4_ADD1,Mass Erase Protected Area Disabled for" endif line.long 0x4 "UR5,SYSCFG user register 5" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x4 16.--23. 1. "WRPN_1,Write protection for flash bank" endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" newline endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" newline endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x4 16.--23. 1. "WRPN_1,Write protection for flash bank" newline endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x4 16.--23. 1. "WRPN_1,Write protection for flash bank" endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" newline endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" newline endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x4 16.--23. 1. "WRPS_1,Write protection for flash bank" endif bitfld.long 0x4 0. "MESAD_1,Mass erase secured area disabled for" "0,1" line.long 0x8 "UR6,SYSCFG user register 6" hexmask.long.word 0x8 16.--27. 1. "PA_END_1,Protected area end address for bank" hexmask.long.word 0x8 0.--11. 1. "PA_BEG_1,Protected area start address for bank" line.long 0xC "UR7,SYSCFG user register 7" hexmask.long.word 0xC 16.--27. 1. "SA_END_1,Secured area end address for bank" hexmask.long.word 0xC 0.--11. 1. "SA_BEG_1,Secured area start address for bank" line.long 0x10 "UR8,SYSCFG user register 8" bitfld.long 0x10 16. "MESAD_2,Mass erase secured area disabled for" "0,1" bitfld.long 0x10 0. "MEPAD_2,Mass erase protected area disabled for" "0,1" line.long 0x14 "UR9,SYSCFG user register 9" hexmask.long.word 0x14 16.--27. 1. "PA_BEG_2,Protected area start address for bank" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) hexmask.long.byte 0x14 0.--7. 1. "WRPN_2,Write protection for flash bank" newline endif sif (cpuis("STM32H745??-CM4")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" endif sif (cpuis("STM32H745??-CM7")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" newline endif sif (cpuis("STM32H747??-CM4")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" endif sif (cpuis("STM32H747??-CM7")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" newline endif sif (cpuis("STM32H750*")) hexmask.long.byte 0x14 0.--7. 1. "WRPN_2,Write protection for flash bank" endif sif (cpuis("STM32H753*")) hexmask.long.byte 0x14 0.--7. 1. "WRPN_2,Write protection for flash bank" newline endif sif (cpuis("STM32H755??-CM4")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" endif sif (cpuis("STM32H755??-CM7")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" newline endif sif (cpuis("STM32H757??-CM4")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" endif sif (cpuis("STM32H757??-CM7")) hexmask.long.byte 0x14 0.--7. 1. "WRPS_2,Write protection for flash bank" endif line.long 0x18 "UR10,SYSCFG user register 10" hexmask.long.word 0x18 16.--27. 1. "SA_BEG_2,Secured area start address for bank" hexmask.long.word 0x18 0.--11. 1. "PA_END_2,Protected area end address for bank" line.long 0x1C "UR11,SYSCFG user register 11" bitfld.long 0x1C 16. "IWDG1M,Independent Watchdog 1" "0,1" hexmask.long.word 0x1C 0.--11. 1. "SA_END_2,Secured area end address for bank" line.long 0x20 "UR12,SYSCFG user register 12" bitfld.long 0x20 16. "SECURE,Secure mode" "0,1" sif (cpuis("STM32H745??-CM4")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x20 0. "IWDG2M,Independent Watchdog 2 mode" "0,1" endif line.long 0x24 "UR13,SYSCFG user register 13" bitfld.long 0x24 16. "D1SBRST,D1 Standby reset" "0,1" bitfld.long 0x24 0.--1. "SDRS,Secured DTCM RAM Size" "0,1,2,3" group.long 0x338++0x3 line.long 0x0 "UR14,SYSCFG user register 14" sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" newline endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" newline endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" newline endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 16. "D2SBRST,D2 Standby Reset" "0,1" newline endif bitfld.long 0x0 0. "D1STPRST,D1 Stop Reset" "0,1" rgroup.long 0x33C++0xB line.long 0x0 "UR15,SYSCFG user register 15" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")) bitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" endif sif (cpuis("STM32H745??-CM4")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" endif sif (cpuis("STM32H747??-CM4")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" endif sif (cpuis("STM32H750*")) bitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" newline endif sif (cpuis("STM32H753*")) bitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" endif sif (cpuis("STM32H755??-CM4")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" endif sif (cpuis("STM32H757??-CM4")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) rbitfld.long 0x0 16. "FZIWDGSTB,Freeze independent watchdog in Standby" "0,1" endif sif (cpuis("STM32H745??-CM4")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" newline endif sif (cpuis("STM32H745??-CM7")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" endif sif (cpuis("STM32H747??-CM4")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" newline endif sif (cpuis("STM32H747??-CM7")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" endif sif (cpuis("STM32H755??-CM4")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" newline endif sif (cpuis("STM32H755??-CM7")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" endif sif (cpuis("STM32H757??-CM4")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" newline endif sif (cpuis("STM32H757??-CM7")) bitfld.long 0x0 0. "D2STPRST,D2 Stop Reset" "0,1" endif line.long 0x4 "UR16,SYSCFG user register 16" bitfld.long 0x4 16. "PKP,Private key programmed" "0,1" bitfld.long 0x4 0. "FZIWDGSTP,Freeze independent watchdog in Stop" "0,1" line.long 0x8 "UR17,SYSCFG user register 17" bitfld.long 0x8 0. "IO_HSLV,I/O high speed / low" "0,1" endif sif (cpuis("STM32H745??-CM4")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H745??-CM4")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H745??-CM7")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H745??-CM7")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H747??-CM4")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H747??-CM4")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H747??-CM7")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H747??-CM7")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H755??-CM4")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H755??-CM4")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H755??-CM7")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H755??-CM7")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H757??-CM4")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H757??-CM4")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H757??-CM7")) group.long 0x310++0x3 line.long 0x0 "UR4,SYSCFG user register 4" endif sif (cpuis("STM32H757??-CM7")) group.long 0x33C++0x3 line.long 0x0 "UR15,SYSCFG user register 15" endif sif (cpuis("STM32H7A3*")) group.long 0x118++0x3 line.long 0x0 "SYSCFG_BRK_LOCKUPR,SYSCFG timer break lockup" bitfld.long 0x0 14. "ITCML,ITCM double ECC error signal" "0,1" bitfld.long 0x0 13. "DTCML,D1TCM or D0TCM double ECC error signal" "0,1" newline bitfld.long 0x0 6. "CM7L,Cortex-M7" "0,1" bitfld.long 0x0 3. "FLASHL,Flash double ECC error lock" "0,1" newline bitfld.long 0x0 2. "PVDL,PVD lock enable bit." "0,1" endif sif (cpuis("STM32H7B0*")) group.long 0x118++0x3 line.long 0x0 "SYSCFG_BRK_LOCKUPR,SYSCFG timer break lockup" bitfld.long 0x0 14. "ITCML,ITCM double ECC error signal" "0,1" bitfld.long 0x0 13. "DTCML,D1TCM or D0TCM double ECC error signal" "0,1" newline bitfld.long 0x0 6. "CM7L,Cortex-M7" "0,1" bitfld.long 0x0 3. "FLASHL,Flash double ECC error lock" "0,1" newline bitfld.long 0x0 2. "PVDL,PVD lock enable bit." "0,1" endif sif (cpuis("STM32H7B3*")) group.long 0x118++0x3 line.long 0x0 "SYSCFG_BRK_LOCKUPR,SYSCFG timer break lockup" bitfld.long 0x0 14. "ITCML,ITCM double ECC error signal" "0,1" bitfld.long 0x0 13. "DTCML,D1TCM or D0TCM double ECC error signal" "0,1" newline bitfld.long 0x0 6. "CM7L,Cortex-M7" "0,1" bitfld.long 0x0 3. "FLASHL,Flash double ECC error lock" "0,1" newline bitfld.long 0x0 2. "PVDL,PVD lock enable bit." "0,1" endif tree.end sif (cpuis("STM32H7A3*")||cpuis("STM32H7B0*")||cpuis("STM32H7B3*")) tree "TAMP (Tamper and Backup Registers)" base ad:0x58004400 group.long 0x0++0x7 line.long 0x0 "TAMP_CR1,TAMP control register 1" bitfld.long 0x0 23. "ITAMP8E,Internal tamper 8 enable: monotonic counter overflow" "0: Internal tamper 8 disabled.,1: Internal tamper 8 enabled: a tamper is generated.." bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.." newline bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.." bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.." newline bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.." bitfld.long 0x0 17. "ITAMP2E,Internal tamper 2 enable: Temperature monitoring" "0: Internal tamper 2 disabled.,1: Internal tamper 2 enabled: a tamper is generated.." newline bitfld.long 0x0 16. "ITAMP1E,Internal tamper 1 enable: RTC power domain supply monitoring" "0: Internal tamper 1 disabled.,1: Internal tamper 1 enabled: a tamper is generated.." bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled." newline bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled." bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled." line.long 0x4 "TAMP_CR2,TAMP control register 2" bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 3 input staying low..,1: If TAMPFLT =/= 00 Tamper 3 input staying high.." bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 2 input staying low..,1: If TAMPFLT =/= 00 Tamper 2 input staying high.." newline bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT =/= 00 Tamper 1 input staying low..,1: If TAMPFLT =/= 00 Tamper 1 input staying high.." bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.." newline bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.." bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.." newline bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers.,1: Tamper 3 event does not erase the backup.." bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.." newline bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.." group.long 0xC++0x7 line.long 0x0 "TAMP_FLTCR,TAMP filter control register" bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins." bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles" newline bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.." sif (cpuis("STM32H7A3*")) bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)" newline endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x0 0.--3. 1. "TAMPFREQ,Tamper sampling frequency" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x0 0.--3. 1. "TAMPFREQ,Tamper sampling frequency" endif line.long 0x4 "TAMP_ATCR1,TAMP active tamper control register 1" bitfld.long 0x4 31. "FLTEN,Active tamper filter enable" "0: Active tamper filtering disable,1: Active tamper filtering enable: a tamper event.." bitfld.long 0x4 30. "ATOSHARE,Active tamper output sharing" "0: Each active tamper input TAMP_INi is compared..,1: Each active tamper input TAMP_INi is compared.." newline sif (cpuis("STM32H7A3*")) bitfld.long 0x4 24.--26. "ATPER,Active tamper output change period" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" "0: RTCCLK is selected,1: RTCCLK/2 is selected when (PREDIV_A+1) = 128..,2: RTCCLK/4 is selected when (PREDIV_A+1) = 128..,?,?,?,?,7: RTCCLK/128 is selected when (PREDIV_A+1) = 128.." newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4 24.--27. 1. "ATPER,Active tamper output change period" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x4 24.--27. 1. "ATPER,Active tamper output change period" newline endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4 16.--19. 1. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" endif sif (cpuis("STM32H7B3*")) hexmask.long.byte 0x4 16.--19. 1. "ATCKSEL,Active tamper RTC asynchronous prescaler clock selection" newline endif bitfld.long 0x4 12.--13. "ATOSEL3,Active tamper shared output 3 selection" "0: TAMPOUTSEL3 = TAMP_OUT1,1: TAMPOUTSEL3 = TAMP_OUT2,2: TAMPOUTSEL3 = TAMP_OUT3,?" bitfld.long 0x4 10.--11. "ATOSEL2,Active tamper shared output 2 selection" "0: TAMPOUTSEL2 = TAMP_OUT1,1: TAMPOUTSEL2 = TAMP_OUT2,2: TAMPOUTSEL2 = TAMP_OUT3,?" newline bitfld.long 0x4 8.--9. "ATOSEL1,Active tamper shared output 1 selection" "0: TAMPOUTSEL1 = TAMP_OUT1,1: TAMPOUTSEL1 = TAMP_OUT2,2: TAMPOUTSEL1 = TAMP_OUT3,?" bitfld.long 0x4 2. "TAMP3AM,Tamper 3 active mode" "0: Tamper 3 detection mode is passive.,1: Tamper 3 detection mode is active." newline bitfld.long 0x4 1. "TAMP2AM,Tamper 2 active mode" "0: Tamper 2 detection mode is passive.,1: Tamper 2 detection mode is active." bitfld.long 0x4 0. "TAMP1AM,Tamper 1 active mode" "0: Tamper 1 detection mode is passive.,1: Tamper 1 detection mode is active." wgroup.long 0x14++0x3 line.long 0x0 "TAMP_ATSEEDR,TAMP active tamper seed register" hexmask.long 0x0 0.--31. 1. "SEED,Pseudo-random generator seed value" rgroup.long 0x18++0x3 line.long 0x0 "TAMP_ATOR,TAMP active tamper output register" bitfld.long 0x0 15. "INITS,Active tamper initialization status" "0,1" bitfld.long 0x0 14. "SEEDF,Seed running flag" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "PRNG,Pseudo-random generator value" group.long 0x2C++0x3 line.long 0x0 "TAMP_IER,TAMP interrupt enable register" bitfld.long 0x0 23. "ITAMP8IE,Internal tamper 8 interrupt enable: monotonic counter overflow" "0: Internal tamper 8 interrupt disabled.,1: Internal tamper 8 interrupt enabled." bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled." newline bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled." bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled." newline bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled." bitfld.long 0x0 17. "ITAMP2IE,Internal tamper 2 interrupt enable: Temperature monitoring" "0: Internal tamper 2 interrupt disabled.,1: Internal tamper 2 interrupt enabled." newline bitfld.long 0x0 16. "ITAMP1IE,Internal tamper 1 interrupt enable: RTC power domain supply monitoring" "0: Internal tamper 1 interrupt disabled.,1: Internal tamper 1 interrupt enabled" bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.." newline bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled." bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled." rgroup.long 0x30++0x7 line.long 0x0 "TAMP_SR,TAMP status register" bitfld.long 0x0 23. "ITAMP8F,Monotonic counter overflow tamper flag" "0,1" bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1" newline bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1" bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1" newline bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1" bitfld.long 0x0 17. "ITAMP2F,Temperature monitoring tamper detection flag" "0,1" newline bitfld.long 0x0 16. "ITAMP1F,RTC power domain voltage monitoring tamper detection flag" "0,1" bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1" newline bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1" bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1" line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register" bitfld.long 0x4 23. "ITAMP8MF,Monotonic counter overflow interrupt masked flag" "0,1" bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1" newline bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1" bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1" newline bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1" bitfld.long 0x4 17. "ITAMP2MF,Temperature monitoring tamper interrupt masked flag" "0,1" newline bitfld.long 0x4 16. "ITAMP1MF,RTC power domain voltage monitoring tamper interrupt masked flag" "0,1" bitfld.long 0x4 2. "TAMP3MF,TAMP3 interrupt masked flag" "0,1" newline bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1" bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1" wgroup.long 0x3C++0x3 line.long 0x0 "TAMP_SCR,TAMP status clear register" bitfld.long 0x0 23. "CITAMP8F,Clear ITAMP8 detection flag" "0,1" bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1" newline bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1" bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1" newline bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1" bitfld.long 0x0 17. "CITAMP2F,Clear ITAMP2 detection flag" "0,1" newline bitfld.long 0x0 16. "CITAMP1F,Clear ITAMP1 detection flag" "0,1" bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1" newline bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1" bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "TAMP_COUNTR,TAMP monotonic counter register" hexmask.long 0x0 0.--31. 1. "COUNT,This register is read-only only and is incremented by one when a write access is done to this register. This register cannot roll-over and is frozen when reaching the maximum value." group.long 0x50++0x3 line.long 0x0 "TAMP_CFGR,TAMP configuration register" bitfld.long 0x0 0. "OUT3_RMP,TAMP_OUT3 mapping" "0: TAMP_OUT3 is mapped on PI8,1: TAMP_OUT3 is mapped on PC13" group.long 0x100++0x7F line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register" hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register" hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register" hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0xC "TAMP_BKP3R,TAMP backup 3 register" hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register" hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register" hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register" hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register" hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register" hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x24 "TAMP_BKP9R,TAMP backup 9 register" hexmask.long 0x24 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x28 "TAMP_BKP10R,TAMP backup 10 register" hexmask.long 0x28 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x2C "TAMP_BKP11R,TAMP backup 11 register" hexmask.long 0x2C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x30 "TAMP_BKP12R,TAMP backup 12 register" hexmask.long 0x30 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x34 "TAMP_BKP13R,TAMP backup 13 register" hexmask.long 0x34 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x38 "TAMP_BKP14R,TAMP backup 14 register" hexmask.long 0x38 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x3C "TAMP_BKP15R,TAMP backup 15 register" hexmask.long 0x3C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x40 "TAMP_BKP16R,TAMP backup 16 register" hexmask.long 0x40 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x44 "TAMP_BKP17R,TAMP backup 17 register" hexmask.long 0x44 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x48 "TAMP_BKP18R,TAMP backup 18 register" hexmask.long 0x48 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x4C "TAMP_BKP19R,TAMP backup 19 register" hexmask.long 0x4C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x50 "TAMP_BKP20R,TAMP backup 20 register" hexmask.long 0x50 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x54 "TAMP_BKP21R,TAMP backup 21 register" hexmask.long 0x54 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x58 "TAMP_BKP22R,TAMP backup 22 register" hexmask.long 0x58 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x5C "TAMP_BKP23R,TAMP backup 23 register" hexmask.long 0x5C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x60 "TAMP_BKP24R,TAMP backup 24 register" hexmask.long 0x60 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x64 "TAMP_BKP25R,TAMP backup 25 register" hexmask.long 0x64 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x68 "TAMP_BKP26R,TAMP backup 26 register" hexmask.long 0x68 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x6C "TAMP_BKP27R,TAMP backup 27 register" hexmask.long 0x6C 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x70 "TAMP_BKP28R,TAMP backup 28 register" hexmask.long 0x70 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x74 "TAMP_BKP29R,TAMP backup 29 register" hexmask.long 0x74 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x78 "TAMP_BKP30R,TAMP backup 30 register" hexmask.long 0x78 0.--31. 1. "BKP,The application can write or read data to and from these registers." line.long 0x7C "TAMP_BKP31R,TAMP backup 31 register" hexmask.long 0x7C 0.--31. 1. "BKP,The application can write or read data to and from these registers." tree.end endif tree "TIM (Timers)" base ad:0x0 sif (cpuis("STM32H723*")) tree "TIM15 (General purpose timers)" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM1" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM2" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM6" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM8" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM12" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM23" base ad:0x4000E000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM24" base ad:0x4000E400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM16 (General-purpose-timers)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17 (General-purpose-timers)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H725*")) tree "TIM1" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H725*")) tree "TIM2" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM6" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM8" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H725*")) tree "TIM12" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM23" base ad:0x4000E000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM24" base ad:0x4000E400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM15 (General purpose timers)" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM16 (General-purpose-timers)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17 (General-purpose-timers)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H730*")) tree "TIM1" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H730*")) tree "TIM2" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM6" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM8" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H730*")) tree "TIM12" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM23" base ad:0x4000E000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM24" base ad:0x4000E400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM15 (General purpose timers)" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM16 (General-purpose-timers)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17 (General-purpose-timers)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H733*")) tree "TIM1" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H733*")) tree "TIM2" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM6" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM8" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H733*")) tree "TIM12" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM23" base ad:0x4000E000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM24" base ad:0x4000E400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM15 (General purpose timers)" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM16 (General-purpose-timers)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17 (General-purpose-timers)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H735*")) tree "TIM1" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H735*")) tree "TIM2" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM6" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM8" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H735*")) tree "TIM12" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM23" base ad:0x4000E000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM24" base ad:0x4000E400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM15 (General purpose timers)" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM16 (General-purpose-timers)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17 (General-purpose-timers)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H742*")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H742*")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H742*")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H742*")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H742*")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H743*")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H743*")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H743*")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H743*")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H743*")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H750*")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H750*")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H750*")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H750*")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H750*")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H753*")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H753*")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H753*")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H753*")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "O24CE,O24CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H753*")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H7A3*")) tree "TIM1" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7A3*")) tree "TIM2" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM6" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM8" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CRR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7A3*")) tree "TIM12" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" bitfld.long 0x0 12.--14. "OC2M,OC2M" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" bitfld.long 0x4 12.--14. "OC4M,OC4M" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" bitfld.long 0x4 4.--6. "OC3M,OC3M" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM15 (General purpose timers)" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" bitfld.long 0x8 4.--6. "TS_2_0,Trigger selection" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM16 (General-purpose-timers)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17 (General-purpose-timers)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7B0*")) tree "TIM16" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7B0*")) tree "TIM15" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS_2_0,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,Output Compare 2 mode" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7B0*")) tree "TIM1 (Advanced-timers)" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" newline hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,Output Compare 2 mode" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,Output compare 4 mode" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "OC3M,Output compare 3 mode" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC6M,Output compare 6 mode" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC5M,Output compare 5 mode" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM8 (Advanced-timers)" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" newline hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,Output Compare 2 mode" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,Output compare 4 mode" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "OC3M,Output compare 3 mode" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC6M,Output compare 6 mode" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC5M,Output compare 5 mode" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CRR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7B0*")) tree "TIM2 (General purpose timers)" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3 (General purpose timers)" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4 (General purpose timers)" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5 (General purpose timers)" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM12 (General purpose timers)" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13 (General purpose timers)" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14 (General purpose timers)" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end endif sif (cpuis("STM32H7B0*")) tree "TIM6 (Basic timers)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7 (Basic timers)" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end endif sif (cpuis("STM32H7B3*")) tree "TIM1" base ad:0x40010000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" newline hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,Output Compare 2 mode" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,Output compare 4 mode" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "OC3M,Output compare 3 mode" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC6M,Output compare 6 mode" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC5M,Output compare 5 mode" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CCR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7B3*")) tree "TIM2" base ad:0x40000000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM3" base ad:0x40000400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM4" base ad:0x40000800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM5" base ad:0x40000C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM6" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM7" base ad:0x40001400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x24++0xB line.long 0x0 "CNT,counter" bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value" line.long 0x4 "PSC,prescaler" hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value" line.long 0x8 "ARR,auto-reload register" hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value" tree.end tree "TIM8" base ad:0x40010400 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" newline bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2" bitfld.long 0x4 18. "OIS6,Output Idle state 6" "0,1" bitfld.long 0x4 16. "OIS5,Output Idle state 5" "0,1" bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1" bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1" bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1" bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" newline bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" newline hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" newline bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1" bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1" bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1" newline bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" newline bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,Output Compare 2 mode" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_4,Output Compare 4 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,Output compare 4 mode" bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1" bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1" bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "OC3M,Output compare 3 mode" bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1" bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1" bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1" bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1" bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1" bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" newline bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" newline bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x8 0.--15. 1. "CNT,counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x30++0x3 line.long 0x0 "RCR,repetition counter register" hexmask.long.byte 0x0 0.--7. 1. "REP,Repetition counter value" group.long 0x44++0x3 line.long 0x0 "BDTR,break and dead-time register" bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0,1" bitfld.long 0x0 24. "BK2E,Break 2 enable" "0,1" hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" newline bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" group.long 0x54++0x17 line.long 0x0 "CCMR3_Output,capture/compare mode register 3 (output" bitfld.long 0x0 24. "OC6M3,Output Compare 6 mode" "0,1" bitfld.long 0x0 16. "OC5M3,Output Compare 5 mode" "0,1" bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC6M,Output compare 6 mode" bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1" bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1" bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC5M,Output compare 5 mode" newline bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1" bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1" line.long 0x4 "CCR5,capture/compare register 5" bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel" "0,1" bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel" "0,1" hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value" line.long 0x8 "CRR6,capture/compare register 6" hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/Compare 6 value" line.long 0xC "AF1,TIM1 alternate function option register" hexmask.long.byte 0xC 14.--17. 1. "ETRSEL,ETR source selection" bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0xC 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1" line.long 0x10 "AF2,TIM1 Alternate function odfsdm1_breakster" bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1" bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarit" "0,1" bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1" bitfld.long 0x10 8. "BK2DF1BK1E,BRK2 dfsdm1_break[1]" "0,1" bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1" bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1" bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable" "0,1" line.long 0x14 "TISEL,TIM1 timer input selection" hexmask.long.byte 0x14 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15]" hexmask.long.byte 0x14 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15]" hexmask.long.byte 0x14 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x14 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif sif (cpuis("STM32H7B3*")) tree "TIM12" base ad:0x40001800 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM13" base ad:0x40001C00 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM14" base ad:0x40002000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3" bitfld.long 0x0 4. "DIR,Direction" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3" bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1" bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1" bitfld.long 0x8 14. "ECE,External clock enable" "0,1" bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3" hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1" bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1" bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1" newline bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1" bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1" bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" newline bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1" bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x0 15. "OC2CE,OC2CE" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,OC2M" bitfld.long 0x0 11. "OC2PE,OC2PE" "0,1" bitfld.long 0x0 10. "OC2FE,OC2FE" "0,1" bitfld.long 0x0 8.--9. "CC2S,CC2S" "0,1,2,3" bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,OC1M" newline bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1" bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1" bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3" group.long 0x18++0x7 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PCS,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output" bitfld.long 0x4 24. "OC4M_3,Output Compare 2 mode - bit" "0,1" bitfld.long 0x4 16. "OC3M_3,Output Compare 1 mode - bit" "0,1" bitfld.long 0x4 15. "OC4CE,OC4CE" "0,1" hexmask.long.byte 0x4 12.--15. 1. "OC4M,OC4M" bitfld.long 0x4 11. "OC4PE,OC4PE" "0,1" bitfld.long 0x4 10. "OC4FE,OC4FE" "0,1" bitfld.long 0x4 8.--9. "CC4S,CC4S" "0,1,2,3" bitfld.long 0x4 7. "OC3CE,OC3CE" "0,1" hexmask.long.byte 0x4 4.--7. 1. "OC3M,OC3M" newline bitfld.long 0x4 3. "OC3PE,OC3PE" "0,1" bitfld.long 0x4 2. "OC3FE,OC3FE" "0,1" bitfld.long 0x4 0.--1. "CC3S,CC3S" "0,1,2,3" group.long 0x1C++0x13 line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input" hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter" bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter" bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3" "0,1,2,3" line.long 0x4 "CCER,capture/compare enable" bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1" bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1" bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1" bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1" bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1" bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1" newline bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x8 "CNT,counter" hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value" hexmask.long.word 0x8 0.--15. 1. "CNT_L,low counter value" line.long 0xC "PSC,prescaler" hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value" line.long 0x10 "ARR,auto-reload register" hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value" hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value" group.long 0x34++0xF line.long 0x0 "CCR1,capture/compare register 1" hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1" hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1" line.long 0x4 "CCR2,capture/compare register 2" hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2" hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2" line.long 0x8 "CCR3,capture/compare register 3" hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value" hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value" line.long 0xC "CCR4,capture/compare register 4" hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value" hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value" group.long 0x48++0x7 line.long 0x0 "DCR,DMA control register" hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address" line.long 0x4 "DMAR,DMA address for full transfer" hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM alternate function option register" hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM timer input selection" hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,TI4[0] to TI4[15] input" hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input" tree.end tree "TIM15 (General purpose timers)" base ad:0x40014000 group.long 0x0++0x13 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1" hexmask.long.byte 0x4 4.--7. 1. "MMS,Master mode selection" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" line.long 0x8 "SMCR,slave mode control register" bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection - bit" "?,?,?,?" bitfld.long 0x8 16. "SMS_3,Slave mode selection bit 3" "0,1" bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1" hexmask.long.byte 0x8 4.--7. 1. "TS_2_0,Trigger selection" hexmask.long.byte 0x8 0.--3. 1. "SMS,Slave mode selection" line.long 0xC "DIER,DMA/Interrupt enable register" bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1" bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1" bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1" bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1" newline bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1" line.long 0x10 "SR,status register" bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1" bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1" bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1" bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 6. "TG,Trigger generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode bit" "0,1" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode bit" "0,1" hexmask.long.byte 0x0 12.--15. 1. "OC2M,Output Compare 2 mode" bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1" bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" newline bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter" bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3" bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x1B line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1" bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1" bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" line.long 0x18 "CCR2,capture/compare register 2" hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "AF1,TIM15 alternate fdfsdm1_breakon register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDF1BK0E,BRK dfsdm1_break[0] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TISEL,TIM15 input selection register" hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15]" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM16 (General-purpose-timers)" base ad:0x40014400 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM16_AF1,TIM16 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM16_TISEL,TIM16 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end tree "TIM17 (General-purpose-timers)" base ad:0x40014800 group.long 0x0++0x7 line.long 0x0 "CR1,control register 1" bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1" bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3" bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1" bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1" bitfld.long 0x0 2. "URS,Update request source" "0,1" bitfld.long 0x0 1. "UDIS,Update disable" "0,1" bitfld.long 0x0 0. "CEN,Counter enable" "0,1" line.long 0x4 "CR2,control register 2" bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1" bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1" bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1" bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1" bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1" group.long 0xC++0x7 line.long 0x0 "DIER,DMA/Interrupt enable register" bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1" bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1" bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1" bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1" bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1" bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1" bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1" line.long 0x4 "SR,status register" bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1" bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1" bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1" bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1" bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "EGR,event generation register" bitfld.long 0x0 7. "BG,Break generation" "0,1" bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1" bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1" bitfld.long 0x0 0. "UG,Update generation" "0,1" group.long 0x18++0x3 line.long 0x0 "CCMR1_Output,capture/compare mode register (output" bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode" "0,1" hexmask.long.byte 0x0 4.--7. 1. "OC1M,Output Compare 1 mode" bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1" bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x18++0x3 line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input" hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter" bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3" bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3" group.long 0x20++0x17 line.long 0x0 "CCER,capture/compare enable" bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1" bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1" bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1" bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1" line.long 0x4 "CNT,counter" rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1" hexmask.long.word 0x4 0.--15. 1. "CNT,counter value" line.long 0x8 "PSC,prescaler" hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value" line.long 0xC "ARR,auto-reload register" hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value" line.long 0x10 "RCR,repetition counter register" hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value" line.long 0x14 "CCR1,capture/compare register 1" hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value" group.long 0x44++0xB line.long 0x0 "BDTR,break and dead-time register" hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter" bitfld.long 0x0 15. "MOE,Main output enable" "0,1" bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1" bitfld.long 0x0 13. "BKP,Break polarity" "0,1" bitfld.long 0x0 12. "BKE,Break enable" "0,1" bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1" bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1" bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3" hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup" line.long 0x4 "DCR,DMA control register" hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length" hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address" line.long 0x8 "DMAR,DMA address for full transfer" hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst" group.long 0x60++0x3 line.long 0x0 "TIM17_AF1,TIM17 alternate function register" bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0,1" bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1" bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1" bitfld.long 0x0 8. "BKDFBK1E,BRK dfsdm1_break[1] enable" "0,1" bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1" bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1" bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1" group.long 0x68++0x3 line.long 0x0 "TIM17_TISEL,TIM17 input selection register" hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15]" tree.end endif tree.end tree "USART (Universal Synchronous Asynchronous Receiver/Transmitter)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "USART1" base ad:0x40011000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "USART3" base ad:0x40004800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "UART4" base ad:0x40004C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "UART5" base ad:0x40005000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "USART6" base ad:0x40011400 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "UART7" base ad:0x40007800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "UART8" base ad:0x40007C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" endif bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" endif bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" newline bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" endif bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" newline bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "UART9" base ad:0x40011800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART10" base ad:0x40011C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H7A3*")) tree "USART9" base ad:0x40011800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART10" base ad:0x40011C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H7B0*")) tree "USART9" base ad:0x40011800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART10" base ad:0x40011C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H7B3*")) tree "UART4" base ad:0x40004C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "UART5" base ad:0x40005000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "UART7" base ad:0x40007800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "UART8" base ad:0x40007C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART1" base ad:0x40011000 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif sif (cpuis("STM32H7B3*")) tree "USART2" base ad:0x40004400 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART3" base ad:0x40004800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART6" base ad:0x40011400 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART9" base ad:0x40011800 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end tree "USART10" base ad:0x40011C00 group.long 0x0++0x17 line.long 0x0 "CR1,Control register 1" bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1" bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1" bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1" bitfld.long 0x0 28. "M1,Word length" "0,1" bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1" bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1" bitfld.long 0x0 25. "DEAT4,Driver Enable assertion" "0,1" bitfld.long 0x0 24. "DEAT3,DEAT3" "0,1" bitfld.long 0x0 23. "DEAT2,DEAT2" "0,1" newline bitfld.long 0x0 22. "DEAT1,DEAT1" "0,1" bitfld.long 0x0 21. "DEAT0,DEAT0" "0,1" bitfld.long 0x0 20. "DEDT4,Driver Enable de-assertion" "0,1" bitfld.long 0x0 19. "DEDT3,DEDT3" "0,1" bitfld.long 0x0 18. "DEDT2,DEDT2" "0,1" bitfld.long 0x0 17. "DEDT1,DEDT1" "0,1" bitfld.long 0x0 16. "DEDT0,DEDT0" "0,1" bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1" bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1" newline bitfld.long 0x0 13. "MME,Mute mode enable" "0,1" bitfld.long 0x0 12. "M0,Word length" "0,1" bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1" bitfld.long 0x0 10. "PCE,Parity control enable" "0,1" bitfld.long 0x0 9. "PS,Parity selection" "0,1" bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1" bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1" bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1" bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1" newline bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1" bitfld.long 0x0 3. "TE,Transmitter enable" "0,1" bitfld.long 0x0 2. "RE,Receiver enable" "0,1" bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1" bitfld.long 0x0 0. "UE,USART enable" "0,1" line.long 0x4 "CR2,Control register 2" hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node" hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node" bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1" bitfld.long 0x4 22. "ABRMOD1,Auto baud rate mode" "0,1" bitfld.long 0x4 21. "ABRMOD0,ABRMOD0" "0,1" bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1" bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1" bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1" bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1" newline bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1" bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1" bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1" bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3" bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1" bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1" bitfld.long 0x4 9. "CPHA,Clock phase" "0,1" bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1" bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1" newline bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1" bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1" bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1" bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1" line.long 0x8 "CR3,Control register 3" hexmask.long.byte 0x8 29.--31. 1. "TXFTCFG,TXFIFO threshold" bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1" hexmask.long.byte 0x8 25.--28. 1. "RXFTCFG,Receive FIFO threshold" bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time " "0,1" bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt" "0,1" bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1" bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3" hexmask.long.byte 0x8 17.--20. 1. "SCARCNT,Smartcard auto-retry count" bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1" newline bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1" bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1" bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1" bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1" bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1" bitfld.long 0x8 9. "CTSE,CTS enable" "0,1" bitfld.long 0x8 8. "RTSE,RTS enable" "0,1" bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1" bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1" newline bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1" bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1" bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1" bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1" bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1" bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1" line.long 0xC "BRR,Baud rate register" hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,DIV_Mantissa" hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,DIV_Fraction" line.long 0x10 "GTPR,Guard time and prescaler" hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value" hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value" line.long 0x14 "RTOR,Receiver timeout register" hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length" hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value" wgroup.long 0x18++0x3 line.long 0x0 "RQR,Request register" bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1" bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1" bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1" bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1" bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "ISR,Interrupt & status" bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1" bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1" bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1" bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1" bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1" bitfld.long 0x0 22. "REACK,REACK" "0,1" bitfld.long 0x0 21. "TEACK,TEACK" "0,1" bitfld.long 0x0 20. "WUF,WUF" "0,1" bitfld.long 0x0 19. "RWU,RWU" "0,1" newline bitfld.long 0x0 18. "SBKF,SBKF" "0,1" bitfld.long 0x0 17. "CMF,CMF" "0,1" bitfld.long 0x0 16. "BUSY,BUSY" "0,1" bitfld.long 0x0 15. "ABRF,ABRF" "0,1" bitfld.long 0x0 14. "ABRE,ABRE" "0,1" bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1" bitfld.long 0x0 12. "EOBF,EOBF" "0,1" bitfld.long 0x0 11. "RTOF,RTOF" "0,1" bitfld.long 0x0 10. "CTS,CTS" "0,1" newline bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1" bitfld.long 0x0 8. "LBDF,LBDF" "0,1" bitfld.long 0x0 7. "TXE,TXE" "0,1" bitfld.long 0x0 6. "TC,TC" "0,1" bitfld.long 0x0 5. "RXNE,RXNE" "0,1" bitfld.long 0x0 4. "IDLE,IDLE" "0,1" bitfld.long 0x0 3. "ORE,ORE" "0,1" bitfld.long 0x0 2. "NF,NF" "0,1" bitfld.long 0x0 1. "FE,FE" "0,1" newline bitfld.long 0x0 0. "PE,PE" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "ICR,Interrupt flag clear register" bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1" bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1" bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1" bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1" bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1" bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1" bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1" bitfld.long 0x0 7. "TCBGTC,Transmission complete before Guard time" "0,1" bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1" newline bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1" bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1" bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1" bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1" bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1" bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "RDR,Receive data register" hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value" group.long 0x28++0x7 line.long 0x0 "TDR,Transmit data register" hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value" line.long 0x4 "PRESC,USART prescaler register" hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler" tree.end endif tree.end tree "USB_OTG_HS (USB On-the-go High-Speed)" base ad:0x0 sif (cpuis("STM32H743*")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H750*")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H753*")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H7A3*")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H7B0*")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" hexmask.long.byte 0xC 0.--3. 1. "TOCAL,FS timeout calibration" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" hexmask.long.byte 0x0 25.--28. 1. "LPMRCNTSTS,LPM retry count status" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" hexmask.long.byte 0x0 21.--24. 1. "LPMRCNT,LPM retry count" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")||cpuis("STM32H7B0*")) tree "OTG1_HS_DEVICE" base ad:0x40040800 group.long 0x0++0x7 line.long 0x0 "OTG_HS_DCFG,OTG_HS device configuration" bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic scheduling" "0,1,2,3" bitfld.long 0x0 11.--12. "PFIVL,Periodic (micro)frame" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" bitfld.long 0x0 2. "NZLSOHSK,Nonzero-length status OUT" "0,1" bitfld.long 0x0 0.--1. "DSPD,Device speed" "0,1,2,3" line.long 0x4 "OTG_HS_DCTL,OTG_HS device control register" bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")||cpuis("STM32H7A3*")) bitfld.long 0x4 4.--6. "TCTL,Test control" "0,1,2,3,4,5,6,7" endif sif (cpuis("STM32H7B0*")) hexmask.long.byte 0x4 4.--7. 1. "TCTL,Test control" endif rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0,1" rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0,1" bitfld.long 0x4 1. "SDIS,Soft disconnect" "0,1" newline bitfld.long 0x4 0. "RWUSIG,Remote wakeup signaling" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "OTG_HS_DSTS,OTG_HS device status register" hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received" bitfld.long 0x0 3. "EERR,Erratic error" "0,1" bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0,1,2,3" bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1" group.long 0x10++0x7 line.long 0x0 "OTG_HS_DIEPMSK,OTG_HS device IN endpoint common interrupt" bitfld.long 0x0 9. "BIM,BNA interrupt mask" "0,1" bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0,1" bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective" "0,1" bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,IN token received when TxFIFO empty" "0,1" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (nonisochronous" "0,1" bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt" "0,1" line.long 0x4 "OTG_HS_DOEPMSK,OTG_HS device OUT endpoint common interrupt" bitfld.long 0x4 9. "BOIM,BNA interrupt mask" "0,1" bitfld.long 0x4 8. "OPEM,OUT packet error mask" "0,1" bitfld.long 0x4 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint" "0,1" bitfld.long 0x4 3. "STUPM,SETUP phase done mask" "0,1" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt" "0,1" bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "OTG_HS_DAINT,OTG_HS device all endpoints interrupt" hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt" hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits" group.long 0x1C++0x3 line.long 0x0 "OTG_HS_DAINTMSK,OTG_HS all endpoints interrupt mask" hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits" hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits" group.long 0x28++0x17 line.long 0x0 "OTG_HS_DVBUSDIS,OTG_HS device VBUS discharge time" hexmask.long.word 0x0 0.--15. 1. "VBUSDT,Device VBUS discharge time" line.long 0x4 "OTG_HS_DVBUSPULSE,OTG_HS device VBUS pulsing time" hexmask.long.word 0x4 0.--11. 1. "DVBUSP,Device VBUS pulsing time" line.long 0x8 "OTG_HS_DTHRCTL,OTG_HS Device threshold control" bitfld.long 0x8 27. "ARPEN,Arbiter parking enable" "0,1" hexmask.long.word 0x8 17.--25. 1. "RXTHRLEN,Receive threshold length" bitfld.long 0x8 16. "RXTHREN,Receive threshold enable" "0,1" hexmask.long.word 0x8 2.--10. 1. "TXTHRLEN,Transmit threshold length" bitfld.long 0x8 1. "ISOTHREN,ISO IN endpoint threshold" "0,1" newline bitfld.long 0x8 0. "NONISOTHREN,Nonisochronous IN endpoints threshold" "0,1" line.long 0xC "OTG_HS_DIEPEMPMSK,OTG_HS device IN endpoint FIFO empty" hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask" line.long 0x10 "OTG_HS_DEACHINT,OTG_HS device each endpoint interrupt" bitfld.long 0x10 17. "OEP1INT,OUT endpoint 1 interrupt" "0,1" bitfld.long 0x10 1. "IEP1INT,IN endpoint 1interrupt bit" "0,1" line.long 0x14 "OTG_HS_DEACHINTMSK,OTG_HS device each endpoint interrupt" bitfld.long 0x14 17. "OEP1INTM,OUT Endpoint 1 interrupt mask" "0,1" bitfld.long 0x14 1. "IEP1INTM,IN Endpoint 1 interrupt mask" "0,1" group.long 0x100++0x3 line.long 0x0 "OTG_HS_DIEPCTL0,OTG device endpoint-0 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x120++0x3 line.long 0x0 "OTG_HS_DIEPCTL1,OTG device endpoint-1 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x140++0x3 line.long 0x0 "OTG_HS_DIEPCTL2,OTG device endpoint-2 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x160++0x3 line.long 0x0 "OTG_HS_DIEPCTL3,OTG device endpoint-3 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x180++0x3 line.long 0x0 "OTG_HS_DIEPCTL4,OTG device endpoint-4 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1A0++0x3 line.long 0x0 "OTG_HS_DIEPCTL5,OTG device endpoint-5 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1C0++0x3 line.long 0x0 "OTG_HS_DIEPCTL6,OTG device endpoint-6 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1E0++0x3 line.long 0x0 "OTG_HS_DIEPCTL7,OTG device endpoint-7 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x108++0x3 line.long 0x0 "OTG_HS_DIEPINT0,OTG device endpoint-0 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x128++0x3 line.long 0x0 "OTG_HS_DIEPINT1,OTG device endpoint-1 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x148++0x3 line.long 0x0 "OTG_HS_DIEPINT2,OTG device endpoint-2 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x168++0x3 line.long 0x0 "OTG_HS_DIEPINT3,OTG device endpoint-3 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x188++0x3 line.long 0x0 "OTG_HS_DIEPINT4,OTG device endpoint-4 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1A8++0x3 line.long 0x0 "OTG_HS_DIEPINT5,OTG device endpoint-5 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1C8++0x3 line.long 0x0 "OTG_HS_DIEPINT6,OTG device endpoint-6 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1E8++0x3 line.long 0x0 "OTG_HS_DIEPINT7,OTG device endpoint-7 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x110++0x7 line.long 0x0 "OTG_HS_DIEPTSIZ0,OTG_HS device IN endpoint 0 transfer size" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_HS_DIEPDMA1,OTG_HS device endpoint-1 DMA address" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA address" group.long 0x134++0x3 line.long 0x0 "OTG_HS_DIEPDMA2,OTG_HS device endpoint-2 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x154++0x3 line.long 0x0 "OTG_HS_DIEPDMA3,OTG_HS device endpoint-3 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x174++0x3 line.long 0x0 "OTG_HS_DIEPDMA4,OTG_HS device endpoint-4 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x194++0x3 line.long 0x0 "OTG_HS_DIEPDMA5,OTG_HS device endpoint-5 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" rgroup.long 0x118++0x3 line.long 0x0 "OTG_HS_DTXFSTS0,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x138++0x3 line.long 0x0 "OTG_HS_DTXFSTS1,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x158++0x3 line.long 0x0 "OTG_HS_DTXFSTS2,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x178++0x3 line.long 0x0 "OTG_HS_DTXFSTS3,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x198++0x3 line.long 0x0 "OTG_HS_DTXFSTS4,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x1B8++0x3 line.long 0x0 "OTG_HS_DTXFSTS5,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" group.long 0x130++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ1,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x150++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ2,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x170++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ3,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x190++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ4,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1B0++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ5,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x300++0x3 line.long 0x0 "OTG_HS_DOEPCTL0,OTG_HS device control OUT endpoint 0 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0,1,2,3" group.long 0x320++0x3 line.long 0x0 "OTG_HS_DOEPCTL1,OTG device endpoint-1 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x340++0x3 line.long 0x0 "OTG_HS_DOEPCTL2,OTG device endpoint-2 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x360++0x3 line.long 0x0 "OTG_HS_DOEPCTL3,OTG device endpoint-3 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x308++0x3 line.long 0x0 "OTG_HS_DOEPINT0,OTG_HS device endpoint-0 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x328++0x3 line.long 0x0 "OTG_HS_DOEPINT1,OTG_HS device endpoint-1 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x348++0x3 line.long 0x0 "OTG_HS_DOEPINT2,OTG_HS device endpoint-2 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x368++0x3 line.long 0x0 "OTG_HS_DOEPINT3,OTG_HS device endpoint-3 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x388++0x3 line.long 0x0 "OTG_HS_DOEPINT4,OTG_HS device endpoint-4 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3A8++0x3 line.long 0x0 "OTG_HS_DOEPINT5,OTG_HS device endpoint-5 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3C8++0x3 line.long 0x0 "OTG_HS_DOEPINT6,OTG_HS device endpoint-6 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3E8++0x3 line.long 0x0 "OTG_HS_DOEPINT7,OTG_HS device endpoint-7 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x310++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ0,OTG_HS device endpoint-0 transfer size" bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "0,1,2,3" bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" group.long 0x330++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ1,OTG_HS device endpoint-1 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x350++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ2,OTG_HS device endpoint-2 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x370++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ3,OTG_HS device endpoint-3 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x390++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ4,OTG_HS device endpoint-4 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1A0++0xF line.long 0x0 "OTG_HS_DIEPTSIZ6,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_HS_DTXFSTS6,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x4 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" line.long 0x8 "OTG_HS_DIEPTSIZ7,OTG_HS device endpoint transfer size" bitfld.long 0x8 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,Transfer size" line.long 0xC "OTG_HS_DTXFSTS7,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0xC 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" group.long 0x380++0x3 line.long 0x0 "OTG_HS_DOEPCTL4,OTG device endpoint-4 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3A0++0x3 line.long 0x0 "OTG_HS_DOEPCTL5,OTG device endpoint-5 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3C0++0x3 line.long 0x0 "OTG_HS_DOEPCTL6,OTG device endpoint-6 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3E0++0x3 line.long 0x0 "OTG_HS_DOEPCTL7,OTG device endpoint-7 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3B0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ5,OTG_HS device endpoint-5 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x3D0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ6,OTG_HS device endpoint-6 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x3F0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ7,OTG_HS device endpoint-7 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" tree.end endif sif (cpuis("STM32H742*")) tree "OTG2_HS_GLOBAL" base ad:0x40080000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")||cpuis("STM32H750*")||cpuis("STM32H753*")||cpuis("STM32H755??-CM4")||cpuis("STM32H755??-CM7")||cpuis("STM32H757??-CM4")||cpuis("STM32H757??-CM7")) tree "OTG2_HS_DEVICE" base ad:0x40080800 group.long 0x0++0x7 line.long 0x0 "OTG_HS_DCFG,OTG_HS device configuration" bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic scheduling" "0,1,2,3" bitfld.long 0x0 11.--12. "PFIVL,Periodic (micro)frame" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" bitfld.long 0x0 2. "NZLSOHSK,Nonzero-length status OUT" "0,1" bitfld.long 0x0 0.--1. "DSPD,Device speed" "0,1,2,3" line.long 0x4 "OTG_HS_DCTL,OTG_HS device control register" bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" newline bitfld.long 0x4 4.--6. "TCTL,Test control" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0,1" rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0,1" bitfld.long 0x4 1. "SDIS,Soft disconnect" "0,1" bitfld.long 0x4 0. "RWUSIG,Remote wakeup signaling" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "OTG_HS_DSTS,OTG_HS device status register" hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received" bitfld.long 0x0 3. "EERR,Erratic error" "0,1" bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0,1,2,3" bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1" group.long 0x10++0x7 line.long 0x0 "OTG_HS_DIEPMSK,OTG_HS device IN endpoint common interrupt" bitfld.long 0x0 9. "BIM,BNA interrupt mask" "0,1" bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0,1" bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective" "0,1" bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,IN token received when TxFIFO empty" "0,1" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (nonisochronous" "0,1" bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt" "0,1" line.long 0x4 "OTG_HS_DOEPMSK,OTG_HS device OUT endpoint common interrupt" bitfld.long 0x4 9. "BOIM,BNA interrupt mask" "0,1" bitfld.long 0x4 8. "OPEM,OUT packet error mask" "0,1" bitfld.long 0x4 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint" "0,1" bitfld.long 0x4 3. "STUPM,SETUP phase done mask" "0,1" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt" "0,1" bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "OTG_HS_DAINT,OTG_HS device all endpoints interrupt" hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt" hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits" group.long 0x1C++0x3 line.long 0x0 "OTG_HS_DAINTMSK,OTG_HS all endpoints interrupt mask" hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits" hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits" group.long 0x28++0x17 line.long 0x0 "OTG_HS_DVBUSDIS,OTG_HS device VBUS discharge time" hexmask.long.word 0x0 0.--15. 1. "VBUSDT,Device VBUS discharge time" line.long 0x4 "OTG_HS_DVBUSPULSE,OTG_HS device VBUS pulsing time" hexmask.long.word 0x4 0.--11. 1. "DVBUSP,Device VBUS pulsing time" line.long 0x8 "OTG_HS_DTHRCTL,OTG_HS Device threshold control" bitfld.long 0x8 27. "ARPEN,Arbiter parking enable" "0,1" hexmask.long.word 0x8 17.--25. 1. "RXTHRLEN,Receive threshold length" bitfld.long 0x8 16. "RXTHREN,Receive threshold enable" "0,1" hexmask.long.word 0x8 2.--10. 1. "TXTHRLEN,Transmit threshold length" bitfld.long 0x8 1. "ISOTHREN,ISO IN endpoint threshold" "0,1" newline bitfld.long 0x8 0. "NONISOTHREN,Nonisochronous IN endpoints threshold" "0,1" line.long 0xC "OTG_HS_DIEPEMPMSK,OTG_HS device IN endpoint FIFO empty" hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask" line.long 0x10 "OTG_HS_DEACHINT,OTG_HS device each endpoint interrupt" bitfld.long 0x10 17. "OEP1INT,OUT endpoint 1 interrupt" "0,1" bitfld.long 0x10 1. "IEP1INT,IN endpoint 1interrupt bit" "0,1" line.long 0x14 "OTG_HS_DEACHINTMSK,OTG_HS device each endpoint interrupt" bitfld.long 0x14 17. "OEP1INTM,OUT Endpoint 1 interrupt mask" "0,1" bitfld.long 0x14 1. "IEP1INTM,IN Endpoint 1 interrupt mask" "0,1" group.long 0x100++0x3 line.long 0x0 "OTG_HS_DIEPCTL0,OTG device endpoint-0 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x120++0x3 line.long 0x0 "OTG_HS_DIEPCTL1,OTG device endpoint-1 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x140++0x3 line.long 0x0 "OTG_HS_DIEPCTL2,OTG device endpoint-2 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x160++0x3 line.long 0x0 "OTG_HS_DIEPCTL3,OTG device endpoint-3 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x180++0x3 line.long 0x0 "OTG_HS_DIEPCTL4,OTG device endpoint-4 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1A0++0x3 line.long 0x0 "OTG_HS_DIEPCTL5,OTG device endpoint-5 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1C0++0x3 line.long 0x0 "OTG_HS_DIEPCTL6,OTG device endpoint-6 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1E0++0x3 line.long 0x0 "OTG_HS_DIEPCTL7,OTG device endpoint-7 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x108++0x3 line.long 0x0 "OTG_HS_DIEPINT0,OTG device endpoint-0 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x128++0x3 line.long 0x0 "OTG_HS_DIEPINT1,OTG device endpoint-1 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x148++0x3 line.long 0x0 "OTG_HS_DIEPINT2,OTG device endpoint-2 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x168++0x3 line.long 0x0 "OTG_HS_DIEPINT3,OTG device endpoint-3 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x188++0x3 line.long 0x0 "OTG_HS_DIEPINT4,OTG device endpoint-4 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1A8++0x3 line.long 0x0 "OTG_HS_DIEPINT5,OTG device endpoint-5 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1C8++0x3 line.long 0x0 "OTG_HS_DIEPINT6,OTG device endpoint-6 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1E8++0x3 line.long 0x0 "OTG_HS_DIEPINT7,OTG device endpoint-7 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x110++0x7 line.long 0x0 "OTG_HS_DIEPTSIZ0,OTG_HS device IN endpoint 0 transfer size" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_HS_DIEPDMA1,OTG_HS device endpoint-1 DMA address" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA address" group.long 0x134++0x3 line.long 0x0 "OTG_HS_DIEPDMA2,OTG_HS device endpoint-2 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x154++0x3 line.long 0x0 "OTG_HS_DIEPDMA3,OTG_HS device endpoint-3 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x174++0x3 line.long 0x0 "OTG_HS_DIEPDMA4,OTG_HS device endpoint-4 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x194++0x3 line.long 0x0 "OTG_HS_DIEPDMA5,OTG_HS device endpoint-5 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" rgroup.long 0x118++0x3 line.long 0x0 "OTG_HS_DTXFSTS0,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x138++0x3 line.long 0x0 "OTG_HS_DTXFSTS1,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x158++0x3 line.long 0x0 "OTG_HS_DTXFSTS2,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x178++0x3 line.long 0x0 "OTG_HS_DTXFSTS3,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x198++0x3 line.long 0x0 "OTG_HS_DTXFSTS4,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x1B8++0x3 line.long 0x0 "OTG_HS_DTXFSTS5,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" group.long 0x130++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ1,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x150++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ2,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x170++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ3,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x190++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ4,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1B0++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ5,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x300++0x3 line.long 0x0 "OTG_HS_DOEPCTL0,OTG_HS device control OUT endpoint 0 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0,1,2,3" group.long 0x320++0x3 line.long 0x0 "OTG_HS_DOEPCTL1,OTG device endpoint-1 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x340++0x3 line.long 0x0 "OTG_HS_DOEPCTL2,OTG device endpoint-2 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x360++0x3 line.long 0x0 "OTG_HS_DOEPCTL3,OTG device endpoint-3 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x308++0x3 line.long 0x0 "OTG_HS_DOEPINT0,OTG_HS device endpoint-0 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x328++0x3 line.long 0x0 "OTG_HS_DOEPINT1,OTG_HS device endpoint-1 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x348++0x3 line.long 0x0 "OTG_HS_DOEPINT2,OTG_HS device endpoint-2 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x368++0x3 line.long 0x0 "OTG_HS_DOEPINT3,OTG_HS device endpoint-3 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x388++0x3 line.long 0x0 "OTG_HS_DOEPINT4,OTG_HS device endpoint-4 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3A8++0x3 line.long 0x0 "OTG_HS_DOEPINT5,OTG_HS device endpoint-5 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3C8++0x3 line.long 0x0 "OTG_HS_DOEPINT6,OTG_HS device endpoint-6 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3E8++0x3 line.long 0x0 "OTG_HS_DOEPINT7,OTG_HS device endpoint-7 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x310++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ0,OTG_HS device endpoint-0 transfer size" bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "0,1,2,3" bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" group.long 0x330++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ1,OTG_HS device endpoint-1 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x350++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ2,OTG_HS device endpoint-2 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x370++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ3,OTG_HS device endpoint-3 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x390++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ4,OTG_HS device endpoint-4 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1A0++0xF line.long 0x0 "OTG_HS_DIEPTSIZ6,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_HS_DTXFSTS6,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x4 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" line.long 0x8 "OTG_HS_DIEPTSIZ7,OTG_HS device endpoint transfer size" bitfld.long 0x8 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,Transfer size" line.long 0xC "OTG_HS_DTXFSTS7,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0xC 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" group.long 0x380++0x3 line.long 0x0 "OTG_HS_DOEPCTL4,OTG device endpoint-4 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3A0++0x3 line.long 0x0 "OTG_HS_DOEPCTL5,OTG device endpoint-5 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3C0++0x3 line.long 0x0 "OTG_HS_DOEPCTL6,OTG device endpoint-6 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3E0++0x3 line.long 0x0 "OTG_HS_DOEPCTL7,OTG device endpoint-7 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3B0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ5,OTG_HS device endpoint-5 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x3D0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ6,OTG_HS device endpoint-6 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x3F0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ7,OTG_HS device endpoint-7 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" tree.end tree "OTG2_HS_HOST" base ad:0x40080400 group.long 0x0++0x7 line.long 0x0 "OTG_HS_HCFG,OTG_HS host configuration" rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1" bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "0,1,2,3" line.long 0x4 "OTG_HS_HFIR,OTG_HS Host frame interval" hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval" rgroup.long 0x8++0x3 line.long 0x0 "OTG_HS_HFNUM,OTG_HS host frame number/frame time" hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining" hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number" group.long 0x10++0x3 line.long 0x0 "OTG_HS_HPTXSTS,OTG_HS_Host periodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space" rgroup.long 0x14++0x3 line.long 0x0 "OTG_HS_HAINT,OTG_HS Host all channels interrupt" hexmask.long.word 0x0 0.--15. 1. "HAINT,Channel interrupts" group.long 0x18++0x3 line.long 0x0 "OTG_HS_HAINTMSK,OTG_HS host all channels interrupt mask" hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask" group.long 0x40++0x3 line.long 0x0 "OTG_HS_HPRT,OTG_HS host port control and status" rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0,1,2,3" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control" bitfld.long 0x0 12. "PPWR,Port power" "0,1" rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3" bitfld.long 0x0 8. "PRST,Port reset" "0,1" bitfld.long 0x0 7. "PSUSP,Port suspend" "0,1" bitfld.long 0x0 6. "PRES,Port resume" "0,1" newline bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1" rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0,1" bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1" bitfld.long 0x0 2. "PENA,Port enable" "0,1" bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1" rbitfld.long 0x0 0. "PCSTS,Port connect status" "0,1" group.long 0x100++0x3 line.long 0x0 "OTG_HS_HCCHAR0,OTG_HS host channel-0 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x120++0x3 line.long 0x0 "OTG_HS_HCCHAR1,OTG_HS host channel-1 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x140++0x3 line.long 0x0 "OTG_HS_HCCHAR2,OTG_HS host channel-2 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x160++0x3 line.long 0x0 "OTG_HS_HCCHAR3,OTG_HS host channel-3 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x180++0x3 line.long 0x0 "OTG_HS_HCCHAR4,OTG_HS host channel-4 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1A0++0x3 line.long 0x0 "OTG_HS_HCCHAR5,OTG_HS host channel-5 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1C0++0x3 line.long 0x0 "OTG_HS_HCCHAR6,OTG_HS host channel-6 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1E0++0x3 line.long 0x0 "OTG_HS_HCCHAR7,OTG_HS host channel-7 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x200++0x3 line.long 0x0 "OTG_HS_HCCHAR8,OTG_HS host channel-8 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x220++0x3 line.long 0x0 "OTG_HS_HCCHAR9,OTG_HS host channel-9 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x240++0x3 line.long 0x0 "OTG_HS_HCCHAR10,OTG_HS host channel-10 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x260++0x3 line.long 0x0 "OTG_HS_HCCHAR11,OTG_HS host channel-11 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x104++0x3 line.long 0x0 "OTG_HS_HCSPLT0,OTG_HS host channel-0 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x124++0x3 line.long 0x0 "OTG_HS_HCSPLT1,OTG_HS host channel-1 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x144++0x3 line.long 0x0 "OTG_HS_HCSPLT2,OTG_HS host channel-2 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x164++0x3 line.long 0x0 "OTG_HS_HCSPLT3,OTG_HS host channel-3 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x184++0x3 line.long 0x0 "OTG_HS_HCSPLT4,OTG_HS host channel-4 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x1A4++0x3 line.long 0x0 "OTG_HS_HCSPLT5,OTG_HS host channel-5 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x1C4++0x3 line.long 0x0 "OTG_HS_HCSPLT6,OTG_HS host channel-6 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x1E4++0x3 line.long 0x0 "OTG_HS_HCSPLT7,OTG_HS host channel-7 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x204++0x3 line.long 0x0 "OTG_HS_HCSPLT8,OTG_HS host channel-8 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x224++0x3 line.long 0x0 "OTG_HS_HCSPLT9,OTG_HS host channel-9 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x244++0x3 line.long 0x0 "OTG_HS_HCSPLT10,OTG_HS host channel-10 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x264++0x3 line.long 0x0 "OTG_HS_HCSPLT11,OTG_HS host channel-11 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x108++0x3 line.long 0x0 "OTG_HS_HCINT0,OTG_HS host channel-11 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x128++0x3 line.long 0x0 "OTG_HS_HCINT1,OTG_HS host channel-1 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x148++0x3 line.long 0x0 "OTG_HS_HCINT2,OTG_HS host channel-2 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x168++0x3 line.long 0x0 "OTG_HS_HCINT3,OTG_HS host channel-3 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x188++0x3 line.long 0x0 "OTG_HS_HCINT4,OTG_HS host channel-4 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1A8++0x3 line.long 0x0 "OTG_HS_HCINT5,OTG_HS host channel-5 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1C8++0x3 line.long 0x0 "OTG_HS_HCINT6,OTG_HS host channel-6 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1E8++0x3 line.long 0x0 "OTG_HS_HCINT7,OTG_HS host channel-7 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x208++0x3 line.long 0x0 "OTG_HS_HCINT8,OTG_HS host channel-8 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x228++0x3 line.long 0x0 "OTG_HS_HCINT9,OTG_HS host channel-9 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x248++0x3 line.long 0x0 "OTG_HS_HCINT10,OTG_HS host channel-10 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x268++0x3 line.long 0x0 "OTG_HS_HCINT11,OTG_HS host channel-11 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x10C++0x3 line.long 0x0 "OTG_HS_HCINTMSK0,OTG_HS host channel-11 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x12C++0x3 line.long 0x0 "OTG_HS_HCINTMSK1,OTG_HS host channel-1 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x14C++0x3 line.long 0x0 "OTG_HS_HCINTMSK2,OTG_HS host channel-2 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x16C++0x3 line.long 0x0 "OTG_HS_HCINTMSK3,OTG_HS host channel-3 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x18C++0x3 line.long 0x0 "OTG_HS_HCINTMSK4,OTG_HS host channel-4 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x1AC++0x3 line.long 0x0 "OTG_HS_HCINTMSK5,OTG_HS host channel-5 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x1CC++0x3 line.long 0x0 "OTG_HS_HCINTMSK6,OTG_HS host channel-6 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x1EC++0x3 line.long 0x0 "OTG_HS_HCINTMSK7,OTG_HS host channel-7 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x20C++0x3 line.long 0x0 "OTG_HS_HCINTMSK8,OTG_HS host channel-8 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x22C++0x3 line.long 0x0 "OTG_HS_HCINTMSK9,OTG_HS host channel-9 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x24C++0x3 line.long 0x0 "OTG_HS_HCINTMSK10,OTG_HS host channel-10 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x26C++0x3 line.long 0x0 "OTG_HS_HCINTMSK11,OTG_HS host channel-11 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x110++0x3 line.long 0x0 "OTG_HS_HCTSIZ0,OTG_HS host channel-11 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x130++0x3 line.long 0x0 "OTG_HS_HCTSIZ1,OTG_HS host channel-1 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x150++0x3 line.long 0x0 "OTG_HS_HCTSIZ2,OTG_HS host channel-2 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x170++0x3 line.long 0x0 "OTG_HS_HCTSIZ3,OTG_HS host channel-3 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x190++0x3 line.long 0x0 "OTG_HS_HCTSIZ4,OTG_HS host channel-4 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1B0++0x3 line.long 0x0 "OTG_HS_HCTSIZ5,OTG_HS host channel-5 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1D0++0x3 line.long 0x0 "OTG_HS_HCTSIZ6,OTG_HS host channel-6 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1F0++0x3 line.long 0x0 "OTG_HS_HCTSIZ7,OTG_HS host channel-7 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x210++0x3 line.long 0x0 "OTG_HS_HCTSIZ8,OTG_HS host channel-8 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x230++0x3 line.long 0x0 "OTG_HS_HCTSIZ9,OTG_HS host channel-9 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x250++0x3 line.long 0x0 "OTG_HS_HCTSIZ10,OTG_HS host channel-10 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x270++0x3 line.long 0x0 "OTG_HS_HCTSIZ11,OTG_HS host channel-11 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x114++0x3 line.long 0x0 "OTG_HS_HCDMA0,OTG_HS host channel-0 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x134++0x3 line.long 0x0 "OTG_HS_HCDMA1,OTG_HS host channel-1 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x154++0x3 line.long 0x0 "OTG_HS_HCDMA2,OTG_HS host channel-2 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x174++0x3 line.long 0x0 "OTG_HS_HCDMA3,OTG_HS host channel-3 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x194++0x3 line.long 0x0 "OTG_HS_HCDMA4,OTG_HS host channel-4 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x1B4++0x3 line.long 0x0 "OTG_HS_HCDMA5,OTG_HS host channel-5 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x1D4++0x3 line.long 0x0 "OTG_HS_HCDMA6,OTG_HS host channel-6 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x1F4++0x3 line.long 0x0 "OTG_HS_HCDMA7,OTG_HS host channel-7 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x214++0x3 line.long 0x0 "OTG_HS_HCDMA8,OTG_HS host channel-8 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x234++0x3 line.long 0x0 "OTG_HS_HCDMA9,OTG_HS host channel-9 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x254++0x3 line.long 0x0 "OTG_HS_HCDMA10,OTG_HS host channel-10 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x274++0x63 line.long 0x0 "OTG_HS_HCDMA11,OTG_HS host channel-11 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" line.long 0x4 "OTG_HS_HCCHAR12,OTG_HS host channel-12 characteristics" bitfld.long 0x4 31. "CHENA,Channel enable" "0,1" bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x4 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" bitfld.long 0x4 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HS_HCSPLT12,OTG_HS host channel-12 split control" bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HS_HCINT12,OTG_HS host channel-12 interrupt" bitfld.long 0xC 10. "DTERR,Data toggle error" "0,1" bitfld.long 0xC 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0xC 8. "BBERR,Babble error" "0,1" bitfld.long 0xC 7. "TXERR,Transaction error" "0,1" bitfld.long 0xC 6. "NYET,Response received" "0,1" bitfld.long 0xC 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0xC 4. "NAK,NAK response received" "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received" "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" bitfld.long 0xC 1. "CHH,Channel halted" "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed" "0,1" line.long 0x10 "OTG_HS_HCINTMSK12,OTG_HS host channel-12 interrupt mask" bitfld.long 0x10 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x10 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x10 8. "BBERRM,Babble error" "0,1" bitfld.long 0x10 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x10 6. "NYET,Response received" "0,1" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x10 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x10 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x10 2. "AHBERR,AHB error" "0,1" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x14 "OTG_HS_HCTSIZ12,OTG_HS host channel-12 transfer size" bitfld.long 0x14 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HS_HCDMA12,OTG_HS host channel-12 DMA address" hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" line.long 0x1C "OTG_HS_HCCHAR13,OTG_HS host channel-13 characteristics" bitfld.long 0x1C 31. "CHENA,Channel enable" "0,1" bitfld.long 0x1C 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x1C 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x1C 22.--28. 1. "DAD,Device address" bitfld.long 0x1C 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x1C 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x1C 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x1C 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x1C 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x1C 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x20 "OTG_HS_HCSPLT13,OTG_HS host channel-13 split control" bitfld.long 0x20 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x20 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x20 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x20 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x20 0.--6. 1. "PRTADDR,Port address" line.long 0x24 "OTG_HS_HCINT13,OTG_HS host channel-13 interrupt" bitfld.long 0x24 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x24 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x24 8. "BBERR,Babble error" "0,1" bitfld.long 0x24 7. "TXERR,Transaction error" "0,1" bitfld.long 0x24 6. "NYET,Response received" "0,1" bitfld.long 0x24 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x24 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x24 3. "STALL,STALL response received" "0,1" bitfld.long 0x24 2. "AHBERR,AHB error" "0,1" bitfld.long 0x24 1. "CHH,Channel halted" "0,1" bitfld.long 0x24 0. "XFRC,Transfer completed" "0,1" line.long 0x28 "OTG_HS_HCINTMSK13,OTG_HS host channel-13 interrupt mask" bitfld.long 0x28 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x28 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x28 8. "BBERRM,Babble error" "0,1" bitfld.long 0x28 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x28 6. "NYET,Response received" "0,1" bitfld.long 0x28 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x28 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x28 3. "STALLM,STALLM response received interrupt" "0,1" bitfld.long 0x28 2. "AHBERR,AHB error" "0,1" bitfld.long 0x28 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x28 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x2C "OTG_HS_HCTSIZ13,OTG_HS host channel-13 transfer size" bitfld.long 0x2C 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x2C 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x2C 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x30 "OTG_HS_HCDMA13,OTG_HS host channel-13 DMA address" hexmask.long 0x30 0.--31. 1. "DMAADDR,DMA address" line.long 0x34 "OTG_HS_HCCHAR14,OTG_HS host channel-14 characteristics" bitfld.long 0x34 31. "CHENA,Channel enable" "0,1" bitfld.long 0x34 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x34 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x34 22.--28. 1. "DAD,Device address" bitfld.long 0x34 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x34 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x34 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x34 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x34 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x34 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x38 "OTG_HS_HCSPLT14,OTG_HS host channel-14 split control" bitfld.long 0x38 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x38 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x38 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x38 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x38 0.--6. 1. "PRTADDR,Port address" line.long 0x3C "OTG_HS_HCINT14,OTG_HS host channel-14 interrupt" bitfld.long 0x3C 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x3C 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x3C 8. "BBERR,Babble error" "0,1" bitfld.long 0x3C 7. "TXERR,Transaction error" "0,1" bitfld.long 0x3C 6. "NYET,Response received" "0,1" bitfld.long 0x3C 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x3C 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x3C 3. "STALL,STALL response received" "0,1" bitfld.long 0x3C 2. "AHBERR,AHB error" "0,1" bitfld.long 0x3C 1. "CHH,Channel halted" "0,1" bitfld.long 0x3C 0. "XFRC,Transfer completed" "0,1" line.long 0x40 "OTG_HS_HCINTMSK14,OTG_HS host channel-14 interrupt mask" bitfld.long 0x40 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x40 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x40 8. "BBERRM,Babble error" "0,1" bitfld.long 0x40 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x40 6. "NYET,Response received" "0,1" bitfld.long 0x40 5. "ACKM,ACKM response received/transmitted" "0,1" bitfld.long 0x40 4. "NAKM,NAKM response received interrupt" "0,1" newline bitfld.long 0x40 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x40 2. "AHBERR,AHB error" "0,1" bitfld.long 0x40 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x40 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x44 "OTG_HS_HCTSIZ14,OTG_HS host channel-14 transfer size" bitfld.long 0x44 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x44 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x44 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x48 "OTG_HS_HCDMA14,OTG_HS host channel-14 DMA address" hexmask.long 0x48 0.--31. 1. "DMAADDR,DMA address" line.long 0x4C "OTG_HS_HCCHAR15,OTG_HS host channel-15 characteristics" bitfld.long 0x4C 31. "CHENA,Channel enable" "0,1" bitfld.long 0x4C 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x4C 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x4C 22.--28. 1. "DAD,Device address" bitfld.long 0x4C 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x4C 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x4C 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x4C 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x4C 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4C 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x50 "OTG_HS_HCSPLT15,OTG_HS host channel-15 split control" bitfld.long 0x50 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x50 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x50 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x50 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x50 0.--6. 1. "PRTADDR,Port address" line.long 0x54 "OTG_HS_HCINT15,OTG_HS host channel-15 interrupt" bitfld.long 0x54 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x54 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x54 8. "BBERR,Babble error" "0,1" bitfld.long 0x54 7. "TXERR,Transaction error" "0,1" bitfld.long 0x54 6. "NYET,Response received" "0,1" bitfld.long 0x54 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x54 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x54 3. "STALL,STALL response received" "0,1" bitfld.long 0x54 2. "AHBERR,AHB error" "0,1" bitfld.long 0x54 1. "CHH,Channel halted" "0,1" bitfld.long 0x54 0. "XFRC,Transfer completed" "0,1" line.long 0x58 "OTG_HS_HCINTMSK15,OTG_HS host channel-15 interrupt mask" bitfld.long 0x58 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x58 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x58 8. "BBERRM,Babble error" "0,1" bitfld.long 0x58 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x58 6. "NYET,Response received" "0,1" bitfld.long 0x58 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x58 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x58 3. "STALL,STALL response received interrupt" "0,1" bitfld.long 0x58 2. "AHBERR,AHB error" "0,1" bitfld.long 0x58 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x58 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x5C "OTG_HS_HCTSIZ15,OTG_HS host channel-15 transfer size" bitfld.long 0x5C 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x5C 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x5C 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x60 "OTG_HS_HCDMA15,OTG_HS host channel-15 DMA address" hexmask.long 0x60 0.--31. 1. "DMAADDR,DMA address" tree.end tree "OTG2_HS_PWRCLK" base ad:0x40080E00 group.long 0x0++0x3 line.long 0x0 "OTG_HS_PCGCR,Power and clock gating control" bitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1" bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1" bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1" tree.end endif sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0: Device mode,1: Host mode" newline bitfld.long 0x0 20. "OTGVER,OTG version" "0: OTG Version 1.3. OTG1.3 is obsolete for new..,1: OTG Version 2.0. In this version the core.." newline rbitfld.long 0x0 19. "BSVLD,B-session valid" "0: B-session is not valid.,1: B-session is valid." newline rbitfld.long 0x0 18. "ASVLD,A-session valid" "0: A-session is not valid,1: A-session is valid" newline rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0: Long debounce time used for physical connections..,1: Short debounce time used for soft connections.." newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0: The OTG_HS controller is in A-device mode,1: The OTG_HS controller is in B-device mode" newline bitfld.long 0x0 12. "EHEN,Embedded host enable" "0: OTG A device state machine is selected,1: Embedded host state machine is selected" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0: HNP is not enabled in the application,1: HNP is enabled in the application" newline bitfld.long 0x0 10. "HSHNPEN,host set HNP enable" "0: Host Set HNP is not enabled,1: Host Set HNP is enabled" newline bitfld.long 0x0 9. "HNPRQ,HNP request" "0: No HNP request,1: HNP request" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0: Host negotiation failure,1: Host negotiation success" newline bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value." "0: Bvalid value is '0' when BVALOEN = 1,1: Bvalid value is '1' when BVALOEN = 1" newline bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0: Override is disabled and Bvalid signal from the..,1: Internally Bvalid received from the PHY is.." newline bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value." "0: Avalid value is '0' when AVALOEN = 1,1: Avalid value is '1' when AVALOEN = 1" newline bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable." "0: Override is disabled and Avalid signal from the..,1: Internally Avalid received from the PHY is.." newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value." "0: vbusvalid value is '0' when VBVALOEN = 1,1: vbusvalid value is '1' when VBVALOEN = 1" newline bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable." "0: Override is disabled and vbusvalid signal from..,1: Internally vbusvalid received from the PHY is.." newline bitfld.long 0x0 1. "SRQ,Session request" "0: No session request,1: Session request" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0: Session request failure,1: Session request success" newline endif sif (cpuis("STM32H742*")) rbitfld.long 0x0 21. "CURMOD,Current mode of operation" "0,1" newline bitfld.long 0x0 20. "OTGVER,OTG version" "0,1" newline rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" newline rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" newline rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" newline rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" newline bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" newline bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" newline rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" newline bitfld.long 0x0 7. "BVALOVAL,B-peripheral session valid override value" "0,1" newline bitfld.long 0x0 6. "BVALOEN,B-peripheral session valid override enable." "0,1" newline bitfld.long 0x0 5. "AVALOVAL,A-peripheral session valid override value" "0,1" newline bitfld.long 0x0 4. "AVALOEN,A-peripheral session valid override enable" "0,1" newline bitfld.long 0x0 3. "VBVALOVAL,VBUS valid override value" "0,1" newline bitfld.long 0x0 2. "VBVALOEN,VBUS valid override enable" "0,1" newline bitfld.long 0x0 1. "SRQ,Session request" "0,1" endif line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" sif (cpuis("STM32H742*")) bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" newline endif bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" newline bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" newline bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" newline bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" newline bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" newline bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" newline bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" newline hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" newline sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x8 0. "GINTMSK,Global interrupt mask" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" endif line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" newline bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" newline bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" newline bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" newline bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" newline bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" newline bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" newline bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" newline bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" newline bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" newline hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" newline bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" newline bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" newline bitfld.long 0xC 0.--2. "TOCAL,FS timeout calibration" "0,1,2,3,4,5,6,7" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" newline rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" newline hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" newline bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" newline bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" newline bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" newline bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x14 31. "WKUPINT,Resume/remote wakeup detected interrupt" "0,1" newline bitfld.long 0x14 27. "LPMINT,LPM interrupt" "0,1" newline bitfld.long 0x14 23. "RSTDET,Reset detected interrupt" "0,1" newline bitfld.long 0x14 21. "IPXFR_INCOMPISOOUT," "0,1" newline rbitfld.long 0x14 7. "GONAKEFF,Global OUT NAK effective" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0: Device mode,1: Host mode" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" newline endif bitfld.long 0x14 30. "SRQINT,Session request/new session detected interrupt" "0,1" newline bitfld.long 0x14 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" newline rbitfld.long 0x14 26. "PTXFE,Periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" newline rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" newline bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" newline sif (cpuis("STM32H742*")) bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" newline endif bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN transfer" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" newline rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" newline bitfld.long 0x14 15. "EOPF,End of periodic frame interrupt" "0,1" newline bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" newline bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" newline bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" newline sif (cpuis("STM32H742*")) rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" newline endif rbitfld.long 0x14 6. "GINAKEFF,Global IN non-periodic NAK effective" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Non-periodic Tx FIFO empty" "0,1" newline rbitfld.long 0x14 4. "RXFLVL,Rx FIFO non-empty" "0,1" newline bitfld.long 0x14 3. "SOF,Start of frame" "0,1" newline rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" newline bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 30. "SRQIM,Session request/new session detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 26. "PTXFEM,Periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 25. "HCIM,Host channels interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 23. "RSTDETM,Reset detected interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 21. "IPXFRM_IISOOXFRM," "0,1" newline bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 12. "USBRST,USB reset mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 6. "GINAKEFFM,Global non-periodic IN NAK effective mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 5. "NPTXFEM,Non-periodic Tx FIFO empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 4. "RXFLVLM,Receive FIFO non-empty mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 3. "SOFM,Start of frame mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt mask" "0: Masked interrupt,1: Unmasked interrupt" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" newline bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" newline bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" newline bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" newline bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" newline rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" newline bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" newline bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" newline bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" newline bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" newline bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" newline bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" newline bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" newline bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline endif sif (cpuis("STM32H742*")) bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" newline bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" newline bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" newline bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" newline bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" endif rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" newline hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" newline hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" newline hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" newline bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" newline bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" newline bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" newline bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" newline bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" newline bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" newline bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" newline bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x1B line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" newline hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" newline hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" newline hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" newline hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" newline hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" newline hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) group.long 0x12C++0x3 line.long 0x0 "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" endif sif (cpuis("STM32H742*")) group.long 0x11C++0x3 line.long 0x0 "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" endif group.long 0x120++0x3 line.long 0x0 "OTG_DIEPTXF8," hexmask.long.word 0x0 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" newline hexmask.long.word 0x0 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) hexmask.long.byte 0x0 27.--30. 1. "STSPHST,Frame number" newline endif hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" newline hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) hexmask.long.byte 0x4 27.--30. 1. "STSPHST,Frame number" newline endif hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" newline hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" newline bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" newline hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" newline hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" newline rbitfld.long 0x0 25.--27. "LPMRCNTSTS,LPM retry count status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" newline bitfld.long 0x0 21.--23. "LPMRCNT,LPM retry count" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" newline rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" newline rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" newline bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" newline rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" newline hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" newline bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" newline bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif sif (cpuis("STM32H7B3*")) tree "OTG1_HS_GLOBAL" base ad:0x40040000 group.long 0x0++0x1B line.long 0x0 "OTG_HS_GOTGCTL,OTG_HS control and status" rbitfld.long 0x0 19. "BSVLD,B-session valid" "0,1" rbitfld.long 0x0 18. "ASVLD,A-session valid" "0,1" rbitfld.long 0x0 17. "DBCT,Long/short debounce time" "0,1" rbitfld.long 0x0 16. "CIDSTS,Connector ID status" "0,1" bitfld.long 0x0 12. "EHEN,Embedded host enable" "0,1" newline bitfld.long 0x0 11. "DHNPEN,Device HNP enabled" "0,1" bitfld.long 0x0 10. "HSHNPEN,Host set HNP enable" "0,1" bitfld.long 0x0 9. "HNPRQ,HNP request" "0,1" rbitfld.long 0x0 8. "HNGSCS,Host negotiation success" "0,1" bitfld.long 0x0 1. "SRQ,Session request" "0,1" newline rbitfld.long 0x0 0. "SRQSCS,Session request success" "0,1" line.long 0x4 "OTG_HS_GOTGINT,OTG_HS interrupt register" bitfld.long 0x4 20. "IDCHNG,ID input pin changed" "0,1" bitfld.long 0x4 19. "DBCDNE,Debounce done" "0,1" bitfld.long 0x4 18. "ADTOCHG,A-device timeout change" "0,1" bitfld.long 0x4 17. "HNGDET,Host negotiation detected" "0,1" bitfld.long 0x4 9. "HNSSCHG,Host negotiation success status" "0,1" newline bitfld.long 0x4 8. "SRSSCHG,Session request success status" "0,1" bitfld.long 0x4 2. "SEDET,Session end detected" "0,1" line.long 0x8 "OTG_HS_GAHBCFG,OTG_HS AHB configuration" bitfld.long 0x8 8. "PTXFELVL,Periodic TxFIFO empty" "0,1" bitfld.long 0x8 7. "TXFELVL,TxFIFO empty level" "0,1" bitfld.long 0x8 5. "DMAEN,DMA enable" "0,1" hexmask.long.byte 0x8 1.--4. 1. "HBSTLEN,Burst length/type" bitfld.long 0x8 0. "GINT,Global interrupt mask" "0,1" line.long 0xC "OTG_HS_GUSBCFG,OTG_HS USB configuration" bitfld.long 0xC 30. "FDMOD,Forced peripheral mode" "0,1" bitfld.long 0xC 29. "FHMOD,Forced host mode" "0,1" bitfld.long 0xC 25. "ULPIIPD,ULPI interface protect" "0,1" bitfld.long 0xC 24. "PTCI,Indicator pass through" "0,1" bitfld.long 0xC 23. "PCCI,Indicator complement" "0,1" newline bitfld.long 0xC 22. "TSDPS,TermSel DLine pulsing" "0,1" bitfld.long 0xC 21. "ULPIEVBUSI,ULPI external VBUS" "0,1" bitfld.long 0xC 20. "ULPIEVBUSD,ULPI External VBUS Drive" "0,1" bitfld.long 0xC 19. "ULPICSM,ULPI Clock SuspendM" "0,1" bitfld.long 0xC 18. "ULPIAR,ULPI Auto-resume" "0,1" newline bitfld.long 0xC 17. "ULPIFSLS,ULPI FS/LS select" "0,1" bitfld.long 0xC 15. "PHYLPCS,PHY Low-power clock select" "0,1" hexmask.long.byte 0xC 10.--13. 1. "TRDT,USB turnaround time" bitfld.long 0xC 9. "HNPCAP,HNP-capable" "0,1" bitfld.long 0xC 8. "SRPCAP,SRP-capable" "0,1" newline bitfld.long 0xC 6. "PHYSEL,USB 2.0 high-speed ULPI PHY or USB 1.1" "0,1" hexmask.long.byte 0xC 0.--3. 1. "TOCAL,FS timeout calibration" line.long 0x10 "OTG_HS_GRSTCTL,OTG_HS reset register" rbitfld.long 0x10 31. "AHBIDL,AHB master idle" "0,1" rbitfld.long 0x10 30. "DMAREQ,DMA request signal enabled for USB OTG" "0,1" hexmask.long.byte 0x10 6.--10. 1. "TXFNUM,TxFIFO number" bitfld.long 0x10 5. "TXFFLSH,TxFIFO flush" "0,1" bitfld.long 0x10 4. "RXFFLSH,RxFIFO flush" "0,1" newline bitfld.long 0x10 2. "FCRST,Host frame counter reset" "0,1" bitfld.long 0x10 1. "HSRST,HCLK soft reset" "0,1" bitfld.long 0x10 0. "CSRST,Core soft reset" "0,1" line.long 0x14 "OTG_HS_GINTSTS,OTG_HS core interrupt register" bitfld.long 0x14 31. "WKUINT,Resume/remote wakeup detected" "0,1" bitfld.long 0x14 30. "SRQINT,Session request/new session detected" "0,1" bitfld.long 0x14 29. "DISCINT,Disconnect detected" "0,1" bitfld.long 0x14 28. "CIDSCHG,Connector ID status change" "0,1" rbitfld.long 0x14 26. "PTXFE,Periodic TxFIFO empty" "0,1" newline rbitfld.long 0x14 25. "HCINT,Host channels interrupt" "0,1" rbitfld.long 0x14 24. "HPRTINT,Host port interrupt" "0,1" bitfld.long 0x14 22. "DATAFSUSP,Data fetch suspended" "0,1" bitfld.long 0x14 21. "PXFR_INCOMPISOOUT,Incomplete periodic" "0,1" bitfld.long 0x14 20. "IISOIXFR,Incomplete isochronous IN" "0,1" newline rbitfld.long 0x14 19. "OEPINT,OUT endpoint interrupt" "0,1" rbitfld.long 0x14 18. "IEPINT,IN endpoint interrupt" "0,1" bitfld.long 0x14 15. "EOPF,End of periodic frame" "0,1" bitfld.long 0x14 14. "ISOODRP,Isochronous OUT packet dropped" "0,1" bitfld.long 0x14 13. "ENUMDNE,Enumeration done" "0,1" newline bitfld.long 0x14 12. "USBRST,USB reset" "0,1" bitfld.long 0x14 11. "USBSUSP,USB suspend" "0,1" bitfld.long 0x14 10. "ESUSP,Early suspend" "0,1" rbitfld.long 0x14 7. "BOUTNAKEFF,Global OUT NAK effective" "0,1" rbitfld.long 0x14 6. "GINAKEFF,Global IN nonperiodic NAK" "0,1" newline rbitfld.long 0x14 5. "NPTXFE,Nonperiodic TxFIFO empty" "0,1" rbitfld.long 0x14 4. "RXFLVL,RxFIFO nonempty" "0,1" bitfld.long 0x14 3. "SOF,Start of frame" "0,1" rbitfld.long 0x14 2. "OTGINT,OTG interrupt" "0,1" bitfld.long 0x14 1. "MMIS,Mode mismatch interrupt" "0,1" newline rbitfld.long 0x14 0. "CMOD,Current mode of operation" "0,1" line.long 0x18 "OTG_HS_GINTMSK,OTG_HS interrupt mask register" bitfld.long 0x18 31. "WUIM,Resume/remote wakeup detected interrupt" "0,1" bitfld.long 0x18 30. "SRQIM,Session request/new session detected" "0,1" bitfld.long 0x18 29. "DISCINT,Disconnect detected interrupt" "0,1" bitfld.long 0x18 28. "CIDSCHGM,Connector ID status change" "0,1" bitfld.long 0x18 27. "LPMINTM,LPM interrupt mask" "0,1" newline bitfld.long 0x18 26. "PTXFEM,Periodic TxFIFO empty mask" "0,1" bitfld.long 0x18 25. "HCIM,Host channels interrupt" "0,1" rbitfld.long 0x18 24. "PRTIM,Host port interrupt mask" "0,1" bitfld.long 0x18 23. "RSTDE,Reset detected interrupt" "0,1" bitfld.long 0x18 22. "FSUSPM,Data fetch suspended mask" "0,1" newline bitfld.long 0x18 21. "PXFRM_IISOOXFRM,Incomplete periodic transfer" "0,1" bitfld.long 0x18 20. "IISOIXFRM,Incomplete isochronous IN transfer" "0,1" bitfld.long 0x18 19. "OEPINT,OUT endpoints interrupt" "0,1" bitfld.long 0x18 18. "IEPINT,IN endpoints interrupt" "0,1" bitfld.long 0x18 15. "EOPFM,End of periodic frame interrupt" "0,1" newline bitfld.long 0x18 14. "ISOODRPM,Isochronous OUT packet dropped interrupt" "0,1" bitfld.long 0x18 13. "ENUMDNEM,Enumeration done mask" "0,1" bitfld.long 0x18 12. "USBRST,USB reset mask" "0,1" bitfld.long 0x18 11. "USBSUSPM,USB suspend mask" "0,1" bitfld.long 0x18 10. "ESUSPM,Early suspend mask" "0,1" newline bitfld.long 0x18 7. "GONAKEFFM,Global OUT NAK effective" "0,1" bitfld.long 0x18 6. "GINAKEFFM,Global nonperiodic IN NAK effective" "0,1" bitfld.long 0x18 5. "NPTXFEM,Nonperiodic TxFIFO empty" "0,1" bitfld.long 0x18 4. "RXFLVLM,Receive FIFO nonempty mask" "0,1" bitfld.long 0x18 3. "SOFM,Start of frame mask" "0,1" newline bitfld.long 0x18 2. "OTGINT,OTG interrupt mask" "0,1" bitfld.long 0x18 1. "MMISM,Mode mismatch interrupt" "0,1" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Host,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "CHNUM,Channel number" line.long 0x4 "OTG_HS_GRXSTSP_Host,OTG_HS status read and pop register (host" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "CHNUM,Channel number" group.long 0x24++0x7 line.long 0x0 "OTG_HS_GRXFSIZ,OTG_HS Receive FIFO size" hexmask.long.word 0x0 0.--15. 1. "RXFD,RxFIFO depth" line.long 0x4 "OTG_HS_HNPTXFSIZ_Host,OTG_HS nonperiodic transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "NPTXFD,Nonperiodic TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "NPTXFSA,Nonperiodic transmit RAM start" group.long 0x28++0x3 line.long 0x0 "OTG_HS_DIEPTXF0_Device,Endpoint 0 transmit FIFO size (peripheral" hexmask.long.word 0x0 16.--31. 1. "TX0FD,Endpoint 0 TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "TX0FSA,Endpoint 0 transmit RAM start" rgroup.long 0x2C++0x3 line.long 0x0 "OTG_HS_GNPTXSTS,OTG_HS nonperiodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--30. 1. "NPTXQTOP,Top of the nonperiodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "NPTQXSAV,Nonperiodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "NPTXFSAV,Nonperiodic TxFIFO space" group.long 0x38++0x7 line.long 0x0 "OTG_HS_GCCFG,OTG_HS general core configuration" bitfld.long 0x0 21. "VBDEN,USB VBUS detection enable" "0,1" bitfld.long 0x0 20. "SDEN,Secondary detection (SD) mode" "0,1" bitfld.long 0x0 19. "PDEN,Primary detection (PD) mode" "0,1" bitfld.long 0x0 18. "DCDEN,Data contact detection (DCD) mode" "0,1" bitfld.long 0x0 17. "BCDEN,Battery charging detector (BCD)" "0,1" newline bitfld.long 0x0 16. "PWRDWN,Power down" "0,1" bitfld.long 0x0 3. "PS2DET,DM pull-up detection" "0,1" bitfld.long 0x0 2. "SDET,Secondary detection (SD)" "0,1" bitfld.long 0x0 1. "PDET,Primary detection (PD)" "0,1" bitfld.long 0x0 0. "DCDET,Data contact detection (DCD)" "0,1" line.long 0x4 "OTG_HS_CID,OTG_HS core ID register" hexmask.long 0x4 0.--31. 1. "PRODUCT_ID,Product ID field" group.long 0x100++0x23 line.long 0x0 "OTG_HS_HPTXFSIZ,OTG_HS Host periodic transmit FIFO size" hexmask.long.word 0x0 16.--31. 1. "PTXFD,Host periodic TxFIFO depth" hexmask.long.word 0x0 0.--15. 1. "PTXSA,Host periodic TxFIFO start" line.long 0x4 "OTG_HS_DIEPTXF1,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x4 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x4 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x8 "OTG_HS_DIEPTXF2,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x8 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x8 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0xC "OTG_HS_DIEPTXF3,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0xC 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0xC 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x10 "OTG_HS_DIEPTXF4,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x10 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x10 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x14 "OTG_HS_DIEPTXF5,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x14 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x14 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x18 "OTG_HS_DIEPTXF6,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x18 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x18 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x1C "OTG_HS_DIEPTXF7,OTG_HS device IN endpoint transmit FIFO size" hexmask.long.word 0x1C 16.--31. 1. "INEPTXFD,IN endpoint TxFIFO depth" hexmask.long.word 0x1C 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start" line.long 0x20 "OTG_DIEPTXF8," hexmask.long.word 0x20 16.--31. 1. "INEPTXFD,IN endpoint Tx FIFO depth" hexmask.long.word 0x20 0.--15. 1. "INEPTXSA,IN endpoint FIFOx transmit RAM start address" rgroup.long 0x1C++0x7 line.long 0x0 "OTG_HS_GRXSTSR_Device,OTG_HS Receive status debug read register" hexmask.long.byte 0x0 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x0 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x0 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x0 0.--3. 1. "EPNUM,Endpoint number" line.long 0x4 "OTG_HS_GRXSTSP_Device,OTG_HS status read and pop register" hexmask.long.byte 0x4 21.--24. 1. "FRMNUM,Frame number" hexmask.long.byte 0x4 17.--20. 1. "PKTSTS,Packet status" bitfld.long 0x4 15.--16. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x4 4.--14. 1. "BCNT,Byte count" hexmask.long.byte 0x4 0.--3. 1. "EPNUM,Endpoint number" group.long 0x54++0x3 line.long 0x0 "OTG_HS_GLPMCFG,OTG core LPM configuration" bitfld.long 0x0 28. "ENBESL,Enable best effort service" "0,1" hexmask.long.byte 0x0 25.--28. 1. "LPMRCNTSTS,LPM retry count status" bitfld.long 0x0 24. "SNDLPM,Send LPM transaction" "0,1" hexmask.long.byte 0x0 21.--24. 1. "LPMRCNT,LPM retry count" hexmask.long.byte 0x0 17.--20. 1. "LPMCHIDX,LPM Channel Index" newline rbitfld.long 0x0 16. "L1RSMOK,Sleep State Resume OK" "0,1" rbitfld.long 0x0 15. "SLPSTS,Port sleep status" "0,1" rbitfld.long 0x0 13.--14. "LPMRST,LPM response" "0,1,2,3" bitfld.long 0x0 12. "L1DSEN,L1 deep sleep enable" "0,1" hexmask.long.byte 0x0 8.--11. 1. "BESLTHRS,BESL threshold" newline bitfld.long 0x0 7. "L1SSEN,L1 Shallow Sleep enable" "0,1" rbitfld.long 0x0 6. "REMWAKE,bRemoteWake value" "0,1" hexmask.long.byte 0x0 2.--5. 1. "BESL,Best effort service" bitfld.long 0x0 1. "LPMACK,LPM token acknowledge" "0,1" bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1" tree.end endif tree "OTG1_HS_HOST" base ad:0x40040400 group.long 0x0++0x7 line.long 0x0 "OTG_HS_HCFG,OTG_HS host configuration" rbitfld.long 0x0 2. "FSLSS,FS- and LS-only support" "0,1" bitfld.long 0x0 0.--1. "FSLSPCS,FS/LS PHY clock select" "0,1,2,3" line.long 0x4 "OTG_HS_HFIR,OTG_HS Host frame interval" hexmask.long.word 0x4 0.--15. 1. "FRIVL,Frame interval" rgroup.long 0x8++0x3 line.long 0x0 "OTG_HS_HFNUM,OTG_HS host frame number/frame time" hexmask.long.word 0x0 16.--31. 1. "FTREM,Frame time remaining" hexmask.long.word 0x0 0.--15. 1. "FRNUM,Frame number" group.long 0x10++0x3 line.long 0x0 "OTG_HS_HPTXSTS,OTG_HS_Host periodic transmit FIFO/queue" hexmask.long.byte 0x0 24.--31. 1. "PTXQTOP,Top of the periodic transmit request" hexmask.long.byte 0x0 16.--23. 1. "PTXQSAV,Periodic transmit request queue space" hexmask.long.word 0x0 0.--15. 1. "PTXFSAVL,Periodic transmit data FIFO space" rgroup.long 0x14++0x3 line.long 0x0 "OTG_HS_HAINT,OTG_HS Host all channels interrupt" hexmask.long.word 0x0 0.--15. 1. "HAINT,Channel interrupts" group.long 0x18++0x3 line.long 0x0 "OTG_HS_HAINTMSK,OTG_HS host all channels interrupt mask" hexmask.long.word 0x0 0.--15. 1. "HAINTM,Channel interrupt mask" group.long 0x40++0x3 line.long 0x0 "OTG_HS_HPRT,OTG_HS host port control and status" rbitfld.long 0x0 17.--18. "PSPD,Port speed" "0,1,2,3" hexmask.long.byte 0x0 13.--16. 1. "PTCTL,Port test control" bitfld.long 0x0 12. "PPWR,Port power" "0,1" rbitfld.long 0x0 10.--11. "PLSTS,Port line status" "0,1,2,3" bitfld.long 0x0 8. "PRST,Port reset" "0,1" bitfld.long 0x0 7. "PSUSP,Port suspend" "0,1" bitfld.long 0x0 6. "PRES,Port resume" "0,1" newline bitfld.long 0x0 5. "POCCHNG,Port overcurrent change" "0,1" rbitfld.long 0x0 4. "POCA,Port overcurrent active" "0,1" bitfld.long 0x0 3. "PENCHNG,Port enable/disable change" "0,1" bitfld.long 0x0 2. "PENA,Port enable" "0,1" bitfld.long 0x0 1. "PCDET,Port connect detected" "0,1" rbitfld.long 0x0 0. "PCSTS,Port connect status" "0,1" group.long 0x100++0x3 line.long 0x0 "OTG_HS_HCCHAR0,OTG_HS host channel-0 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x120++0x3 line.long 0x0 "OTG_HS_HCCHAR1,OTG_HS host channel-1 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x140++0x3 line.long 0x0 "OTG_HS_HCCHAR2,OTG_HS host channel-2 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x160++0x3 line.long 0x0 "OTG_HS_HCCHAR3,OTG_HS host channel-3 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x180++0x3 line.long 0x0 "OTG_HS_HCCHAR4,OTG_HS host channel-4 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1A0++0x3 line.long 0x0 "OTG_HS_HCCHAR5,OTG_HS host channel-5 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1C0++0x3 line.long 0x0 "OTG_HS_HCCHAR6,OTG_HS host channel-6 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1E0++0x3 line.long 0x0 "OTG_HS_HCCHAR7,OTG_HS host channel-7 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x200++0x3 line.long 0x0 "OTG_HS_HCCHAR8,OTG_HS host channel-8 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x220++0x3 line.long 0x0 "OTG_HS_HCCHAR9,OTG_HS host channel-9 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x240++0x3 line.long 0x0 "OTG_HS_HCCHAR10,OTG_HS host channel-10 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x260++0x3 line.long 0x0 "OTG_HS_HCCHAR11,OTG_HS host channel-11 characteristics" bitfld.long 0x0 31. "CHENA,Channel enable" "0,1" bitfld.long 0x0 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x0 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x0 22.--28. 1. "DAD,Device address" bitfld.long 0x0 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x0 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x0 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x0 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x104++0x3 line.long 0x0 "OTG_HS_HCSPLT0,OTG_HS host channel-0 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x124++0x3 line.long 0x0 "OTG_HS_HCSPLT1,OTG_HS host channel-1 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x144++0x3 line.long 0x0 "OTG_HS_HCSPLT2,OTG_HS host channel-2 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x164++0x3 line.long 0x0 "OTG_HS_HCSPLT3,OTG_HS host channel-3 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x184++0x3 line.long 0x0 "OTG_HS_HCSPLT4,OTG_HS host channel-4 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x1A4++0x3 line.long 0x0 "OTG_HS_HCSPLT5,OTG_HS host channel-5 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x1C4++0x3 line.long 0x0 "OTG_HS_HCSPLT6,OTG_HS host channel-6 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x1E4++0x3 line.long 0x0 "OTG_HS_HCSPLT7,OTG_HS host channel-7 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x204++0x3 line.long 0x0 "OTG_HS_HCSPLT8,OTG_HS host channel-8 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x224++0x3 line.long 0x0 "OTG_HS_HCSPLT9,OTG_HS host channel-9 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x244++0x3 line.long 0x0 "OTG_HS_HCSPLT10,OTG_HS host channel-10 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x264++0x3 line.long 0x0 "OTG_HS_HCSPLT11,OTG_HS host channel-11 split control" bitfld.long 0x0 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x0 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x0 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x0 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x0 0.--6. 1. "PRTADDR,Port address" group.long 0x108++0x3 line.long 0x0 "OTG_HS_HCINT0,OTG_HS host channel-11 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x128++0x3 line.long 0x0 "OTG_HS_HCINT1,OTG_HS host channel-1 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x148++0x3 line.long 0x0 "OTG_HS_HCINT2,OTG_HS host channel-2 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x168++0x3 line.long 0x0 "OTG_HS_HCINT3,OTG_HS host channel-3 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x188++0x3 line.long 0x0 "OTG_HS_HCINT4,OTG_HS host channel-4 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1A8++0x3 line.long 0x0 "OTG_HS_HCINT5,OTG_HS host channel-5 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1C8++0x3 line.long 0x0 "OTG_HS_HCINT6,OTG_HS host channel-6 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1E8++0x3 line.long 0x0 "OTG_HS_HCINT7,OTG_HS host channel-7 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x208++0x3 line.long 0x0 "OTG_HS_HCINT8,OTG_HS host channel-8 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x228++0x3 line.long 0x0 "OTG_HS_HCINT9,OTG_HS host channel-9 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x248++0x3 line.long 0x0 "OTG_HS_HCINT10,OTG_HS host channel-10 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x268++0x3 line.long 0x0 "OTG_HS_HCINT11,OTG_HS host channel-11 interrupt" bitfld.long 0x0 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x0 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x0 8. "BBERR,Babble error" "0,1" bitfld.long 0x0 7. "TXERR,Transaction error" "0,1" bitfld.long 0x0 6. "NYET,Response received" "0,1" bitfld.long 0x0 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x0 3. "STALL,STALL response received" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHH,Channel halted" "0,1" bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x10C++0x3 line.long 0x0 "OTG_HS_HCINTMSK0,OTG_HS host channel-11 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x12C++0x3 line.long 0x0 "OTG_HS_HCINTMSK1,OTG_HS host channel-1 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x14C++0x3 line.long 0x0 "OTG_HS_HCINTMSK2,OTG_HS host channel-2 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x16C++0x3 line.long 0x0 "OTG_HS_HCINTMSK3,OTG_HS host channel-3 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x18C++0x3 line.long 0x0 "OTG_HS_HCINTMSK4,OTG_HS host channel-4 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x1AC++0x3 line.long 0x0 "OTG_HS_HCINTMSK5,OTG_HS host channel-5 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x1CC++0x3 line.long 0x0 "OTG_HS_HCINTMSK6,OTG_HS host channel-6 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x1EC++0x3 line.long 0x0 "OTG_HS_HCINTMSK7,OTG_HS host channel-7 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x20C++0x3 line.long 0x0 "OTG_HS_HCINTMSK8,OTG_HS host channel-8 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x22C++0x3 line.long 0x0 "OTG_HS_HCINTMSK9,OTG_HS host channel-9 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x24C++0x3 line.long 0x0 "OTG_HS_HCINTMSK10,OTG_HS host channel-10 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x26C++0x3 line.long 0x0 "OTG_HS_HCINTMSK11,OTG_HS host channel-11 interrupt mask" bitfld.long 0x0 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x0 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x0 8. "BBERRM,Babble error mask" "0,1" bitfld.long 0x0 7. "TXERRM,Transaction error mask" "0,1" bitfld.long 0x0 6. "NYET,response received interrupt" "0,1" bitfld.long 0x0 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x0 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x0 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x0 2. "AHBERR,AHB error" "0,1" bitfld.long 0x0 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed mask" "0,1" group.long 0x110++0x3 line.long 0x0 "OTG_HS_HCTSIZ0,OTG_HS host channel-11 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x130++0x3 line.long 0x0 "OTG_HS_HCTSIZ1,OTG_HS host channel-1 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x150++0x3 line.long 0x0 "OTG_HS_HCTSIZ2,OTG_HS host channel-2 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x170++0x3 line.long 0x0 "OTG_HS_HCTSIZ3,OTG_HS host channel-3 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x190++0x3 line.long 0x0 "OTG_HS_HCTSIZ4,OTG_HS host channel-4 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1B0++0x3 line.long 0x0 "OTG_HS_HCTSIZ5,OTG_HS host channel-5 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1D0++0x3 line.long 0x0 "OTG_HS_HCTSIZ6,OTG_HS host channel-6 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1F0++0x3 line.long 0x0 "OTG_HS_HCTSIZ7,OTG_HS host channel-7 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x210++0x3 line.long 0x0 "OTG_HS_HCTSIZ8,OTG_HS host channel-8 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x230++0x3 line.long 0x0 "OTG_HS_HCTSIZ9,OTG_HS host channel-9 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x250++0x3 line.long 0x0 "OTG_HS_HCTSIZ10,OTG_HS host channel-10 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x270++0x3 line.long 0x0 "OTG_HS_HCTSIZ11,OTG_HS host channel-11 transfer size" bitfld.long 0x0 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x114++0x3 line.long 0x0 "OTG_HS_HCDMA0,OTG_HS host channel-0 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x134++0x3 line.long 0x0 "OTG_HS_HCDMA1,OTG_HS host channel-1 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x154++0x3 line.long 0x0 "OTG_HS_HCDMA2,OTG_HS host channel-2 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x174++0x3 line.long 0x0 "OTG_HS_HCDMA3,OTG_HS host channel-3 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x194++0x3 line.long 0x0 "OTG_HS_HCDMA4,OTG_HS host channel-4 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x1B4++0x3 line.long 0x0 "OTG_HS_HCDMA5,OTG_HS host channel-5 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x1D4++0x3 line.long 0x0 "OTG_HS_HCDMA6,OTG_HS host channel-6 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x1F4++0x3 line.long 0x0 "OTG_HS_HCDMA7,OTG_HS host channel-7 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x214++0x3 line.long 0x0 "OTG_HS_HCDMA8,OTG_HS host channel-8 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x234++0x3 line.long 0x0 "OTG_HS_HCDMA9,OTG_HS host channel-9 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x254++0x3 line.long 0x0 "OTG_HS_HCDMA10,OTG_HS host channel-10 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x274++0x63 line.long 0x0 "OTG_HS_HCDMA11,OTG_HS host channel-11 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" line.long 0x4 "OTG_HS_HCCHAR12,OTG_HS host channel-12 characteristics" bitfld.long 0x4 31. "CHENA,Channel enable" "0,1" bitfld.long 0x4 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x4 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x4 22.--28. 1. "DAD,Device address" bitfld.long 0x4 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x4 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x4 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x4 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x4 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x8 "OTG_HS_HCSPLT12,OTG_HS host channel-12 split control" bitfld.long 0x8 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x8 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x8 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x8 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x8 0.--6. 1. "PRTADDR,Port address" line.long 0xC "OTG_HS_HCINT12,OTG_HS host channel-12 interrupt" bitfld.long 0xC 10. "DTERR,Data toggle error" "0,1" bitfld.long 0xC 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0xC 8. "BBERR,Babble error" "0,1" bitfld.long 0xC 7. "TXERR,Transaction error" "0,1" bitfld.long 0xC 6. "NYET,Response received" "0,1" bitfld.long 0xC 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0xC 4. "NAK,NAK response received" "0,1" newline bitfld.long 0xC 3. "STALL,STALL response received" "0,1" bitfld.long 0xC 2. "AHBERR,AHB error" "0,1" bitfld.long 0xC 1. "CHH,Channel halted" "0,1" bitfld.long 0xC 0. "XFRC,Transfer completed" "0,1" line.long 0x10 "OTG_HS_HCINTMSK12,OTG_HS host channel-12 interrupt mask" bitfld.long 0x10 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x10 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x10 8. "BBERRM,Babble error" "0,1" bitfld.long 0x10 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x10 6. "NYET,Response received" "0,1" bitfld.long 0x10 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x10 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x10 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x10 2. "AHBERR,AHB error" "0,1" bitfld.long 0x10 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x10 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x14 "OTG_HS_HCTSIZ12,OTG_HS host channel-12 transfer size" bitfld.long 0x14 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x14 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x14 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x18 "OTG_HS_HCDMA12,OTG_HS host channel-12 DMA address" hexmask.long 0x18 0.--31. 1. "DMAADDR,DMA address" line.long 0x1C "OTG_HS_HCCHAR13,OTG_HS host channel-13 characteristics" bitfld.long 0x1C 31. "CHENA,Channel enable" "0,1" bitfld.long 0x1C 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x1C 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x1C 22.--28. 1. "DAD,Device address" bitfld.long 0x1C 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x1C 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x1C 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x1C 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x1C 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x1C 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x20 "OTG_HS_HCSPLT13,OTG_HS host channel-13 split control" bitfld.long 0x20 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x20 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x20 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x20 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x20 0.--6. 1. "PRTADDR,Port address" line.long 0x24 "OTG_HS_HCINT13,OTG_HS host channel-13 interrupt" bitfld.long 0x24 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x24 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x24 8. "BBERR,Babble error" "0,1" bitfld.long 0x24 7. "TXERR,Transaction error" "0,1" bitfld.long 0x24 6. "NYET,Response received" "0,1" bitfld.long 0x24 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x24 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x24 3. "STALL,STALL response received" "0,1" bitfld.long 0x24 2. "AHBERR,AHB error" "0,1" bitfld.long 0x24 1. "CHH,Channel halted" "0,1" bitfld.long 0x24 0. "XFRC,Transfer completed" "0,1" line.long 0x28 "OTG_HS_HCINTMSK13,OTG_HS host channel-13 interrupt mask" bitfld.long 0x28 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x28 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x28 8. "BBERRM,Babble error" "0,1" bitfld.long 0x28 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x28 6. "NYET,Response received" "0,1" bitfld.long 0x28 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x28 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x28 3. "STALLM,STALLM response received interrupt" "0,1" bitfld.long 0x28 2. "AHBERR,AHB error" "0,1" bitfld.long 0x28 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x28 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x2C "OTG_HS_HCTSIZ13,OTG_HS host channel-13 transfer size" bitfld.long 0x2C 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x2C 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x2C 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x30 "OTG_HS_HCDMA13,OTG_HS host channel-13 DMA address" hexmask.long 0x30 0.--31. 1. "DMAADDR,DMA address" line.long 0x34 "OTG_HS_HCCHAR14,OTG_HS host channel-14 characteristics" bitfld.long 0x34 31. "CHENA,Channel enable" "0,1" bitfld.long 0x34 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x34 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x34 22.--28. 1. "DAD,Device address" bitfld.long 0x34 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x34 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x34 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x34 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x34 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x34 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x38 "OTG_HS_HCSPLT14,OTG_HS host channel-14 split control" bitfld.long 0x38 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x38 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x38 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x38 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x38 0.--6. 1. "PRTADDR,Port address" line.long 0x3C "OTG_HS_HCINT14,OTG_HS host channel-14 interrupt" bitfld.long 0x3C 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x3C 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x3C 8. "BBERR,Babble error" "0,1" bitfld.long 0x3C 7. "TXERR,Transaction error" "0,1" bitfld.long 0x3C 6. "NYET,Response received" "0,1" bitfld.long 0x3C 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x3C 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x3C 3. "STALL,STALL response received" "0,1" bitfld.long 0x3C 2. "AHBERR,AHB error" "0,1" bitfld.long 0x3C 1. "CHH,Channel halted" "0,1" bitfld.long 0x3C 0. "XFRC,Transfer completed" "0,1" line.long 0x40 "OTG_HS_HCINTMSK14,OTG_HS host channel-14 interrupt mask" bitfld.long 0x40 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x40 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x40 8. "BBERRM,Babble error" "0,1" bitfld.long 0x40 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x40 6. "NYET,Response received" "0,1" bitfld.long 0x40 5. "ACKM,ACKM response received/transmitted" "0,1" bitfld.long 0x40 4. "NAKM,NAKM response received interrupt" "0,1" newline bitfld.long 0x40 3. "STALLM,STALL response received interrupt" "0,1" bitfld.long 0x40 2. "AHBERR,AHB error" "0,1" bitfld.long 0x40 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x40 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x44 "OTG_HS_HCTSIZ14,OTG_HS host channel-14 transfer size" bitfld.long 0x44 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x44 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x44 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x48 "OTG_HS_HCDMA14,OTG_HS host channel-14 DMA address" hexmask.long 0x48 0.--31. 1. "DMAADDR,DMA address" line.long 0x4C "OTG_HS_HCCHAR15,OTG_HS host channel-15 characteristics" bitfld.long 0x4C 31. "CHENA,Channel enable" "0,1" bitfld.long 0x4C 30. "CHDIS,Channel disable" "0,1" bitfld.long 0x4C 29. "ODDFRM,Odd frame" "0,1" hexmask.long.byte 0x4C 22.--28. 1. "DAD,Device address" bitfld.long 0x4C 20.--21. "MC,Multi Count (MC) / Error Count" "0,1,2,3" bitfld.long 0x4C 18.--19. "EPTYP,Endpoint type" "0,1,2,3" bitfld.long 0x4C 17. "LSDEV,Low-speed device" "0,1" newline bitfld.long 0x4C 15. "EPDIR,Endpoint direction" "0,1" hexmask.long.byte 0x4C 11.--14. 1. "EPNUM,Endpoint number" hexmask.long.word 0x4C 0.--10. 1. "MPSIZ,Maximum packet size" line.long 0x50 "OTG_HS_HCSPLT15,OTG_HS host channel-15 split control" bitfld.long 0x50 31. "SPLITEN,Split enable" "0,1" bitfld.long 0x50 16. "COMPLSPLT,Do complete split" "0,1" bitfld.long 0x50 14.--15. "XACTPOS,XACTPOS" "0,1,2,3" hexmask.long.byte 0x50 7.--13. 1. "HUBADDR,Hub address" hexmask.long.byte 0x50 0.--6. 1. "PRTADDR,Port address" line.long 0x54 "OTG_HS_HCINT15,OTG_HS host channel-15 interrupt" bitfld.long 0x54 10. "DTERR,Data toggle error" "0,1" bitfld.long 0x54 9. "FRMOR,Frame overrun" "0,1" bitfld.long 0x54 8. "BBERR,Babble error" "0,1" bitfld.long 0x54 7. "TXERR,Transaction error" "0,1" bitfld.long 0x54 6. "NYET,Response received" "0,1" bitfld.long 0x54 5. "ACK,ACK response received/transmitted" "0,1" bitfld.long 0x54 4. "NAK,NAK response received" "0,1" newline bitfld.long 0x54 3. "STALL,STALL response received" "0,1" bitfld.long 0x54 2. "AHBERR,AHB error" "0,1" bitfld.long 0x54 1. "CHH,Channel halted" "0,1" bitfld.long 0x54 0. "XFRC,Transfer completed" "0,1" line.long 0x58 "OTG_HS_HCINTMSK15,OTG_HS host channel-15 interrupt mask" bitfld.long 0x58 10. "DTERRM,Data toggle error mask" "0,1" bitfld.long 0x58 9. "FRMORM,Frame overrun mask" "0,1" bitfld.long 0x58 8. "BBERRM,Babble error" "0,1" bitfld.long 0x58 7. "TXERRM,Transaction error" "0,1" bitfld.long 0x58 6. "NYET,Response received" "0,1" bitfld.long 0x58 5. "ACKM,ACK response received/transmitted" "0,1" bitfld.long 0x58 4. "NAKM,NAK response received interrupt" "0,1" newline bitfld.long 0x58 3. "STALL,STALL response received interrupt" "0,1" bitfld.long 0x58 2. "AHBERR,AHB error" "0,1" bitfld.long 0x58 1. "CHHM,Channel halted mask" "0,1" bitfld.long 0x58 0. "XFRCM,Transfer completed mask" "0,1" line.long 0x5C "OTG_HS_HCTSIZ15,OTG_HS host channel-15 transfer size" bitfld.long 0x5C 29.--30. "DPID,Data PID" "0,1,2,3" hexmask.long.word 0x5C 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x5C 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x60 "OTG_HS_HCDMA15,OTG_HS host channel-15 DMA address" hexmask.long 0x60 0.--31. 1. "DMAADDR,DMA address" tree.end sif (cpuis("STM32H7B3*")) tree "OTG1_HS_DEVICE" base ad:0x40040800 group.long 0x0++0x7 line.long 0x0 "OTG_HS_DCFG,OTG_HS device configuration" bitfld.long 0x0 24.--25. "PERSCHIVL,Periodic scheduling" "0,1,2,3" bitfld.long 0x0 11.--12. "PFIVL,Periodic (micro)frame" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. "DAD,Device address" bitfld.long 0x0 2. "NZLSOHSK,Nonzero-length status OUT" "0,1" bitfld.long 0x0 0.--1. "DSPD,Device speed" "0,1,2,3" line.long 0x4 "OTG_HS_DCTL,OTG_HS device control register" bitfld.long 0x4 11. "POPRGDNE,Power-on programming done" "0,1" bitfld.long 0x4 10. "CGONAK,Clear global OUT NAK" "0,1" bitfld.long 0x4 9. "SGONAK,Set global OUT NAK" "0,1" bitfld.long 0x4 8. "CGINAK,Clear global IN NAK" "0,1" bitfld.long 0x4 7. "SGINAK,Set global IN NAK" "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "TCTL,Test control" rbitfld.long 0x4 3. "GONSTS,Global OUT NAK status" "0,1" rbitfld.long 0x4 2. "GINSTS,Global IN NAK status" "0,1" bitfld.long 0x4 1. "SDIS,Soft disconnect" "0,1" bitfld.long 0x4 0. "RWUSIG,Remote wakeup signaling" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "OTG_HS_DSTS,OTG_HS device status register" hexmask.long.word 0x0 8.--21. 1. "FNSOF,Frame number of the received" bitfld.long 0x0 3. "EERR,Erratic error" "0,1" bitfld.long 0x0 1.--2. "ENUMSPD,Enumerated speed" "0,1,2,3" bitfld.long 0x0 0. "SUSPSTS,Suspend status" "0,1" group.long 0x10++0x7 line.long 0x0 "OTG_HS_DIEPMSK,OTG_HS device IN endpoint common interrupt" bitfld.long 0x0 9. "BIM,BNA interrupt mask" "0,1" bitfld.long 0x0 8. "TXFURM,FIFO underrun mask" "0,1" bitfld.long 0x0 6. "INEPNEM,IN endpoint NAK effective" "0,1" bitfld.long 0x0 5. "INEPNMM,IN token received with EP mismatch" "0,1" bitfld.long 0x0 4. "ITTXFEMSK,IN token received when TxFIFO empty" "0,1" newline bitfld.long 0x0 3. "TOM,Timeout condition mask (nonisochronous" "0,1" bitfld.long 0x0 1. "EPDM,Endpoint disabled interrupt" "0,1" bitfld.long 0x0 0. "XFRCM,Transfer completed interrupt" "0,1" line.long 0x4 "OTG_HS_DOEPMSK,OTG_HS device OUT endpoint common interrupt" bitfld.long 0x4 9. "BOIM,BNA interrupt mask" "0,1" bitfld.long 0x4 8. "OPEM,OUT packet error mask" "0,1" bitfld.long 0x4 6. "B2BSTUP,Back-to-back SETUP packets received" "0,1" bitfld.long 0x4 4. "OTEPDM,OUT token received when endpoint" "0,1" bitfld.long 0x4 3. "STUPM,SETUP phase done mask" "0,1" newline bitfld.long 0x4 1. "EPDM,Endpoint disabled interrupt" "0,1" bitfld.long 0x4 0. "XFRCM,Transfer completed interrupt" "0,1" rgroup.long 0x18++0x3 line.long 0x0 "OTG_HS_DAINT,OTG_HS device all endpoints interrupt" hexmask.long.word 0x0 16.--31. 1. "OEPINT,OUT endpoint interrupt" hexmask.long.word 0x0 0.--15. 1. "IEPINT,IN endpoint interrupt bits" group.long 0x1C++0x3 line.long 0x0 "OTG_HS_DAINTMSK,OTG_HS all endpoints interrupt mask" hexmask.long.word 0x0 16.--31. 1. "OEPM,OUT EP interrupt mask bits" hexmask.long.word 0x0 0.--15. 1. "IEPM,IN EP interrupt mask bits" group.long 0x28++0x17 line.long 0x0 "OTG_HS_DVBUSDIS,OTG_HS device VBUS discharge time" hexmask.long.word 0x0 0.--15. 1. "VBUSDT,Device VBUS discharge time" line.long 0x4 "OTG_HS_DVBUSPULSE,OTG_HS device VBUS pulsing time" hexmask.long.word 0x4 0.--11. 1. "DVBUSP,Device VBUS pulsing time" line.long 0x8 "OTG_HS_DTHRCTL,OTG_HS Device threshold control" bitfld.long 0x8 27. "ARPEN,Arbiter parking enable" "0,1" hexmask.long.word 0x8 17.--25. 1. "RXTHRLEN,Receive threshold length" bitfld.long 0x8 16. "RXTHREN,Receive threshold enable" "0,1" hexmask.long.word 0x8 2.--10. 1. "TXTHRLEN,Transmit threshold length" bitfld.long 0x8 1. "ISOTHREN,ISO IN endpoint threshold" "0,1" newline bitfld.long 0x8 0. "NONISOTHREN,Nonisochronous IN endpoints threshold" "0,1" line.long 0xC "OTG_HS_DIEPEMPMSK,OTG_HS device IN endpoint FIFO empty" hexmask.long.word 0xC 0.--15. 1. "INEPTXFEM,IN EP Tx FIFO empty interrupt mask" line.long 0x10 "OTG_HS_DEACHINT,OTG_HS device each endpoint interrupt" bitfld.long 0x10 17. "OEP1INT,OUT endpoint 1 interrupt" "0,1" bitfld.long 0x10 1. "IEP1INT,IN endpoint 1interrupt bit" "0,1" line.long 0x14 "OTG_HS_DEACHINTMSK,OTG_HS device each endpoint interrupt" bitfld.long 0x14 17. "OEP1INTM,OUT Endpoint 1 interrupt mask" "0,1" bitfld.long 0x14 1. "IEP1INTM,IN Endpoint 1 interrupt mask" "0,1" group.long 0x100++0x3 line.long 0x0 "OTG_HS_DIEPCTL0,OTG device endpoint-0 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x120++0x3 line.long 0x0 "OTG_HS_DIEPCTL1,OTG device endpoint-1 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x140++0x3 line.long 0x0 "OTG_HS_DIEPCTL2,OTG device endpoint-2 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x160++0x3 line.long 0x0 "OTG_HS_DIEPCTL3,OTG device endpoint-3 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x180++0x3 line.long 0x0 "OTG_HS_DIEPCTL4,OTG device endpoint-4 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1A0++0x3 line.long 0x0 "OTG_HS_DIEPCTL5,OTG device endpoint-5 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1C0++0x3 line.long 0x0 "OTG_HS_DIEPCTL6,OTG device endpoint-6 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x1E0++0x3 line.long 0x0 "OTG_HS_DIEPCTL7,OTG device endpoint-7 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" hexmask.long.byte 0x0 22.--25. 1. "TXFNUM,TxFIFO number" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even/odd frame" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x108++0x3 line.long 0x0 "OTG_HS_DIEPINT0,OTG device endpoint-0 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x128++0x3 line.long 0x0 "OTG_HS_DIEPINT1,OTG device endpoint-1 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x148++0x3 line.long 0x0 "OTG_HS_DIEPINT2,OTG device endpoint-2 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x168++0x3 line.long 0x0 "OTG_HS_DIEPINT3,OTG device endpoint-3 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x188++0x3 line.long 0x0 "OTG_HS_DIEPINT4,OTG device endpoint-4 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1A8++0x3 line.long 0x0 "OTG_HS_DIEPINT5,OTG device endpoint-5 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1C8++0x3 line.long 0x0 "OTG_HS_DIEPINT6,OTG device endpoint-6 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x1E8++0x3 line.long 0x0 "OTG_HS_DIEPINT7,OTG device endpoint-7 interrupt" bitfld.long 0x0 13. "NAK,NAK interrupt" "0,1" bitfld.long 0x0 12. "BERR,Babble error interrupt" "0,1" bitfld.long 0x0 11. "PKTDRPSTS,Packet dropped status" "0,1" bitfld.long 0x0 9. "BNA,Buffer not available" "0,1" bitfld.long 0x0 8. "TXFIFOUDRN,Transmit Fifo Underrun" "0,1" newline rbitfld.long 0x0 7. "TXFE,Transmit FIFO empty" "0,1" bitfld.long 0x0 6. "INEPNE,IN endpoint NAK effective" "0,1" bitfld.long 0x0 4. "ITTXFE,IN token received when TxFIFO is" "0,1" bitfld.long 0x0 3. "TOC,Timeout condition" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x110++0x7 line.long 0x0 "OTG_HS_DIEPTSIZ0,OTG_HS device IN endpoint 0 transfer size" bitfld.long 0x0 19.--20. "PKTCNT,Packet count" "0,1,2,3" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_HS_DIEPDMA1,OTG_HS device endpoint-1 DMA address" hexmask.long 0x4 0.--31. 1. "DMAADDR,DMA address" group.long 0x134++0x3 line.long 0x0 "OTG_HS_DIEPDMA2,OTG_HS device endpoint-2 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x154++0x3 line.long 0x0 "OTG_HS_DIEPDMA3,OTG_HS device endpoint-3 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x174++0x3 line.long 0x0 "OTG_HS_DIEPDMA4,OTG_HS device endpoint-4 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" group.long 0x194++0x3 line.long 0x0 "OTG_HS_DIEPDMA5,OTG_HS device endpoint-5 DMA address" hexmask.long 0x0 0.--31. 1. "DMAADDR,DMA address" rgroup.long 0x118++0x3 line.long 0x0 "OTG_HS_DTXFSTS0,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x138++0x3 line.long 0x0 "OTG_HS_DTXFSTS1,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x158++0x3 line.long 0x0 "OTG_HS_DTXFSTS2,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x178++0x3 line.long 0x0 "OTG_HS_DTXFSTS3,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x198++0x3 line.long 0x0 "OTG_HS_DTXFSTS4,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" rgroup.long 0x1B8++0x3 line.long 0x0 "OTG_HS_DTXFSTS5,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x0 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" group.long 0x130++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ1,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x150++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ2,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x170++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ3,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x190++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ4,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1B0++0x3 line.long 0x0 "OTG_HS_DIEPTSIZ5,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x300++0x3 line.long 0x0 "OTG_HS_DOEPCTL0,OTG_HS device control OUT endpoint 0 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" rbitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" newline bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" rbitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" rbitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" rbitfld.long 0x0 0.--1. "MPSIZ,Maximum packet size" "0,1,2,3" group.long 0x320++0x3 line.long 0x0 "OTG_HS_DOEPCTL1,OTG device endpoint-1 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x340++0x3 line.long 0x0 "OTG_HS_DOEPCTL2,OTG device endpoint-2 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x360++0x3 line.long 0x0 "OTG_HS_DOEPCTL3,OTG device endpoint-3 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x308++0x3 line.long 0x0 "OTG_HS_DOEPINT0,OTG_HS device endpoint-0 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x328++0x3 line.long 0x0 "OTG_HS_DOEPINT1,OTG_HS device endpoint-1 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x348++0x3 line.long 0x0 "OTG_HS_DOEPINT2,OTG_HS device endpoint-2 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x368++0x3 line.long 0x0 "OTG_HS_DOEPINT3,OTG_HS device endpoint-3 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x388++0x3 line.long 0x0 "OTG_HS_DOEPINT4,OTG_HS device endpoint-4 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3A8++0x3 line.long 0x0 "OTG_HS_DOEPINT5,OTG_HS device endpoint-5 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3C8++0x3 line.long 0x0 "OTG_HS_DOEPINT6,OTG_HS device endpoint-6 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x3E8++0x3 line.long 0x0 "OTG_HS_DOEPINT7,OTG_HS device endpoint-7 interrupt" bitfld.long 0x0 14. "NYET,NYET interrupt" "0,1" bitfld.long 0x0 6. "B2BSTUP,Back-to-back SETUP packets" "0,1" bitfld.long 0x0 4. "OTEPDIS,OUT token received when endpoint" "0,1" bitfld.long 0x0 3. "STUP,SETUP phase done" "0,1" bitfld.long 0x0 1. "EPDISD,Endpoint disabled" "0,1" newline bitfld.long 0x0 0. "XFRC,Transfer completed" "0,1" group.long 0x310++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ0,OTG_HS device endpoint-0 transfer size" bitfld.long 0x0 29.--30. "STUPCNT,SETUP packet count" "0,1,2,3" bitfld.long 0x0 19. "PKTCNT,Packet count" "0,1" hexmask.long.byte 0x0 0.--6. 1. "XFRSIZ,Transfer size" group.long 0x330++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ1,OTG_HS device endpoint-1 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x350++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ2,OTG_HS device endpoint-2 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x370++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ3,OTG_HS device endpoint-3 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x390++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ4,OTG_HS device endpoint-4 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x1A0++0xF line.long 0x0 "OTG_HS_DIEPTSIZ6,OTG_HS device endpoint transfer size" bitfld.long 0x0 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" line.long 0x4 "OTG_HS_DTXFSTS6,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0x4 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" line.long 0x8 "OTG_HS_DIEPTSIZ7,OTG_HS device endpoint transfer size" bitfld.long 0x8 29.--30. "MCNT,Multi count" "0,1,2,3" hexmask.long.word 0x8 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x8 0.--18. 1. "XFRSIZ,Transfer size" line.long 0xC "OTG_HS_DTXFSTS7,OTG_HS device IN endpoint transmit FIFO" hexmask.long.word 0xC 0.--15. 1. "INEPTFSAV,IN endpoint TxFIFO space" group.long 0x380++0x3 line.long 0x0 "OTG_HS_DOEPCTL4,OTG device endpoint-4 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3A0++0x3 line.long 0x0 "OTG_HS_DOEPCTL5,OTG device endpoint-5 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3C0++0x3 line.long 0x0 "OTG_HS_DOEPCTL6,OTG device endpoint-6 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3E0++0x3 line.long 0x0 "OTG_HS_DOEPCTL7,OTG device endpoint-7 control" bitfld.long 0x0 31. "EPENA,Endpoint enable" "0,1" bitfld.long 0x0 30. "EPDIS,Endpoint disable" "0,1" bitfld.long 0x0 29. "SODDFRM,Set odd frame" "0,1" bitfld.long 0x0 28. "SD0PID_SEVNFRM,Set DATA0 PID/Set even" "0,1" bitfld.long 0x0 27. "SNAK,Set NAK" "0,1" newline bitfld.long 0x0 26. "CNAK,Clear NAK" "0,1" bitfld.long 0x0 21. "Stall,STALL handshake" "0,1" bitfld.long 0x0 20. "SNPM,Snoop mode" "0,1" bitfld.long 0x0 18.--19. "EPTYP,Endpoint type" "0,1,2,3" rbitfld.long 0x0 17. "NAKSTS,NAK status" "0,1" newline rbitfld.long 0x0 16. "EONUM_DPID,Even odd frame/Endpoint data" "0,1" bitfld.long 0x0 15. "USBAEP,USB active endpoint" "0,1" hexmask.long.word 0x0 0.--10. 1. "MPSIZ,Maximum packet size" group.long 0x3B0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ5,OTG_HS device endpoint-5 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x3D0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ6,OTG_HS device endpoint-6 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" group.long 0x3F0++0x3 line.long 0x0 "OTG_HS_DOEPTSIZ7,OTG_HS device endpoint-7 transfer size" bitfld.long 0x0 29.--30. "RXDPID_STUPCNT,Received data PID/SETUP packet" "0,1,2,3" hexmask.long.word 0x0 19.--28. 1. "PKTCNT,Packet count" hexmask.long.tbyte 0x0 0.--18. 1. "XFRSIZ,Transfer size" tree.end endif tree "OTG1_HS_PWRCLK" base ad:0x40040E00 group.long 0x0++0x3 line.long 0x0 "OTG_HS_PCGCR,Power and clock gating control" bitfld.long 0x0 4. "PHYSUSP,PHY suspended" "0,1" bitfld.long 0x0 1. "GATEHCLK,Gate HCLK" "0,1" bitfld.long 0x0 0. "STPPCLK,Stop PHY clock" "0,1" tree.end tree.end tree "VREFBUF (Voltage Reference Buffer)" base ad:0x58003C00 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")||cpuis("STM32H742*")||cpuis("STM32H743*")||cpuis("STM32H745??-CM4")||cpuis("STM32H745??-CM7")||cpuis("STM32H747??-CM4")||cpuis("STM32H747??-CM7")) group.long 0x0++0x7 line.long 0x0 "CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H750*")) group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H753*")) group.long 0x0++0x7 line.long 0x0 "CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H755??-CM4")) group.long 0x0++0x7 line.long 0x0 "CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H755??-CM7")) group.long 0x0++0x7 line.long 0x0 "CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H757??-CM4")) group.long 0x0++0x7 line.long 0x0 "CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H757??-CM7")) group.long 0x0++0x7 line.long 0x0 "CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H7A3*")) group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status" bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H7B0*")) group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status" hexmask.long.byte 0x0 4.--7. 1. "VRS,Voltage reference scale These bits" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif sif (cpuis("STM32H7B3*")) group.long 0x0++0x7 line.long 0x0 "VREFBUF_CSR,VREFBUF control and status" hexmask.long.byte 0x0 4.--7. 1. "VRS,Voltage reference scale These bits" rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1" newline bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1" bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1" line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control" hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are" endif tree.end tree "WWDG (Window Watchdog)" base ad:0x0 sif (cpuis("STM32H723*")||cpuis("STM32H725*")||cpuis("STM32H730*")||cpuis("STM32H733*")||cpuis("STM32H735*")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H742*")) tree "WWDG" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H743*")) tree "WWDG" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H745??-CM4")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H745??-CM7")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H747??-CM4")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H747??-CM7")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H750*")) tree "WWDG" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "WWDG_CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "WWDG_CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "WWDG_SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H753*")) tree "WWDG" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H755??-CM4")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H755??-CM7")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H757??-CM4")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "WWDG1" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H757??-CM7")) tree "WWDG2" base ad:0x40002C00 group.long 0x0++0xB line.long 0x0 "CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H7A3*")) tree "WWDG" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "WWDG_CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "WWDG_CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "WWDG_SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H7B0*")) tree "WWDG" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "WWDG_CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "WWDG_CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "WWDG_SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif sif (cpuis("STM32H7B3*")) tree "WWDG" base ad:0x50003000 group.long 0x0++0xB line.long 0x0 "WWDG_CR,Control register" bitfld.long 0x0 7. "WDGA,Activation bit This bit is set by" "0,1" hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB) These bits" line.long 0x4 "WWDG_CFR,Configuration register" bitfld.long 0x4 11.--12. "WDGTB,Timer base The time base of the" "0,1,2,3" bitfld.long 0x4 9. "EWI,Early wakeup interrupt When set an" "0,1" hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value These bits contain" line.long 0x8 "WWDG_SR,Status register" bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag This bit is" "0,1" tree.end endif tree.end AUTOINDENT.OFF